Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F76xxx and STM32F77xxx microcontroller memory and peripherals.

The STM32F76xxx and STM32F77xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm^® Cortex^®-M7 with FPU core, refer to the Cortex^®-M7 with FPU Technical Reference Manual.
Related documents

Available from STMicroelectronics web site www.st.com:

• STM32F76xxx and STM32F77xxx datasheets
  
• STM32F7 Series Cortex^®-M7 processor programming manual (PM0253)
  

1 Documentation conventions

1.1 General information

The STM32F76xxx and STM32F77xxx devices have an Arm^®(a) Cortex^®-M7 core.

1.2 List of abbreviations for registers

The following abbreviations^(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.

write-only (w) Software can only write to this bit. Reading this bit returns the reset value.

read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.

read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.

read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.

read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value.

read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value.

read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit value.

read/write once (rwo) Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value.

toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.

read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.

Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STM microcontrollers, some of them may not be used in the current document.

1.3 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

• The CPU core integrates two debug ports:
  
  • JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol.
    

  • SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.
    

    For both the JTAG and SWD protocols, refer to the Cortex^®-M7 Technical Reference Manual.
    

• Word: data of 32-bit length.
  
• Half-word: data of 16-bit length.
  
• Byte: data of 8-bit length.
  
• Double word: data of 64-bit length.
  
• IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.
  
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board.
  
• Option bytes: product configuration bits stored in the Flash memory.
  
• AHB: advanced high-performance bus.
  
• AHBS: AHB Slave bus.
  
• AXIM: AXI master bus.
  
• ITCM: Instruction Tighly Coupled Memory.
  
• DTCM: Data Tighly Coupled Memory.
  
• CPU: refers to the Cortex^®-M7 core.
  

1.4 Peripheral availability

For peripheral availability and number across all sales types, refer to the particular device datasheet.

2 System and memory overview

2.1 System architecture

The main system architecture is based on 2 sub-systems:

• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
  
  • 1x AXI to 64-bit AHB bridge connected to the embedded flash
    
  • 3x AXI to 32bit AHB bridge connected to AHB bus matrix
    
• A multi-AHB Bus-Matrix
  

The multi-AHB Bus-Matrix interconnects all the masters and slaves and it consists on:

• 32-bit multi-AHB Bus-Matrix
• 64-bit multi-AHB Bus-Matrix: It interconnects the 64-bit AHB bus from CPU through the AXI to AHB bridge and the 32-bit AHB bus from GP DMAs and peripheral DMAs upsized to 64-bit to the internal flash.

The multi AHB bus matrix interconnects:

• 12 bus masters:
  
  • 3x32-bit AHB bus Cortex^®-M7 AXI Master bus 64-bits, splitted 4 masters through the AXI to AHB bridge.
    
  • 1x64-bit AHB bus connected to the embedded flash
    
  • Cortex^® -M7 AHB Peripherals bus
  • DMA1 memory bus
    
  • DMA2 memory bus
    
  • DMA2 peripheral bus
    
  • Ethernet DMA bus
    
  • USB OTG HS DMA bus
    
  • LCD Controller DMA-bus
    
  • Chrom-Art Accelerator™ (DMA2D) memory bus
• Eight bus slaves:
  
  • the embedded Flash on AHB bus (for Flash read/write access, for code execution and data access)
  • Cortex^®-M7 AHBS slave interface for DMAs data transfer on DTCM RAM only.
    
  • Main internal SRAM1 (368 KB)
    
  • Auxiliary internal SRAM2 (16 KB)
    
  • AHB1peripherals including AHB to APB bridges and APB peripherals
    
  • AHB2 peripherals
    
  • FMC
  • Quad-SPI
    

2.1.1 Multi AHB BusMatrix

The multi AHB BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm.

It provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. The DTCM and ITCM RAMs (tightly coupled memories) are not part of the bus matrix.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave bus of the CPU. The instruction TCM RAM is reserved only for CPU. it is accessed at CPU clock speed with 0 wait states. The architecture is shown in Figure 1.

2.1.2 AHB/APB bridges (APB)

The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to Table 1 for the address mapping of AHB and APB peripherals.

After each device reset, all peripheral clocks are disabled (except for the SRAM, DTCM, ITCM RAM and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR or RCC_APBxENR register.

Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.1.3 CPU AXIM bus

This bus connects the Cortex^®-M7 with FPU core to the multi-AHB Bus-Matrix through AXI to AHB bridge. There are 4 AXI bus targets:

• CPU AXI bus access 1: The target of this AXI bus is the external memory FMC containing code or data. For the NAND Bank mapped at address 0x8000 0000 to 0x8FFF FFFF, the MPU memory attribute for this space must be reconfigured by software to Device.
  
• CPU AXI bus access 2: The target of this AXI bus is the external memory Quad-SPI containing code or data.
  
• CPU AXI bus access 3: The target of this AXI bus is the internal SRAMs (SRAM1 and SRAM2) containing code or data.
• CPU AXI bus access 4: The target of this AXI bus is the embedded Flash mapped on AXI interface containing code or data.

2.1.4 ITCM bus

This bus is used by the Cortex^®-M7 and AHBS for instruction fetches and data access on the embedded flash mapped on ITCM interface and instruction fetches and data access on ITCM RAM.

2.1.5 DTCM bus

This bus is used by the Cortex^®-M7 for data access on the DTCM RAM. It can be also used for instruction fetches.

2.1.6 CPU AHBS bus

This bus connects the AHB Slave bus of the Cortex^®-M7 to the BusMatrix. This bus is used by DMAs and Peripherals DMAs for Data transfer on DTCM RAM only.

The ITCM bus is not accessible on AHBS. So the DMA data transfer to/from ITCM RAM is not supported. For DMA transfer to/from Flash on ITCM interface, all the transfers are forced through AHB bus

2.1.7 AHB peripheral bus

This bus connects the AHB Peripheral bus of the Cortex^®-M7 to the BusMatrix. This bus is used by the core to perform all data accesses to peripherals.

The target of this bus is the AHB1 peripherals including the APB peripherals and the AHB2 peripherals.

2.1.8 DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the DMA to perform transfer to/from memories. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex^®-M7) internal Flash memory and external memories through the FMC or Quad-SPI.

2.1.9 DMA peripheral bus

This bus connects the DMA peripheral master bus interface to the AHB-to-APB bridges or the BusMatrix. This bus is used by the DMA to access peripherals or to perform memory-to-memory transfers. The targets of this bus are the APB peripherals plus AHB peripherals and data memories (internal SRAM1, SRAM2 and DTCM internal Flash memory and external memories through the FMC or Quad-SPI) for DMA2.

2.1.10 Ethernet DMA bus

This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by the Ethernet DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex^®-M7) internal Flash memory, and external memories through the FMC or Quad-SPI.

2.1.11 USB OTG HS DMA bus

This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex^®-M7), internal Flash memory, and external memories through the FMC or Quad-SPI.

2.1.12 LCD-TFT controller DMA bus

This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by the LCD-TFT DMA to load data from a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex^®-M7), external memories through FMC or Quad-SPI, and internal Flash memory.

2.1.13 DMA2D bus

This bus connect the DMA2D master interface to the BusMatrix. This bus is used by the DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex^®-M7), external memories through FMC or Quad-SPI, and internal Flash memory.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.

2.2.2 Memory map and register boundary addresses

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

2.3 Embedded SRAM

The STM32F76xxx and STM32F77xxx feature:

• System SRAM up to 512 Kbytes including Data TCM RAM 128 Kbytes
  
• Instruction RAM (ITCM-RAM) 16 Kbytes.
  
• 4 Kbytes of backup SRAM (see section 5.1.2: Battery backup domain)
  

The embedded SRAM is divided into up to four blocks:

• System SRAM:
  
  • SRAM1 mapped at address 0x2002 0000 and accessible by all AHB masters from AHB bus Matrix.
  • SRAM2 mapped at address 0x2007 C000 and accessible by all AHB masters from AHB bus Matrix.
    
  • DTCM-RAM on TCM interface (Tightly Coupled Memory interface) mapped at address 0x2000 0000 and accessible by all AHB masters from AHB bus Matrix but through a specific AHB slave bus of the CPU.
    
• Instruction SRAM:
  
  • Instruction RAM (ITCM-RAM) mapped at address 0x0000 0000 and accessible only by CPU.
    

The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32 bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full words (32 bits) or double words (64 bits).

2.4 Flash memory overview

The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with ART on TCM interface or L1-
Cache on AXIM interface.

The Flash memory is organized as follows:

• A main memory block divided into sectors.
  
• A second block:
  • System memory from which the device boots in System memory boot mode
    
  • 1024 OTP (one-time programmable) bytes for user data.
    
  • Option bytes to configure read and write protection, BOR level, software/hardware watchdog, boot memory base address and reset when the device is in Standby or Stop mode.
    

Refer to Section 3: Embedded Flash memory (FLASH) for more details.

2.5 Boot configuration

In the STM32F76xxx and STM32F77xxx, two different boot areas can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 2.

The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset.

The BOOT pin is also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode.

After startup delay, the selection of the boot area is done before releasing the processor reset.

The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:

• All Flash address space mapped on ITCM or AXIM interface
  
• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
  
• The System memory bootloader
  

The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot from any other boot address after next reset.

If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows:

• Boot address 0: ITCM-FLASH at 0x0020 0000
  
• Boot address 1: ITCM-RAM at 0x0000 0000
  

When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface) or system bootloader will be available. If the already programmed boot address in the BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at address 0x00200000.

When the device is in Dual bank mode (nDBANK =0) the application software can either boot from bank 1 or from bank 2. By default Dual boot is desactivated.

To select boot from the Flash memory bank 2, program the nDBOOT bit in the user option bytes. When this bit is reset (nDBOOT =0) and the BOOT pin selects an address in the Flash memory range, the device boots from system memory, and the bootloader jumps to execute the user application programmed in the Flask memory bank 2. For further details, please refer to the application note (AN2606).

Embedded bootloader

The embedded bootloader code is located in the system memory. It is programmed by ST during production. For full information, refer to the application note (AN2606) STM32 microcontroller system memory boot mode.

By default, when the boot from system bootloader is selected, the code is executed from TCM interface. It could be executed from AXIM interface by reprogramming the BOOT_ADDx address option bytes to 0x1FF0 0000.

3 Embedded Flash memory (FLASH)

3.1 Introduction

The Flash memory interface manages Cortex^®-M7 AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.

The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines on ITCM interface (ART Accelerator™).

3.2 Flash main features

• Flash memory read operations with two data width modes supported:
  • Single bank mode nDBANK=1: read access of 256 bits
  • Dual bank mode nDBANK=0: read access of 128 bits
    
• Flash memory program/erase operations
  
• Read / write protections
  
• Read While Write (RWW) (only possible in dual bank mode nDBANK=0)
  
• Dual Boot mode (only possible in dual bank mode nDBANK=0)
  
• ART Accelerator™: 64 cache lines of 128/256 bits on ITCM interface (depending on read access width)
  
• Prefetch on TCM instruction code
  

Figure 3 shows the Flash memory interface connection inside the system architecture.

3.3 Flash functional description

3.3.1 Flash memory organization

The Flash memory has the following main features:

• Capacity up to 2 Mbytes, in single bank mode (read width 256 bits) or in dual bank mode (read width 128 bits)
  
• Supports dual boot mode thanks to nDBOOT option bit (only in dual bank mode nDBANK=0)
  
• 256 bits wide data read in single bank mode or 128 bits wide data read in dual bank configuration
  
• Byte, half-word, word and double word write
  
• Sector, mass erase and bank mass erase (only in dual bank mode)

The Flash memory is organized as follows:

• Main memory organization depends on dual bank configuration bit:
  • When the dual bank mode is disabled (nDBANK bit is set), the main memory block is divided into 4 sectors of 32 Kbytes, 1 Sector of 128 Kbytes, and 7 sectors of 256 Kbytes
    

  • In dual bank mode (nDBANK bit is reset), the main memory is divided into two banks of 1 Mbyte. Each 1 Mbyte bank is composed of 4 sectors of 16 Kbytes, 1 Sector of 64 Kbytes and 7 sectors of 128 Kbytes
    

    - If nDBANK=1, Size of main memory block: 4 sectors of 32 KBytes, 1 sector of 128 KBytes, 7 sectors of 256 KBytes (reference to memory organization)
    

    - If nDBANK=0, Each 1MB banks is composed of: 4 sectors of 16 KBytes, 1 sector of 64 KBytes, 7 sectors of 128 KBytes (reference to memory organization)
    

• Dual bank organization on 1 Mbyte devices
  

  The dual bank feature on 1 Mbyte devices is available. it is enabled by setting the nDBANK option bit to 0.
  

  To obtain a dual bank Flash memory, the last 512 Kbytes of the single bank (sectors [8:11]) are re-structured in the same way as the first 512 Kbytes.
  

  The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 12 sectors whereas the dual bank memory contains 16 sectors (see Table 6).
  

  For erase operation, the right sector numbering must be considered according to nDBANK option bit.
  

  • When the nDBANK bit is set (single bank mode), the erase operation must be performed on the default sector number.
    

  • When the nDBANK bit is reset, to perform an erase operation on bank 2, the sector number must be programmed (sector number from 12 to 19). Refer to FLASH_CR register for SNB (Sector number) configuration.
    

    Refer to Table 5: 1 Mbyte Flash memory single bank organization (256 bits read
    width) and Table 6: 1 Mbyte Flash memory dual bank organization (128 bits read

width) for details on 1 Mbyte single bank and 1 Mbyte dual bank organizations.

• Information blocks containing:
  • System memory from which the device boots in System memory boot mode
    
  • 1024 OTP (one-time programmable) for user data
    
  • The OTP area contains 16 additional bytes used to lock the corresponding OTP data block.
    
  • Option bytes to configure read and write protection, BOR level, watchdog, boot memory base address, software/hardware and reset when the device is in Standby or Stop mode.
    

On 1 Mbyte devices the main memory block is divided into 4 sectors of 32 Kbytes, 1 sector of 128 Kbytes, and 3 sectors of 256 Kbytes. The dual bank feature is also available.

To obtain a dual bank Flash memory, the main memory block is re-structured in the a way that the first and last 512 Kbytes of each bank has the same structure.

The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 8 continuous sector numbers whereas the dual bank memory contains 16 sectors with discontinuity on sector numbering for each 512 Kbytes (see Table 5: 1 Mbyte Flash memory single bank organization (256 bits read width)).

For erase operation, the right sector numbering must be considered according to the dual bank nDBANK option bit.

• When the nDBANK bit is set (single bank configuration), the erase operation must be performed on the default sector number.
  
• When the nDBANK bit is reset (dual bank configuration), to perform an erase operation on bank 2, the sector number must be programmed (sector number from 12 to 19). Refer to FLASH_CR register for SNB (Sector number) configuration.
  

The embedded Flash has three main interfaces:

• 64-bits ITCM interface:
  
  • It is connected to the ITCM bus of Cortex-M7 and used for instruction execution and data read access.
  • Write accesses are not supported on ITCM interface
    
  • Supports a unified 64 cache lines (ART accelerator). The cache line size depends on nDBANK option bit, 256 bits width when in single bank configuration and 128 bits width in dual bank configuration
    
• 64-bits AHB interface:
  
  • It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used for code execution, read and write accesses.
    
  • DMAs and peripherals DMAs data transfer on Flash are done through the AHB interface whatever the addressed flash interface TCM or AHB.
    
• 32-bits AHB register interface:
  
  • It is used for control and status register accesses.
    

The main memory and information block organization is shown in the following tables:

3.3.2 Read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.

The correspondence between wait states and CPU clock frequency is given in Table 13 and Table 7.

Note: - When VOS[1:0] = '0x01', the maximum value of f_HCLK is 144 MHz.

- When VOS[1:0] = '0x10', the maximum value of f_HCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode.

- When VOS[1:0] = '0x11, the maximum value of f_HCLK is 180 MHz. It can be extended to
216 MHz by activating the over-drive mode.

- The over-drive mode is not available when V_DD ranges from 1.8 to 2.1 V.

Refer to Section 4.1.6: Voltage regulator for details on how to activate the over-drive mode.

After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the FLASH_ACR register.

It is highly recommended to use the following software sequences to tune the number of wait states to access the Flash memory with the CPU frequency.

Increasing the CPU frequency

1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR register
   
2. Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register
   
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
   
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
   
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
   

Decreasing the CPU frequency

1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
   
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
   
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register
   
4. Program the new number of wait states to the LATENCY bits in FLASH_ACR
   
5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register
   

Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have

configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.

Instruction prefetch

Depending on Flash dual bank mode configuration, each flash read operation provides:

In case of single bank mode (nDBANK option bit is set) 256 bits representing 8 instructions of 32 bits to 16 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 8 CPU cycles are needed to execute the previous instruction line read.

When in dual bank mode (nDBANK option bit is reset) 128 bits representing 4 instructions of 32 bits to 8 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 4 CPU cycles are needed to execute the previous instruction line read. The prefetch on ITCM bus allows to read the sequential next line of instructions in the flash while the current instruction line is requested by the CPU. The prefetch can be enabled by setting the PRFTEN bit of the FLASH_ACR register. This feature is useful if at least one Wait State is needed to access the flash. When the code is not sequential (branch), the instruction may not be present neither in the current instruction line used nor in the prefetched instruction line. In this case (miss), the penalty in term of number of cycles is at least equal to the number of Wait States.

Adaptive real-time memory accelerator (ART Accelerator™)

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm^® Cortex^®-M7 with FPU processors. It balances the inherent performance advantage of the Arm^® Cortex^®-M7 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies.

To release the processor full performance, the accelerator implements a unified cache of an instruction and branch cache which increases program execution speed from the Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 216 MHz.

The ART accelerator is available only for flash access on ITCM interface.

To limit the time lost due to jumps, it is possible to retain 64 lines of 256 bits (when in single bank mode configuration nDBANK=1 or 128 bits in dual bank configuration with nDBANK=0) in the ART accelerator. This feature can be enabled by setting the ARTEN bit of the FLASH_CR register. The ART Accelerator is unified, it contains instruction as well as data literal pools. Each time a miss occurs (requested data not present in the current data line used or in the instruction cache memory), the read line is copied in the instruction cache memory of ART. If a data contained in the instruction cache memory is requested by the CPU, the data is provided without inserting delay. Once all the cache memory lines are filled, the LRU (Least Recently Used) policy is used to determine the line to replace in the memory cache. This feature is particularly useful in case of code containing loops.

Note: Data in user configuration sector are not cacheable.

3.3.3 Flash program and erase operations

For any Flash memory program operation (erase or program), the CPU clock frequency (HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation.

Any attempt to read the Flash memory while it is being written or erased, causes the bus to stall. Read operations are processed correctly once the program operation has completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing.

3.3.4 Unlocking the Flash control register

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register:

1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
   
2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
   

Any wrong sequence will return a bus error and lock up the FLASH_CR register until the next reset.

The FLASH_CR register can be locked again by software by setting the LOCK bit in the FLASH_CR register.

Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.

3.3.5 Program/erase parallelism

The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external V_PP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register before any programming/erasing operation.

A Flash memory erase operation can only be performed by sector, bank or for the whole Flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet.

Table 8 provides the correct PSIZE values.

Note: Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.

To use V_PP, an external high-voltage supply (between 8 and 9 V) must be applied to the V_PP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The V_PP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.

3.3.6 Switching from single bank to dual bank configuration

It is possible to use main Flash either in single bank mode (256 bits read width) or dual bank mode (128 bits read width) thanks to nDBANK option bit. However, it is highly recommended to use the following sequence when switching from a mode to an other.

Activating dual bank mode (switching from nDBANK=1 to nDBANK=0)

When switching from one Flash mode to another (single to dual Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when the memory organization is changed any access (CPU or DMAs) to Flash memory should be avoided before reprogramming.

1. Depending on execution path:
   

If ITCM path is used for code execution:

1. Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator reset PRFTEN and ARTEN bits in FLASH_ACR register
   
2. Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR register)
   

If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed).

2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to Section 3.4.2: Option bytes programming)
   

Note: The memory organization is changed and previously data in Flash memory is corrupted.

3. Program new application:
   
   1. Erase needed memory (Sectors, or Mass erase)
      
   2. Reprogram the Flash memory
      

   3. If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections)
      

      -> the new software is ready to be run using bank configuration
      

De-activating dual bank mode (switching from nDBANK=0 to nDBANK=1)

When switching from one Flash mode to another (dual to single Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when memory organization is changed any access (CPU or DMAs) to Flash memory should be avoided before reprogramming.

1. Depending on execution path:
   

If ITCM path is used for code execution:

1. Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator reset PRFTEN and ARTEN bits in FLASH_ACR register
   
2. Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR register)
   

If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed)

2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to Section 3.4.2: Option bytes programming)
   

Note: The memory organization is changed and previously data in Flash memory is corrupted.

3. Program new application:
   
   1. Erase needed memory (Sectors, or Mass erase)
      
   2. Reprogram the Flash memory
      

   3. If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections)

      -> The new software is ready to be run using single bank configuration
      

3.3.7 Flash erase sequences

The Flash memory erase operation can be performed at sector level, at bank level (bank mass erase when dual bank mode is enabled nDBANK=0) or on the whole Flash memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector.

Sector Erase

To erase a sector, follow the procedure below:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
   
2. Set the SER bit and select the sector out of the 8 in the main memory block) you wish to erase (SNB) in the FLASH_CR register
   
3. Set the STRT bit in the FLASH_CR register
   
4. Wait for the BSY bit to be cleared
   

Bank Mass Erase (available only in dual bank mode when nDBANK=0)

To perform mass erase on Bank 1 or Bank 2, the procedure below should be followed:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
   
2. Set accordingly MER/MER1 OR MER2 bit in the FLASH_CR register
   
3. Set the STRT bit in the FLASH_CR register
   
4. Wait for the BSY bit to be reset
   
5. Reset accordingly MER/MER1 OR MER2 bit in the FLASH_CR register

Mass Erase

To perform Mass Erase, the following sequence is recommended depending on nDBANK option bit:

• When dual bank mode is active (nDBANK=0) :
  

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
   
2. Set the MER/MER1 AND MER2 bit in the FLASH_CR register
   
3. Set the STRT bit in the FLASH_CR register
   
4. Wait for the BSY bit to be reset
   
5. Reset the MER/MER1 AND MER2 bit in the FLASH_CR register
   

• When single bank mode is active (nDBANK=1) :
  

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
   
2. Set the MER/MER1 bit in the FLASH_CR register
   
3. Set the STRT bit in the FLASH_CR register
   
4. Wait for the BSY bit to be cleared If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
   

Note: If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.

If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.

Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.

3.3.8 Flash programming sequences

Standard programming

The Flash memory programming sequence is as follows:

1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
   
2. Set the PG bit in the FLASH_CR register
   
3. Perform the data write operation(s) to the desired memory address (inside main memory block or OTP area):
   
   • Byte access in case of x8 parallelism
     
   • Half-word access in case of x16 parallelism
     
   • Word access in case of x32 parallelism
     
   • Double word access in case of x64 parallelism
     
4. Wait for the BSY bit to be cleared.
   

Note: Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.

If an erase and a program operation are requested simultaneously, the erase operation is
performed first.

Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.

Programming errors

In case of error, the Flash operation (programming or erasing) is aborted with one of the following errors:

• PGAERR: Alignment Programming error
  

  It is not allowed to program data to the Flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and the program alignment error flag (PGAERR) is set in the FLASH_SR register.
  

• PGEPRR: Programming parallelism error
  

  The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and the program parallelism error flag (PGPERR) is set in the FLASH_SR register.
  

• ERSERR: Erase sequence error

  When an erase operation to the flash is performed by the code while the control register has not been correctly configured, the ERSERR error flag is set
  

• WRPERR: Write Protection Error
  

  WRPERR is set if one of the following conditions occurs:
  

  • Attempt to program or erase in a write protected area (WRP)
  • Attempt to program or erase the system memory area.
    
  • A write in the OTP area which is already locked
    
  • Attempt to modify the option bytes when the read protection (RDP) is set to Level
    
  • The Flash memory is read protected and an intrusion is detected
    

If a part of code is programmed in the flash, the user must guarantee that this part of code has not been executed since the last reset. If this condition can not be filled safely, it is recommended to flush the Caches.

1. ART accelerator flush and/or desactivate is performed by setting respectively the bits ARTRST and/or ARTEN of the FLASH_CR register.
2. Perform CPU Cache maintenance operations
   

If a flash program or erase operation hits one or several data section already loaded in the cache, it is the responsibility of the user to guarantee that these data will not be accessed during code execution. Therefore during these operations, it is recommended to flush and/or deactivate the Caches.

Note: Data coherency between caches and Flash memory is the responsibility of the user code

Note: The ART cache can be flushed only if the ART accelerator is disabled (ARTEN = 0).

Read-while-write (RWW)

Thanks to the dual bank mode (active when nDBANK option bit is 0), the Flash memory structure allows read-while-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank.

Note: Write-while-write operations are not allowed. As an exampled, It is not possible to perform
an erase or program operation on one bank while erasing or programming the other one,
except mass erase which erase both banks at same time

Read from bank 1 while erasing bank 2

While executing a program code from bank 1, it is possible to perform an erase operation on bank 2 (and vice versa). Follow the procedure below:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is on going to bank 1 or bank 2)
   
2. Set MER/MER1 or MER2 bit in the FLASH_CR register
   
3. Set the STRT bit in the FLASH_CR register
   
4. Wait for the BSY bit to be reset (or use the EOP interrupt).
   

Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.

Read from bank 1 while programming bank 2

While executing a program code (instruction fetch) from bank 1,it is possible to perform an program operation to the bank 2 (and vice versa). Follow the procedure below:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is on going on bank 1 or bank 2)
   
2. Set the PG bit in the FLASH_CR register
   
3. Perform the data write operation(s) to the desired memory address inside main memory block or OTP area
   
4. Wait for the BSY bit to be reset.
   

Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.

3.3.9 Flash Interrupts

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables interrupt generation when an erase or program operation ends, that is when the busy bit (BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this case, the end of operation (EOP) bit in the FLASH_SR register is set.

If an error occurs during a program, an erase, or a read operation request, one of the following error flags is set in the FLASH_SR register:

• PGAERR, PGPERR, ERSERR (Program error flags)
  
• WRPERR (Protection error flag)
  

In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.

Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.

3.4 FLASH Option bytes

3.4.1 Option bytes description

The option bytes are configured by the end user depending on the application requirements. Table 10 shows the organization of these bytes inside the information block.

The option bytes can be read from the user configuration memory locations or from the Option byte registers:

• Flash option control register (FLASH_OPTCR)
  
• Flash option control register (FLASH_OPTCR1)
  

User and read protection options bytes

Memory address: 0x1FFF 0000

ST programmed value: 0x5500AAFF

User and write protection options bytes

Memory address: 0x1FFF 0008

ST programmed value: 0x0000FFFF

Boot address option bytes when Boot pin =0

Memory address: 0x1FFF 0010

ST programmed value: 0xFF7F 0080 (ITCM-FLASH base address)

Boot address option bytes when Boot pin =1

Memory address: 0x1FFF 0018

ST programmed value: 0xFFBF0040 (system memory bootoader address)

3.4.2 Option bytes programming

To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have to perform the following sequence:

1. Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)
   
2. Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)
   

The user option bytes can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

Modifying user option bytes

To modify the user option value, follow the sequence below:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
   
2. Write the desired option value in the FLASH_OPTCR register.
   
3. Set the option start bit (OPTSTRT) in the FLASH_OPTCR register
   
4. Wait for the BSY bit to be cleared.
   

Note: The value of an option is automatically modified by first erasing the information block and
then programming all the option bytes with the values contained in the FLASH_OPTCR
register.

Note: When setting the OPTSTRT bit in the FLASH_OPTCR register and before polling the BSY
bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a
previous access to the FLASH_OPTCR register.

3.5 FLASH memory protection

3.5.1 Read protection (RDP)

The user area in the Flash memory can be protected against read operations by an entrusted code. Three read protection levels are defined:

• Level 0: no read protection
  

  When the read protection level is set to Level 0 by writing 0xAA into the read protection option byte (RDP), all read/write operations (if no write protection is set) from/to the Flash memory or the backup SRAM are possible in all boot configurations (Flash user boot, debug or boot from RAM).
  

• Level 1: read protection enabled
  

  It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:
  

  • No access (read, erase, program) to Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader. A bus error is generated in case of read request.
  • When booting from Flash memory, accesses (read, erase, program) to Flash memory and backup SRAM from user code are allowed.

  When Level 1 is active, programming the protection option byte (RDP) to Level 0 causes the Flash memory and the backup SRAM to be mass-erased. As a result the user code area is cleared before the read protection is removed. The mass erase only erases the user code area. The other option bytes including write protections remain unchanged from before the mass-erase operation. The OTP area is not affected by mass erase and remains unchanged. Mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.
  

• Level 2: debug/chip read disabled
  

  The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When the read protection Level 2 is set:
  

  • All protections provided by Level 1 are active.
  • Booting from RAM or system memory bootloader is no more allowed.
    
  • JTAG, SWV (serial-wire viewer), ETM, and boundary scan are disabled.
    
  • User option bytes can no longer be changed.
    
  • When booting from Flash memory, accesses (read, erase and program) to Flash memory and backup SRAM from user code are allowed.
    

  Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.
  

Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.

Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply
a POR (power-on reset).

1. The main Flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.

Figure 4 shows how to go from one RDP level to another.

3.5.2 Write protections

User sectors in the Flash memory can be protected against unwanted write operations due to loss of program counter contexts. When the non-write protection nWRPi bits in the FLASH_OPTCR register is low, the corresponding sector cannot be erased or programmed.

If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.

Write protection user options in single bank mode (nBANK=1)

The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:

nWRP[0] bit is write protection bit for sector 0

nWRP[1] bit is write protection bit for sector 1

...

nWRP[5] bit is write protection bit for sector 5

nWRP[6] bit is write protection bit for sector 6

nWRP[7] bit is write protection bit for sector 7

...

nWRP[11] bit is write protection bit for sector 11

When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.

Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection user options in dual bank mode (nBANK=0)

The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:

nWRP[0] bit is write protection bit for bank 1 sector 0/ sector 1

nWRP[1] bit is write protection bit for bank 1 sector 2/ sector 3

...

nWRP[5] bit is write protection bit for bank 1 sector 10/ sector 11

nWRP[6] bit is write protection bit for bank 2 sector 12/ sector 13

nWRP[7] bit is write protection bit for bank 2 sector 14/ sector 15

...

nWRP[11] bit is write protection bit for bank 2 sector 22/ sector 23

When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.

Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection error flag

If an erase/program operation to a write protected part of the Flash memory is performed, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.

If an erase operation is requested, the WRPERR bit is set when:

When in single bank mode (nDBANK=1)

• A sector erase is requested and the Sector Number SNB field is not valid
• A mass erase is requested while at least one of the user sector is write protected by option bit (MER/MER1 = 1 and nWRPi = 0 with 0 <= i <= 11 bits in the FLASH_OPTCR register)
  
• A sector erase is requested on a sector write protected by option bit (SER = 1, SNB = i and nWRPi = 0 with i 0 <= i <= 11 bits in the FLASH_OPTCR register)
• The Flash memory is readout protected and an intrusion is detected

When in dual bank mode (nDBANK=0)

• A sector erase is requested and the Sector Number SNB field is not valid
  
• A mass erase is requested while at least one of the user sector is write protected by option bit (MER/MER1 = 1 and MER2 = 1 and nWRPi = 0 with 0 <= i <= 11 bits in the FLASH_OPTCR register)
  
• A bank erase is requested on bank 1 while at least one of the user sector of the bank 1 is write protected
  
• A bank erase is requested on bank 2 while at least one of the user sector of the bank 2 is write protected
  
• A sector erase is requested on a sector write protected by option bit (SER = 1, SNB = i and nWRPi= 0 with i 0 <= i <= 11 bits in the FLASH_OPTCR register). Note that SNB gives full granularity of sectors for bank 1 and bank 2 whereas nWRPi groups sectors by 2. An error is set if one of the two sectors is erased whereas write protection is enabled (example, nWRP[0]=0 and SNB = 0x00000 or SNB = 0x00001).
  
• The Flash memory is readout protected and an intrusion is detected
  

If a program operation is requested, the WRPERR bit is set when:

• A write operation is performed on System memory or on the reserved part of the user specific sector
  
• A write operation is performed to the information block
  
• A write operation is performed on a sector write protected by option bit. For nDBANK=0 configuration, SNB gives full granularity of sectors for bank 1 and bank 2 whereas nWRPi groups sectors by 2. An error is set if one of the two sectors is programed whereas write protection is enabled (example, nWRP[0]=0 and trying to program bank 1 sector 0 or sector 1).
  
• A write operation is requested on an OTP area which is already locked
  
• The Flash memory is read protected and an intrusion is detected.
  

3.6 One-time programmable bytes

Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area.

The OTP area is divided into 16 OTP data blocks of 64 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly.

3.7 FLASH registers

3.7.1 Flash access control register (FLASH_ACR)

The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency.

Address offset: 0x00
Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

3.7.2 Flash key register (FLASH_KEYR)

The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations.

Address offset: 0x04
Reset value: 0x0000 0000

Access: no wait state, word access

3.7.3 Flash option key register (FLASH_OPTKEYR)

The Flash option key register is used to allow program and erase operations in the information block.

Address offset: 0x08
Reset value: 0x0000 0000

Access: no wait state, word access

3.7.4 Flash status register (FLASH_SR)

The Flash status register gives information on ongoing program and erase operations.

Address offset: 0x0C
Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

3.7.5 Flash control register (FLASH_CR)

The Flash control register is used to configure and start Flash memory operations.

Address offset: 0x10

Reset value: 0x8000 0000

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

3.7.6 Flash option control register (FLASH_OPTCR)

The FLASH_OPTCR register is used to modify the user option bytes.

Address offset: 0x14

Reset value: 0xFFFFAAFD. The option bytes are loaded with values from Flash memory at reset release.

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

Note: When modifying the IWDG_SW, IWDG_STOP or IWDG_STDBY option byte, a system
reset is required to make the change effective.

3.7.7 Flash option control register (FLASH_OPTCR1)

The FLASH_OPTCR1 register is used to modify the user option bytes.

Address offset: 0x18

Reset value: 0x0040 0080 (ITCM-FLASH). The option bytes are loaded with values from Flash memory at reset release.

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

3.7.8 Flash interface register map

4 Power controller (PWR)

4.1 Power supplies

The device requires a 1.8 to 3.6 V operating voltage supply (V_DD). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power.

The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V_BAT voltage when the main V_DD supply is powered off.

Note: Depending on the operating power supply range, some peripheral may be used with limited
functionality and performance. For more details refer to section "General operating
conditions" in STM32F76xxx and STM32F77xxx datasheets.

1. V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.

4.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.

• The ADC voltage supply input is available on a separate V_DDA pin.
• An isolated supply ground connection is provided on pin V_SSA.

To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on V_REF. The voltage on V_REF ranges from 1.8 V to V_DDA.

4.1.2 Independent USB transceivers supply

The V_DDUSB is an independent USB power supply for full speed transceivers (USB OTG FS and USB OTG HS in FS mode). It can be connected either to V_DD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer Figure 6 and Figure 7). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V_DDUSB. When the V_DDUSB is connected to a separated power supply, it is independent from V_DD or V_DDA but it must be the last supply to be provided and the first to disappear. The following conditions V_DDUSB must be respected:

• During power-on phase (V_DD < V_{DD_MIN}), V_DDUSB should be always lower than V_DD
  
• During power-down phase (V_DD < V_{DD_MIN}), V_DDUSB should be always lower than V_DD
  
• V_DDUSB rising and falling time rate specifications must be respected
  
• In operating mode phase, V_DDUSB could be lower or higher than V_DD:
  
  • If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by V_DDUSB are operating between V_{DDUSB_MIN} and V_{DDUSB_MAX}.
    
  • The V_DDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied at by V_DDUSB.
    
  • If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by V_DDUSB are operating between V_{DD_MIN} and V_{DD_MAX}.
    

4.1.3 Independent SDMMC2 supply

The V_DDSDMMC is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7, PG9..12). It can be connected either to V_DD or an external independent power supply.

For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V_DDSDMMC. When the V_DDSDMMC is connected to a separated power supply, it is independent from V_DD and V_DDA but it must be the last supply to be provided and the first to disappear. The following conditions V_DDSDMMC must be respected:

• During power-on phase (V_DD < V_{DD_MIN}), V_DDDSDMMC should be always lower than V_DD
  
• During power-down phase (V_DD < V_{DD_MIN}), V_DDSDMMC should be always lower than V_DD
  
• V_DDSDMMC rising and falling time rate specifications must be respected
• In operating mode phase, V_DDSDMMC could be lower or higher than V_DD: the associated GPIOs (PD6, PD7, PG9..12) powered by V_DDSDMMC are operating between V_{DDSDMMC_MIN} and V_{DDSDMMC_MAX}. If V_DDSDMMC = V_DD, the associated GPIOs powered by V_DDSDMMC are operating between V_{DD_MIN} and V_{DD_MAX}.
  

4.1.4 Independent DSI supply

The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins:

• V_DDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global V_DD.
  
• V_CAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally to V_DD12DSI.
  
• V_DD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 uF must be connected on V_DD12DSI pin.
  
• V_SSDSI pin is an isolated supply ground used for DSI sub-system.
  

If DSI functionality is not used at all, then:

• V_DDDSI pin must be connected to global V_DD.
  
• V_CAPDSI pin must be connected externally to V_DD12DSI but the external capacitor is no more needed.
  
• V_SSDSI pin must be grounded
  

4.1.5 Battery backup domain

Backup domain description

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when V_DD is turned off, V_BAT pin can be connected to an optional standby voltage supplied by a battery or by another source.

To allow the RTC to operate even when the main digital supply (V_DD) is turned off, the V_BAT
pin powers the following blocks:

• The RTC
  
• The LSE oscillator
  
• The backup SRAM when the low-power backup regulator is enabled
  
• PC13 to PC15 I/Os, plus PI8 I/O (when available)

The switch to the V_BAT supply is controlled by the power-down reset embedded in the Reset block.

Warning: During t_RSTTEMPO (temporization at V_DD startup) or after a PDR
is detected, the power switch between V_BAT and V_DD remains
connected to V_BAT.
During the startup phase, if V_DD is established in less than
t_RSTTEMPO (Refer to the datasheet for the value of t_RSTTEMPO)
and V_DD > V_BAT + 0.6 V, a current may be injected into V_BAT
through an internal diode connected between V_DD and the
power switch (V_BAT).
If the power supply/battery connected to the V_BAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the V_BAT pin.

If no external battery is used in the application, it is recommended to connect the V_BAT pin to V_DD with a 100 nF external decoupling ceramic capacitor in parallel.

When the backup domain is supplied by V_DD (analog switch connected to V_DD), the following functions are available:

• PC14 and PC15 can be used as either GPIO or LSE pins
  
• PC13 and PI8 can be used as a GPIO pin (refer to Table 194: RTC pin PC13
  configuration and Table 195: RTC pin PI8 configuration for more details about these pins configuration)
  

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PI8 and PC13 to PC15 are restricted: the speed has to be limited to 2 MHz with a

maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).

When the backup domain is supplied by V_BAT (analog switch connected to V_BAT because V_DD is not present), the following functions are available:

• PC14 and PC15 can be used as LSE pins only
  
• PC13 can be used as tamper pin (TAMP1)
  
• PI8 can be used as tamper pin (TAMP2)
  

Backup domain access

After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

• Access to the RTC and RTC backup registers
  

1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 5.3.13)
   
2. Set the DBP bit in the PWR power control register (PWR_CR1) to enable access to the backup domain
   
3. Select the RTC clock source: see Section 5.2.8: RTC/AWU clock
   
4. Enable the RTC clock by programming the RTCEN [15] bit in the RCC backup domain
   control register (RCC_BDCR)
   

• Access to the backup SRAM
  

1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 5.3.13)
   
2. Set the DBP bit in the PWR power control register (PWR_CR1) to enable access to the backup domain
   
3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC APB1
   peripheral clock enable register (RCC_APB1ENR).
   

RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 32 backup data registers (128 bytes) which are reset when a tamper detection event occurs. For more details refer to Section 32:
Real-time clock (RTC).

Backup SRAM

The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or V_BAT mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when V_BAT is always present.

When the backup domain is supplied by V_DD (analog switch connected to V_DD), the backup SRAM is powered from V_DD which replaces the V_BAT power supply to save battery life.

When the backup domain is supplied by V_BAT (analog switch connected to V_BAT because V_DD is not present), the backup SRAM is powered by a dedicated low-power regulator. This regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and V_BAT modes or not. The power-down of this regulator is controlled

by a dedicated bit, the BRE control bit of the PWR_CSR1 register (see Section 4.4.2: PWR
power control/status register (PWR_CSR1)).

The backup SRAM is not mass erased by an tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. Refer to the description of Read protection (RDP) option byte.

4.1.6 Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is around 1.2 V.

This voltage regulator requires two external capacitors to be connected to two dedicated pins, V_{CAP_1} and V_{CAP_2} available in all packages. Specific pins must be connected either to V_SS or V_DD to activate or deactivate the voltage regulator. These pins depend on the package.

When activated by software, the voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes (Run, Stop, or Standby mode).

• In Run mode, the main regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale 3 can be configured through VOS[1:0] bits of the PWR_CR1 register). The scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock source. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected.
  

  The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency. After exit from Stop mode, the voltage

scale 3 is automatically selected.(see Section 4.4.1: PWR power control register
(PWR_CR1).

2 operating modes are available:

• Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3)
  
• Over-drive mode: This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for the voltage scaling scale 1 and scale 2.
  

• In Stop mode: the main regulator or low-power regulator supplies a low-power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM.
  

  The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured by software as follows:
  

  • Normal mode: the 1.2 V domain is preserved in nominal leakage mode. It is the default mode when the main regulator (MR) or the low-power regulator (LPR) is enabled.
    
  • Under-drive mode: the 1.2 V domain is preserved in reduced leakage mode. This mode is only available with the main regulator or the low-power regulator mode (see Table 14).
• In Standby mode: the regulator is powered down. The content of the registers and SRAM are lost except for the Standby circuitry and the backup domain.
  

Note: Over-drive and under-drive mode are not available when the regulator is bypassed.

For more details, refer to the voltage regulator section in the datasheets.

1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when V_DD = 1.8 to 2.1 V.
   

Entering Over-drive mode

It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase.

To enter Over-drive mode, follow the sequence below:

1. Select HSI or HSE as system clock.
   
2. Configure RCC_PLLCFGR register and set PLLON bit of RCC_CR register.
   
3. Set ODEN bit of PWR_CR1 register to enable the Over-drive mode and wait for the ODRDY flag to be set in the PWR_CSR1 register.
   
4. Set the ODSW bit in the PWR_CR1 register to switch the voltage regulator from Normal mode to Over-drive mode. The System will be stalled during the switch but the PLL clock system will be still running during locking phase.
   
5. Wait for the ODSWRDY flag in the PWR_CSR1 to be set.
   
6. Select the required Flash latency as well as AHB and APB prescalers.
   
7. Wait for PLL lock.
   
8. Switch the system clock to the PLL.
   
9. Enable the peripherals that are not generated by the System PLL (I2S clock, LCD-TFT clock, SAI1 clock, USB_48MHz clock....).
   

Note: The PLLI2S and PLLSAI can be configured at the same time as the system PLL.

During the Over-drive switch activation, no peripheral clocks should be enabled. The
peripheral clocks must be enabled once the Over-drive mode is activated.

Entering Stop mode disables the Over-drive mode, as well as the PLL. The application
software has to configure again the Over-drive mode and the PLL after exiting from Stop
mode.

Exiting from Over-drive mode

It is recommended to exit from Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE.There are two sequences that allow exiting from over-drive mode:

• By resetting simultaneously the ODEN and ODSW bits bit in the PWR_CR1 register (sequence 1)
  
• By resetting first the ODSW bit to switch the voltage regulator to Normal mode and then resetting the ODEN bit to disable the Over-drive mode (sequence 2).
  

Example of sequence 1:

1. Select HSI or HSE as system clock source.
   
2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, LCD-TFT clock, SAI1 clock, USB_48MHz clock,....)
   
3. Reset simultaneously the ODEN and the ODSW bits in the PWR_CR1 register to switch back the voltage regulator to Normal mode and disable the Over-drive mode.
   
4. Wait for the ODWRDY flag of PWR_CSR1 to be reset.

Example of sequence 2:

1. Select HSI or HSE as system clock source.
2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, LCD-TFT clock, SAI1 clock, USB_48MHz clock,....).
   
3. Reset the ODSW bit in the PWR_CR1 register to switch back the voltage regulator to Normal mode. The system clock is stalled during voltage switching.
   
4. Wait for the ODWRDY flag of PWR_CSR1 to be reset.
   
5. Reset the ODEN bit in the PWR_CR1 register to disable the Over-drive mode.
   

Note: During step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not
active (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled
and the voltage regulator is switched back to the initial voltage.

4.2 Power supply supervisor

4.2.1 Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting
from 1.8 V.

The device remains in Reset mode when V_DD/V_DDA is below a specified threshold, V_POR/PDR, without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

4.2.2 Brownout reset (BOR)

During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V_BOR threshold.

V_BOR is configured through device option bytes. By default, BOR is off. 3 programmable V_BOR threshold levels can be selected:

• BOR Level 3 (VBOR3). Brownout threshold level 3.
  
• BOR Level 2 (VBOR2). Brownout threshold level 2.
  
• BOR Level 1 (VBOR1). Brownout threshold level 1.
  

Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section in
the device datasheet.

When the supply voltage (V_DD) drops below the selected V_BOR threshold, a device reset is generated.

The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR (see Section 4.2.1: Power-on reset (POR)/power-down reset (PDR)).

The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).

4.2.3 Programmable voltage detector (PVD)

You can use the PVD to monitor the V_DD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to indicate if V_DD is higher or lower than the PVD threshold. This event is internally connected

to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V_DD drops below the PVD threshold and/or when V_DD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The devices feature three low-power modes:

• Sleep mode (Cortex^®-M7 core stopped, peripherals kept running)
  
• Stop mode (all clocks are stopped)
  
• Standby mode (1.2 V domain powered off)
  

In addition, the power consumption in Run mode can be reduce by one of the following means:

• Slowing down the system clocks
  
• Gating the clocks to the APBx and AHBx peripherals when they are unused.
  

Entering low-power mode

Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex^®-M7 System Control register is set on Return from ISR.

Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending.

Exiting low-power mode

The MCU exits from Sleep and Stop modes low-power mode depending on the way the low-power mode was entered:

• If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
  
• If the WFE instruction is used to enter the low-power mode, the MCU exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by:
  

  • NVIC IRQ interrupt:
    

    When SEVONPEND = 0 in the Cortex^®-M7 System Control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
    

    When SEVONPEND = 1 in the Cortex^®-M7 System Control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones.Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
    

  • Event
    

    This is done by configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.
    

The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 348: RTC block diagram).

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. Wakeup highlighted in gray.
   
2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need it anymore.
   

4.3.1 Debug mode

By default, the debug connection is lost when the devices enters in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex^®-M7 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 40.16.1: Debug support for low-power modes.

4.3.2 Run mode

Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 5.3.3: RCC clock configuration register (RCC_CFGR).

Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 peripheral clock enable register (RCC_AHB3ENR) (see Section 5.3.10: RCC AHB1
peripheral clock register (RCC_AHB1ENR), Section 5.3.11: RCC AHB2 peripheral clock
enable register (RCC_AHB2ENR), and Section 5.3.12: RCC AHB3 peripheral clock enable
register (RCC_AHB3ENR).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

4.3.3 Low-power mode

Entering low-power mode

Low-power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE (Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex^®-M7 System Control register is set on Return from ISR.

Exiting low-power mode

From Sleep and Stop modes the MCU exits low-power mode depending on the way the mode was entered:

• If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device
  
• If the WFE instruction was used to enter the low-power mode, the MCU exits the mode as soon as an event occurs. The wakeup event can by generated either by:
  

  • NVIC IRQ interrupt
    

    - When SEVEONPEND=0 in the Cortex^®-M7 System Control register.
    

    By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
    

    Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
    

    - When SEVEONPEND=1 in the Cortex^®-M7 System Control register.
    

    By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and (when enabled) the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
    

    All NVIC interrupts will wakeup the MCU, even the disabled ones.
    

    Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
    

    - Event
    

    Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.
    

From Standby mode the MCU exits Low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event (see Figure 348: RTC block diagram).

4.3.4 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex^®-M7 System Control register:

• Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.
• Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR.

Refer to Table 17 and Table 18 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:

• Enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex^®-M7 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
  
• Or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.
  

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.

Refer to Table 17 and Table 18 for more details on how to exit Sleep mode.

4.3.5 Stop mode

The Stop mode is based on the Cortex^®-M7 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

In Stop mode, the power consumption can be further reduced by using additional settings in the PWR_CR1 register. However this will induce an additional startup delay when waking up from Stop mode (see Table 19).

I/O states in Stop mode

In stop mode, all I/Os pins keep the same state as in the run mode

Entering Stop mode

The Stop mode is entered according to Entering low-power mode, when the SLEEPDEEP bit in Cortex^®-M7 System Control register is set.

Refer to Table 20 for details on how to enter the Stop mode.

When the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power or low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and UDEN bits of the PWR power control register (PWR_CR1).

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled during when the Stop mode is activated.

In Stop mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 30.3 in Section 30: Independent watchdog (IWDG).
  
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain
  control register (RCC_BDCR)
  
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC clock
  control & status register (RCC_CSR).
  
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR).
  

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

Note: Before entering Stop mode, it is recommended to enable the clock security system (CSS)
feature to prevent external oscillator (HSE) failure from impacting the internal MCU
behavior.

Exiting Stop mode

Refer to Table 20 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.

4.3.6 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex^®-M7 deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see Figure 5).

Entering Standby mode

The Standby mode is entered according to Entering low-power mode, when the SLEEPDEEP bit in the Cortex^®-M7 System Control register is set.

Refer to Table 21 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 30.3 in Section 30: Independent watchdog (IWDG).
  
• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the backup domain control register (RCC_BDCR)
  

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG Reset, a rising or falling edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp

event is detected. All registers are reset after wakeup from Standby except for PWR power
control/status register (PWR_CSR1).

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, vector reset is fetched, etc.). The SBF status flag in the PWR
power control/status register (PWR_CSR1) indicates that the MCU was in Standby mode.

Refer to Table 21 for more details on how to exit Standby mode.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• Reset pad (still available)
  
• PC13 if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out
  
• WKUP pins (PA0/PA2/PC1/PC13/PI8/PI11), if enabled
  

4.3.7 Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes

The MCU can be woken up from a low-power mode by an RTC alternate function.

The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.

These RTC alternate functions can wake up the system from the Stop and Standby low-power modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.

For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register
(RCC_BDCR):

• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with a very low-power consumption (additional consumption of less than 1 µA under typical conditions)
  
• Low-power internal RC oscillator (LSI RC)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC oscillator is designed to use minimum power.
  

RTC alternate functions to wake up the device from the Stop mode

• To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
  
  1. Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes)
     
  2. Enable the RTC Alarm Interrupt in the RTC_CR register
     
  3. Configure the RTC to generate the RTC alarm
     
• To wake up the device from the Stop mode with an RTC tamper or time stamp event, it is necessary to:
  
  1. Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes)
     
  2. Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register
     
  3. Configure the RTC to detect the tamper or time stamp event
     
• To wake up the device from the Stop mode with an RTC wakeup event, it is necessary to:
  
  1. Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes)
     
  2. Enable the RTC wakeup interrupt in the RTC_CR register
     
  3. Configure the RTC to generate the RTC Wakeup event

RTC alternate functions to wake up the device from the Standby mode

• To wake up the device from the Standby mode with an RTC alarm event, it is necessary to:
  
  1. Enable the RTC alarm interrupt in the RTC_CR register
     
  2. Configure the RTC to generate the RTC alarm
     
• To wake up the device from the Standby mode with an RTC tamper or time stamp event, it is necessary to:
  
  1. Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register
     
  2. Configure the RTC to detect the tamper or time stamp event
     
• To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to:
  
  1. Enable the RTC wakeup interrupt in the RTC_CR register
     
  2. Configure the RTC to generate the RTC wakeup event
     

Safe RTC alternate function wakeup flag clearing sequence

To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:

• When using RTC alarm to wake up the device from the low-power modes:
  
  1. Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
     
  2. Clear the RTC alarm (ALRAF/ALRBF) flag
     
  3. Enable the RTC alarm interrupt
     
  4. Re-enter the low-power mode
     
• When using RTC wakeup to wake up the device from the low-power modes:
  
  1. Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
     
  2. Enable the RTC Wakeup interrupt
     
  3. Re-enter the low-power mode
     
• When using RTC tamper to wake up the device from the low-power modes:
  
  1. Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
     
  2. Clear the Tamper (TAMP1F/TSF) flag
     
  3. Enable the RTC tamper interrupt
     
  4. Re-enter the low-power mode
     
• When using RTC time stamp to wake up the device from the low-power modes:
  
  1. Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
     
  2. Clear the RTC time stamp (TSF) flag
     
  3. Enable the RTC TimeStamp interrupt
     
  4. Re-enter the low-power mode

4.4 Power control registers

4.4.1 PWR power control register (PWR_CR1)

Address offset: 0x00

Reset value: 0x0000 C000 (reset by wakeup from Standby mode)

4.4.2 PWR power control/status register (PWR_CSR1)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

4.4.3 PWR power control/status register 2 (PWR_CR2)

Address offset: 0x08

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)