This reference manual targets application developers. It provides complete information on how to use the STM32F76xxx and STM32F77xxx microcontroller memory and peripherals.
The STM32F76xxx and STM32F77xxx is a family of microcontrollers with different memory sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics refer to the datasheets.
For information on the Arm® Cortex®-M7 with FPU core, refer to the Cortex®-M7 with FPU Technical Reference Manual.
Related documents
Available from STMicroelectronics web site www.st.com:
The STM32F76xxx and STM32F77xxx devices have an Arm®(a) Cortex®-M7 core.
| (omitted) |
The following abbreviations(b) are used in register descriptions:
read/write (rw) Software can read and write to this bit.
read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STM microcontrollers, some of them may not be used in the current document.
This section gives a brief definition of acronyms and abbreviations used in this document:
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, refer to the Cortex®-M7 Technical Reference Manual.
For peripheral availability and number across all sales types, refer to the particular device datasheet.
The main system architecture is based on 2 sub-systems:
| (omitted) |
The multi-AHB Bus-Matrix interconnects all the masters and slaves and it consists on:
The multi AHB bus matrix interconnects:
The multi AHB BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm.
It provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. The DTCM and ITCM RAMs (tightly coupled memories) are not part of the bus matrix.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave bus of the CPU. The instruction TCM RAM is reserved only for CPU. it is accessed at CPU clock speed with 0 wait states. The architecture is shown in Figure 1.
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM, DTCM, ITCM RAM and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR or RCC_APBxENR register.
Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
This bus connects the Cortex®-M7 with FPU core to the multi-AHB Bus-Matrix through AXI to AHB bridge. There are 4 AXI bus targets:
This bus is used by the Cortex®-M7 and AHBS for instruction fetches and data access on the embedded flash mapped on ITCM interface and instruction fetches and data access on ITCM RAM.
This bus is used by the Cortex®-M7 for data access on the DTCM RAM. It can be also used for instruction fetches.
This bus connects the AHB Slave bus of the Cortex®-M7 to the BusMatrix. This bus is used by DMAs and Peripherals DMAs for Data transfer on DTCM RAM only.
The ITCM bus is not accessible on AHBS. So the DMA data transfer to/from ITCM RAM is not supported. For DMA transfer to/from Flash on ITCM interface, all the transfers are forced through AHB bus
This bus connects the AHB Peripheral bus of the Cortex®-M7 to the BusMatrix. This bus is used by the core to perform all data accesses to peripherals.
The target of this bus is the AHB1 peripherals including the APB peripherals and the AHB2 peripherals.
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the DMA to perform transfer to/from memories. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7) internal Flash memory and external memories through the FMC or Quad-SPI.
This bus connects the DMA peripheral master bus interface to the AHB-to-APB bridges or the BusMatrix. This bus is used by the DMA to access peripherals or to perform memory-to-memory transfers. The targets of this bus are the APB peripherals plus AHB peripherals and data memories (internal SRAM1, SRAM2 and DTCM internal Flash memory and external memories through the FMC or Quad-SPI) for DMA2.
This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by the Ethernet DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7) internal Flash memory, and external memories through the FMC or Quad-SPI.
This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7), internal Flash memory, and external memories through the FMC or Quad-SPI.
This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by the LCD-TFT DMA to load data from a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7), external memories through FMC or Quad-SPI, and internal Flash memory.
This bus connect the DMA2D master interface to the BusMatrix. This bus is used by the DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7), external memories through FMC or Quad-SPI, and internal Flash memory.
Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.
| (omitted) |
All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.
The following table gives the boundary addresses of the peripherals available in the devices.
| Boundary address | Peripheral | Bus | Register map |
|---|---|---|---|
| 0xA000 1000 - 0xA0001FFF | QUADSPI Control Register | AHB3 |
Section 14.5.14: QUADSPI register map on
page 437 |
| 0xA000 0000 - 0xA000 0FFF | FMC control register |
Section 13.8: FMC register map on page 407
|
|
| 0x5006 0800 - 0x5006 0BFF | RNG |
AHB2 |
Section 22.8.4: RNG register map on page 770
|
| 0x5006 0400 - 0x5006 07FF | HASH |
Section 24.6.8: HASH register map on page 861
|
|
| 0x5006 0000 - 0x5006 03FF | CRYP |
Section 23.6.21: CRYP register map on page 837
|
|
| 0x5005 1000 - 0x5005 1FFF | JPEG |
Section 21.5.11: JPEG codec register map
|
|
| 0x5005 0000 - 0x5005 03FF | DCMI |
Section 18.7.12: DCMI register map on page 589
|
|
| 0x5000 0000 - 0x5003 FFFF | USB OTG FS |
Section 41.15.61: OTG_FS/OTG_HS register map
on page 1691 |
|
| 0x4004 0000 - 0x4007 FFFF | USB OTG HS |
AHB1 |
Section 41.15.61: OTG_FS/OTG_HS register map
on page 1691 |
| 0x4002 B000 - 0x4002 BBFF | Chrom-ART (DMA2D) |
Section 9.5.21: DMA2D register map on page 311
|
|
| 0x4002 8000 - 0x4002 93FF | ETHERNET MAC |
Section 42.8.5: Ethernet register maps on
page 1882 |
|
| 0x4002 6400 - 0x4002 67FF | DMA2 |
Section 8.5.11: DMA register map on page 276
|
|
| 0x4002 6000 - 0x4002 63FF | DMA1 |
||
| 0x4002 4000 - 0x4002 4FFF | BKPSRAM |
Section 5.3.27: RCC register map on page 217
|
|
| 0x4002 3C00 - 0x4002 3FFF | Flash interface register |
Section 3.7.8: Flash interface register map on
page 116 |
|
| 0x4002 3800 - 0x4002 3BFF | RCC |
Section 5.3.27: RCC register map on page 217
|
|
| 0x4002 3000 - 0x4002 33FF | CRC |
Section 12.4.6: CRC register map on page 331
|
|
| 0x4002 2800 - 0x4002 2BFF | GPIOK |
Section 6.4.11: GPIO register map on page 235
|
|
| 0x4002 2400 - 0x4002 27FF | GPIOJ |
||
| 0x4002 2000 - 0x4002 23FF | GPIOI |
Section 6.4.11: GPIO register map on page 235
|
|
| 0x4002 1C00 - 0x4002 1FFF | GPIOH |
||
| 0x4002 1800 - 0x4002 1BFF | GPIOG |
||
| 0x4002 1400 - 0x4002 17FF | GPIOF |
||
| 0x4002 1000 - 0x4002 13FF | GPIOE |
||
| 0x4002 0C00 - 0x4002 0FFF | GPIOD |
||
| 0x4002 0800 - 0x4002 0BFF | GPIOC |
||
| 0x4002 0400 - 0x4002 07FF | GPIOB |
||
| 0x4002 0000 - 0x4002 03FF | GPIOA |
||
| 0x4001 7800 - 0x4001 7BFF | MDIOS |
APB2 |
Section 38.4.10: MDIOS register map on
page 1470 |
| 0x4001 7400 - 0x4001 77FF | DFSDM1 |
Section 17.8.16: DFSDM register map on
page 555 |
|
| 0x4001 6C00 - 0x4001 73FF | DSI Host |
Section 20.17: DSI Host register map on page 737
|
|
| 0x4001 6800 - 0x4001 6BFF | LCD-TFT |
Section 19.7.26: LTDC register map on page 622
|
|
| 0x4001 5C00 - 0x4001 5FFF | SAI2 |
Section 36.5.18: SAI register map on page 1422
|
|
| 0x4001 5800 - 0x4001 5BFF | SAI1 |
Section 36.5.18: SAI register map on page 1422
|
|
| 0x4001 5400 - 0x4001 57FF | SPI6 |
Section 35.9.10: SPI/I2S register map on
page 1368 |
|
| 0x4001 5000 - 0x4001 53FF | SPI5 |
||
| 0x4001 4800 - 0x4001 4BFF | TIM11 |
Section 27.5.12: TIM10/TIM11/TIM13/TIM14
register map on page 1078 |
|
| 0x4001 4400 - 0x4001 47FF | TIM10 |
||
| 0x4001 4000 - 0x4001 43FF | TIM9 |
Section 27.4.13: TIM9/TIM12 register map on
page 1068 |
|
| 0x4001 3C00 - 0x4001 3FFF | EXTI |
Section 11.9.7: EXTI register map on page 325
|
|
| 0x4001 3800 - 0x4001 3BFF | SYSCFG |
Section 7.2.9: SYSCFG register map on page 244
|
|
| 0x4001 3400 - 0x4001 37FF | SPI4 |
Section 35.9.10: SPI/I2S register map on
page 1368 |
|
| 0x4001 3000 - 0x4001 33FF | SPI1 |
Section 35.9.10: SPI/I2S register map on
page 1368 |
|
| 0x4001 2C00 - 0x4001 2FFF | SDMMC1 |
Section 39.8.16: SDMMC register map on
page 1529 |
|
| 0x4001 2000 - 0x4001 23FF | ADC1 - ADC2 - ADC3 |
Section 15.13.18: ADC register map on page 483
|
|
| 0x4001 1C00 - 0x4001 1FFF | SDMMC2 |
Section 39.8.16: SDMMC register map on
page 1529 |
|
| 0x4001 1400 - 0x4001 17FF | USART6 |
Section 34.8.12: USART register map on
page 1307 |
|
| 0x4001 1000 - 0x4001 13FF | USART1 |
||
| 0x4001 0400 - 0x4001 07FF | TIM8 |
Section 25.4.27: TIM8 register map on page 958
|
|
| 0x4001 0000 - 0x4001 03FF | TIM1 |
Section 25.4.26: TIM1 register map on page 955
|
|
| 0x4000 7C00 - 0x4000 7FFF | UART8 |
APB1 |
Section 34.8.12: USART register map on
page 1307 |
| 0x4000 7800 - 0x4000 7BFF | UART7 |
||
| 0x4000 7400 - 0x4000 77FF | DAC |
Section 16.5.15: DAC register map on page 507
|
|
| 0x4000 7000 - 0x4000 73FF | PWR |
Section 4.4.4: PWR power control register 2
(PWR_CSR2) on page 148 |
|
| 0x4000 6C00 - 0x4000 6FFF | HDMI-CEC |
Section 43.7.7: HDMI-CEC register map on
page 1904 |
|
| 0x4000 6800 - 0x4000 6BFF | CAN2 |
Section 40.9.5: bxCAN register map on page 1573
|
|
| 0x4000 6400 - 0x4000 67FF | CAN1 |
||
| 0x4000 6000 - 0x4000 63FF | I2C4 |
Section 33.7.12: I2C register map on page 1239
|
|
| 0x4000 5C00 - 0x4000 5FFF | I2C3 |
Section 33.7.12: I2C register map on page 1239
|
|
| 0x4000 5800 - 0x4000 5BFF | I2C2 | ||
| 0x4000 5400 - 0x4000 57FF | I2C1 |
||
| 0x4000 5000 - 0x4000 53FF | UART5 |
Section 34.8.12: USART register map on
page 1307 |
|
| 0x4000 4C00 - 0x4000 4FFF | UART4 |
||
| 0x4000 4800 - 0x4000 4BFF | USART3 | ||
| 0x4000 4400 - 0x4000 47FF | USART2 |
||
| 0x4000 4000 - 0x4000 43FF | SPDIFRX |
Section 37.5.10: SPDIFRX interface register map
on page 1456 |
|
| 0x4000 3C00 - 0x4000 3FFF | SPI3 / I2S3 |
Section 35.9.10: SPI/I2S register map on
page 1368 |
|
| 0x4000 3800 - 0x4000 3BFF | SPI2 / I2S2 |
||
| 0x4000 3400 - 0x4000 37FF | CAN3 |
Section 40.9.5: bxCAN register map on page 1573
|
|
| 0x4000 3000 - 0x4000 33FF | IWDG |
Section 30.4.6: IWDG register map on page 1121
|
|
| 0x4000 2C00 - 0x4000 2FFF | WWDG |
Section 31.4.4: WWDG register map on page 1128
|
|
| 0x4000 2800 - 0x4000 2BFF | RTC & BKP Registers |
Section 32.6.21: RTC register map on page 1172
|
|
| 0x4000 2400 - 0x4000 27FF | LPTIM1 |
Section 29.6.9: LPTIM register map on page 1112
|
|
| 0x4000 2000 - 0x4000 23FF | TIM14 |
Section 27.5.12: TIM10/TIM11/TIM13/TIM14
register map on page 1078 |
|
| 0x4000 1C00 - 0x4000 1FFF | TIM13 |
||
| 0x4000 1800 - 0x4000 1BFF | TIM12 |
Section 27.4.13: TIM9/TIM12 register map on
page 1068 |
|
| 0x4000 1400 - 0x4000 17FF | TIM7 |
Section 28.4.9: TIM6/TIM7 register map on
page 1092 |
|
| 0x4000 1000 - 0x4000 13FF | TIM6 |
||
| 0x4000 0C00 - 0x4000 0FFF | TIM5 |
Section 26.4.21: TIMx register map on page 1028
|
|
| 0x4000 0800 - 0x4000 0BFF | TIM4 |
||
| 0x4000 0400 - 0x4000 07FF | TIM3 |
||
| 0x4000 0000 - 0x4000 03FF | TIM2 |
The STM32F76xxx and STM32F77xxx feature:
The embedded SRAM is divided into up to four blocks:
The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32 bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full words (32 bits) or double words (64 bits).
The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with ART on TCM interface or L1-
Cache on AXIM interface.
The Flash memory is organized as follows:
Refer to Section 3: Embedded Flash memory (FLASH) for more details.
In the STM32F76xxx and STM32F77xxx, two different boot areas can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 2.
| Boot mode selection |
Boot area |
|
|---|---|---|
| BOOT | Boot address option bytes |
|
| 0 | BOOT_ADD0[15:0] | Boot address defined by user option byte BOOT_ADD0[15:0] ST programmed value: Flash on ITCM at 0x0020 0000 |
| 1 | BOOT_ADD1[15:0] | Boot address defined by user option byte BOOT_ADD1[15:0] ST programmed value: System bootloader at 0x0010 0000 |
The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset.
The BOOT pin is also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode.
After startup delay, the selection of the boot area is done before releasing the processor reset.
The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot from any other boot address after next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows:
When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface) or system bootloader will be available. If the already programmed boot address in the BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at address 0x00200000.
When the device is in Dual bank mode (nDBANK =0) the application software can either boot from bank 1 or from bank 2. By default Dual boot is desactivated.
To select boot from the Flash memory bank 2, program the nDBOOT bit in the user option bytes. When this bit is reset (nDBOOT =0) and the BOOT pin selects an address in the Flash memory range, the device boots from system memory, and the bootloader jumps to execute the user application programmed in the Flask memory bank 2. For further details, please refer to the application note (AN2606).
Embedded bootloader
The embedded bootloader code is located in the system memory. It is programmed by ST during production. For full information, refer to the application note (AN2606) STM32 microcontroller system memory boot mode.
By default, when the boot from system bootloader is selected, the code is executed from TCM interface. It could be executed from AXIM interface by reprogramming the BOOT_ADDx address option bytes to 0x1FF0 0000.
The Flash memory interface manages Cortex®-M7 AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines on ITCM interface (ART Accelerator™).
Figure 3 shows the Flash memory interface connection inside the system architecture.
| (omitted) |
The Flash memory has the following main features:
The Flash memory is organized as follows:
In dual bank mode (nDBANK bit is reset), the main memory is divided into two banks of 1 Mbyte. Each 1 Mbyte bank is composed of 4 sectors of 16 Kbytes, 1 Sector of 64 Kbytes and 7 sectors of 128 Kbytes
- If nDBANK=1, Size of main memory block: 4 sectors of 32 KBytes, 1 sector of 128 KBytes, 7 sectors of 256 KBytes (reference to memory organization)
- If nDBANK=0, Each 1MB banks is composed of: 4 sectors of 16 KBytes, 1 sector of 64 KBytes, 7 sectors of 128 KBytes (reference to memory organization)
Dual bank organization on 1 Mbyte devices
The dual bank feature on 1 Mbyte devices is available. it is enabled by setting the nDBANK option bit to 0.
To obtain a dual bank Flash memory, the last 512 Kbytes of the single bank (sectors [8:11]) are re-structured in the same way as the first 512 Kbytes.
The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 12 sectors whereas the dual bank memory contains 16 sectors (see Table 6).
For erase operation, the right sector numbering must be considered according to nDBANK option bit.
When the nDBANK bit is reset, to perform an erase operation on bank 2, the sector number must be programmed (sector number from 12 to 19). Refer to FLASH_CR register for SNB (Sector number) configuration.
Refer to Table 5: 1 Mbyte Flash memory single bank organization (256 bits read
width) and Table 6: 1 Mbyte Flash memory dual bank organization (128 bits read
width) for details on 1 Mbyte single bank and 1 Mbyte dual bank organizations.
On 1 Mbyte devices the main memory block is divided into 4 sectors of 32 Kbytes, 1 sector of 128 Kbytes, and 3 sectors of 256 Kbytes. The dual bank feature is also available.
To obtain a dual bank Flash memory, the main memory block is re-structured in the a way that the first and last 512 Kbytes of each bank has the same structure.
The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 8 continuous sector numbers whereas the dual bank memory contains 16 sectors with discontinuity on sector numbering for each 512 Kbytes (see Table 5: 1 Mbyte Flash memory single bank organization (256 bits read width)).
For erase operation, the right sector numbering must be considered according to the dual bank nDBANK option bit.
The embedded Flash has three main interfaces:
The main memory and information block organization is shown in the following tables:
| Block | Name | Bloc base address on AXIM interface |
Block base address on ICTM interface |
Sector size |
|---|---|---|---|---|
| Main memory block |
Sector 0 | 0x0800 0000 - 0x0800 7FFF | 0x0020 0000 - 0x0020 7FFF | 32 KB |
| Sector 1 | 0x0800 8000 - 0x0800 FFFF | 0x0020 8000 - 0x0020 FFFF | 32 KB |
|
| Sector 2 | 0x0801 0000 - 0x0801 7FFF | 0x0021 0000 - 0x0021 7FFF | 32 KB |
|
| Sector 3 | 0x0801 8000 - 0x0801 FFFF | 0x0021 8000 - 0x0021 FFFF | 32 KB |
|
| Sector 4 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
|
| Sector 5 | 0x0804 0000 - 0x0807 FFFF | 0x0024 0000 - 0x0027 FFFF | 256 KB |
|
| Sector 6 | 0x0808 0000 - 0x080B FFFF | 0x0028 0000 - 0x002B FFFF | 256 KB |
|
| Sector 7 | 0x080C 0000 - 0x080F FFFF | 0x002C 0000 - 0x002F FFFF | 256 KB |
|
| Sector 8 | 0x0810 0000 - 0x0813 FFFF | 0x0030 0000 - 0x0033 FFFF | 256 KB |
|
| Sector 9 | 0x0814 0000 - 0x0817 FFFF | 0x00340000 - 0x0037 FFFF | 256 KB |
|
| Sector 10 | 0x0818 0000 - 0x081B FFFF | 0x0038 0000 - 0x003B FFFF | 256 KB |
|
| Sector 11 | 0x081C 0000 - 0x081F FFFF | 0x003C 0000 - 0x003F FFFF | 256 KB |
|
| Information block |
System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
|
| Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
| Block | Name | Bloc base address on AXIM interface |
Block base address on ICTM interface |
Sector size |
|---|---|---|---|---|
| Bank 1 |
Sector 0 | 0x0800 0000 - 0x0800 3FFF | 0x0020 0000 - 0x0020 3FFF | 16 KB |
| Sector 1 | 0x0800 4000 - 0x0800 7FFF | 0x0020 4000 - 0x0020 7FFF | 16 KB |
|
| Sector 2 | 0x0800 8000 - 0x0800 BFFF | 0x0020 8000 - 0x0020 BFFF | 16 KB |
|
| Sector 3 | 0x0800 C000 - 0x0800 FFFF | 0x0020 C000 - 0x0020 FFFF | 16 KB |
|
| Sector 4 | 0x0801 0000 - 0x0801 FFFF | 0x0021 0000 - 0x0021 FFFF | 64 KB |
|
| Sector 5 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
|
| Sector 6 | 0x0804 0000 - 0x0805 FFFF | 0x0024 0000 - 0x0025 FFFF | 128 KB |
|
| Sector 7 | 0x0806 0000 - 0x0807 FFFF | 0x0026 0000 - 0x0027 FFFF | 128 KB |
|
| Sector 8 | 0x0808 0000 - 0x0809 FFFF | 0x0028 0000 - 0x0029 FFFF | 128 KB |
|
| Sector 9 | 0x080A 0000 - 0x080B FFFF | 0x002A 0000 - 0x002B FFFF | 128 KB |
|
| Sector 10 | 0x080C 0000 - 0x080E FFFF | 0x002C 0000 - 0x002E FFFF | 128 KB |
|
| Sector 11 | 0x080E 0000 - 0x080F FFFF | 0x002E 0000 - 0x002F FFFF | 128 KB | |
| Bank 2 |
Sector 12 | 0x0810 0000 - 0x0810 3FFF | 0x0030 0000 - 0x0030 3FFF | 16 KB |
| Sector 13 | 0x0810 4000 - 0x0810 7FFF | 0x0030 4000 - 0x0030 7FFF | 16 KB |
|
| Sector 14 | 0x0810 8000 - 0x0810 BFFF | 0x0030 8000 - 0x0030 BFFF | 16 KB |
|
| Sector 15 | 0x0810 C000 - 0x0810 FFFF | 0x0030 C000 - 0x0030 FFFF | 16 KB |
|
| Sector 16 | 0x0811 0000 - 0x0811 FFFF | 0x0031 0000 - 0x0031 FFFF | 64 KB |
|
| Sector 17 | 0x0812 0000 - 0x0813 FFFF | 0x0032 0000 - 0x0033 FFFF | 128 KB |
|
| Sector 18 | 0x0814 0000 - 0x0815 FFFF | 0x0034 0000 - 0x0035 FFFF | 128 KB |
|
| Sector 19 | 0x0816 0000 - 0x0817 FFFF | 0x0036 0000 - 0x0037 FFFF | 128 KB |
|
| Sector 20 | 0x0818 0000 - 0x0819 FFFF | 0x0038 0000 - 0x0039 FFFF | 128 KB |
|
| Sector 21 | 0x081A 0000 - 0x081B FFFF | 0x003A 0000 - 0x003B FFFF | 128 KB |
|
| Sector 22 | 0x081C 0000 - 0x081E FFFF | 0x003C 0000 - 0x003E FFFF | 128 KB |
|
| Sector 23 | 0x081E 0000 - 0x081F FFFF | 0x003E 0000 - 0x003F FFFF | 128 KB |
|
| Information block |
System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
|
| Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
| Block | Name | Bloc base address on AXIM interface |
Block base address on ICTM interface |
Sector size |
|---|---|---|---|---|
|
Main memory block |
Sector 0 | 0x0800 0000 - 0x0800 7FFF | 0x0020 0000 - 0x0020 7FFF | 32 KB |
| Sector 1 | 0x0800 8000 - 0x0800 FFFF | 0x0020 8000 - 0x0020 FFFF | 32 KB |
|
| Sector 2 | 0x0801 0000 - 0x0801 7FFF | 0x0021 0000 - 0x0021 7FFF | 32 KB |
|
| Sector 3 | 0x0801 8000 - 0x0801 FFFF | 0x0021 8000 - 0x0021 FFFF | 32 KB |
|
| Sector 4 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
|
| Sector 5 | 0x0804 0000 - 0x0807 FFFF | 0x0024 0000 - 0x0027 FFFF | 256 KB |
|
| Sector 6 | 0x0808 0000 - 0x080B FFFF | 0x0028 0000 - 0x002B FFFF | 256 KB |
|
| Sector 7 | 0x080C 0000 - 0x080F FFFF | 0x002C 0000 - 0x002F FFFF | 256 KB |
|
| Information block |
System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
|
| Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
| Block | Name | Bloc base address on AXIM interface |
Block base address on ICTM interface |
Sector size |
|---|---|---|---|---|
| Bank1 |
Sector 0 | 0x0800 0000 - 0x0800 3FFF | 0x0020 0000 - 0x0020 3FFF | 16 KB |
| Sector 1 | 0x0800 4000 - 0x0800 7FFF | 0x0020 4000 - 0x0020 7FFF | 16 KB |
|
| Sector 2 | 0x0800 8000 - 0x0800 BFFF | 0x0020 8000 - 0x0020 BFFF | 16 KB |
|
| Sector 3 | 0x0800 C000 - 0x0800 FFFF | 0x0020 C000 - 0x0020 FFFF | 16 KB |
|
| Sector 4 | 0x0801 0000 - 0x0801 FFFF | 0x0021 0000 - 0x0021 FFFF | 64 KB |
|
| Sector 5 | 0x0802 0000 - 0x0803 FFFF | 0x0022 0000 - 0x0023 FFFF | 128 KB |
|
| Sector 6 | 0x0804 0000 - 0x0805 FFFF | 0x0024 0000 - 0x0025 FFFF | 128 KB |
|
| Sector 7 | 0x0806 0000 - 0x0807 FFFF | 0x0026 0000 - 0x0027 FFFF | 128 KB |
|
| Bank 2 |
Sector 12 | 0x0808 0000 - 0x0808 3FFF | 0x0028 0000 - 0x0028 3FFF | 16 KB |
| Sector 13 | 0x0808 4000 - 0x0808 7FFF | 0x0028 4000 - 0x0028 7FFF | 16 KB |
|
| Sector 14 | 0x0808 8000 - 0x0808 BFFF | 0x0028 8000 - 0x0028 BFFF | 16 KB |
|
| Sector 15 | 0x0808 C000 - 0x0808 FFFF | 0x0028 C000 - 0x0028 FFFF | 16 KB |
|
| Sector 16 | 0x0809 0000 - 0x0809 FFFF | 0x0029 0000 - 0x0029 FFFF | 64 KB |
|
| Sector 17 | 0x080A 0000 - 0x080B FFFF | 0x002A 0000 - 0x002B FFFF | 128 KB |
|
| Sector 18 | 0x080C 0000 - 0x080E FFFF | 0x002C 0000 - 0x002E FFFF | 128 KB |
|
| Sector 19 | 0x080E 0000 - 0x080F FFFF | 0x002E 0000 - 0x002F FFFF | 128 KB |
|
| Information block |
System memory | 0x1FF0 0000 - 0x1FF0 EDBF | 0x0010 0000 - 0x0010 EDBF | 60 Kbytes |
| OTP | 0x1FF0 F000 - 0x1FF0 F41F | 0x0010 F000 - 0x0010 F41F | 1024 bytes |
|
| Option bytes | 0x1FFF 0000 - 0x1FFF 001F | - | 32 bytes |
To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
The correspondence between wait states and CPU clock frequency is given in Table 13 and Table 7.
Note: - When VOS[1:0] = '0x01', the maximum value of fHCLK is 144 MHz.
- When VOS[1:0] = '0x10', the maximum value of fHCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode.
- When VOS[1:0] = '0x11, the maximum value of fHCLK is 180 MHz. It can be extended to
216 MHz by activating the over-drive mode.
- The over-drive mode is not available when VDD ranges from 1.8 to 2.1 V.
Refer to Section 4.1.6: Voltage regulator for details on how to activate the over-drive mode.
|
Wait states (WS) (LATENCY) |
HCLK (MHz) |
|||
|---|---|---|---|---|
|
Voltage range 2.7 V - 3.6 V |
Voltage range 2.4 V - 2.7 V |
Voltage range 2.1 V - 2.4 V |
Voltage range 1.8 V - 2.1 V |
|
| 0 WS (1 CPU cycle) | 0 < HCLK ≤ 30 | 0 < HCLK ≤ 24 | 0 < HCLK ≤ 22 | 0 < HCLK ≤ 20 |
| 1 WS (2 CPU cycles) | 30 < HCLK ≤ 60 | 24 < HCLK ≤ 48 | 22 < HCLK ≤ 44 | 20 < HCLK ≤ 40 |
| 2 WS (3 CPU cycles) | 60 < HCLK ≤ 90 | 48 < HCLK ≤ 72 | 44 < HCLK ≤ 66 | 40 < HCLK ≤ 60 |
| 3 WS (4 CPU cycles) | 90 < HCLK ≤ 120 | 72 < HCLK ≤ 96 | 66 < HCLK ≤ 88 | 60 < HCLK ≤ 80 |
| 4 WS (5 CPU cycles) | 120 < HCLK ≤ 150 | 96 < HCLK ≤ 120 | 88 < HCLK ≤ 110 | 80 < HCLK ≤ 100 |
| 5 WS (6 CPU cycles) | 150 < HCLK ≤ 180 | 120 < HCLK ≤ 144 | 110 < HCLK ≤ 132 | 100 < HCLK ≤ 120 |
| 6 WS (7 CPU cycles) | 180 < HCLK ≤ 210 | 144 <HCLK ≤ 168 | 132 < HCLK ≤ 154 | 120 < HCLK ≤ 140 |
| 7 WS (8 CPU cycles) | 210 < HCLK ≤ 216 | 168 < HCLK ≤ 192 | 154 < HCLK ≤ 176 | 140 < HCLK ≤ 160 |
| 8 WS (9 CPU cycles) | - | 192 < HCLK ≤ 216 | 176 < HCLK ≤ 198 | 160 < HCLK ≤ 180 |
| 9 WS (10 CPU cycles) | - | - | 198 < HCLK ≤ 216 | - |
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of wait states to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
Decreasing the CPU frequency
Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
Instruction prefetch
Depending on Flash dual bank mode configuration, each flash read operation provides:
In case of single bank mode (nDBANK option bit is set) 256 bits representing 8 instructions of 32 bits to 16 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 8 CPU cycles are needed to execute the previous instruction line read.
When in dual bank mode (nDBANK option bit is reset) 128 bits representing 4 instructions of 32 bits to 8 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 4 CPU cycles are needed to execute the previous instruction line read. The prefetch on ITCM bus allows to read the sequential next line of instructions in the flash while the current instruction line is requested by the CPU. The prefetch can be enabled by setting the PRFTEN bit of the FLASH_ACR register. This feature is useful if at least one Wait State is needed to access the flash. When the code is not sequential (branch), the instruction may not be present neither in the current instruction line used nor in the prefetched instruction line. In this case (miss), the penalty in term of number of cycles is at least equal to the number of Wait States.
Adaptive real-time memory accelerator (ART Accelerator™)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm® Cortex®-M7 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M7 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies.
To release the processor full performance, the accelerator implements a unified cache of an instruction and branch cache which increases program execution speed from the Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 216 MHz.
The ART accelerator is available only for flash access on ITCM interface.
To limit the time lost due to jumps, it is possible to retain 64 lines of 256 bits (when in single bank mode configuration nDBANK=1 or 128 bits in dual bank configuration with nDBANK=0) in the ART accelerator. This feature can be enabled by setting the ARTEN bit of the FLASH_CR register. The ART Accelerator is unified, it contains instruction as well as data literal pools. Each time a miss occurs (requested data not present in the current data line used or in the instruction cache memory), the read line is copied in the instruction cache memory of ART. If a data contained in the instruction cache memory is requested by the CPU, the data is provided without inserting delay. Once all the cache memory lines are filled, the LRU (Least Recently Used) policy is used to determine the line to replace in the memory cache. This feature is particularly useful in case of code containing loops.
Note: Data in user configuration sector are not cacheable.
For any Flash memory program operation (erase or program), the CPU clock frequency (HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation.
Any attempt to read the Flash memory while it is being written or erased, causes the bus to stall. Read operations are processed correctly once the program operation has completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing.
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register:
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the FLASH_CR register.
Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register before any programming/erasing operation.
A Flash memory erase operation can only be performed by sector, bank or for the whole Flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet.
Table 8 provides the correct PSIZE values.
| Voltage range 2.7 - 3.6 V with External VPP |
Voltage range 2.7 - 3.6 V |
Voltage range 2.4 - 2.7 V |
Voltage range 2.1 - 2.4 V |
Voltage range 1.8 V - 2.1 V |
|
|---|---|---|---|---|---|
| Parallelism size | x64 | x32 | x16 | x8 |
|
| PSIZE(1:0) | 11 | 10 | 01 | 00 | |
Note: Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.
To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The VPP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.
It is possible to use main Flash either in single bank mode (256 bits read width) or dual bank mode (128 bits read width) thanks to nDBANK option bit. However, it is highly recommended to use the following sequence when switching from a mode to an other.
Activating dual bank mode (switching from nDBANK=1 to nDBANK=0)
When switching from one Flash mode to another (single to dual Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when the memory organization is changed any access (CPU or DMAs) to Flash memory should be avoided before reprogramming.
If ITCM path is used for code execution:
If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed).
Note: The memory organization is changed and previously data in Flash memory is corrupted.
If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections)
-> the new software is ready to be run using bank configuration
De-activating dual bank mode (switching from nDBANK=0 to nDBANK=1)
When switching from one Flash mode to another (dual to single Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when memory organization is changed any access (CPU or DMAs) to Flash memory should be avoided before reprogramming.
If ITCM path is used for code execution:
If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed)
Note: The memory organization is changed and previously data in Flash memory is corrupted.
If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections)
-> The new software is ready to be run using single bank configuration
The Flash memory erase operation can be performed at sector level, at bank level (bank mass erase when dual bank mode is enabled nDBANK=0) or on the whole Flash memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector.
Sector Erase
To erase a sector, follow the procedure below:
Bank Mass Erase (available only in dual bank mode when nDBANK=0)
To perform mass erase on Bank 1 or Bank 2, the procedure below should be followed:
Mass Erase
To perform Mass Erase, the following sequence is recommended depending on nDBANK option bit:
Note: If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.
Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.
Standard programming
The Flash memory programming sequence is as follows:
Note: Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.
If an erase and a program operation are requested simultaneously, the erase operation is
performed first.
Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.
Programming errors
In case of error, the Flash operation (programming or erasing) is aborted with one of the following errors:
PGAERR: Alignment Programming error
It is not allowed to program data to the Flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and the program alignment error flag (PGAERR) is set in the FLASH_SR register.
PGEPRR: Programming parallelism error
The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and the program parallelism error flag (PGPERR) is set in the FLASH_SR register.
ERSERR: Erase sequence error
When an erase operation to the flash is performed by the code while the control register has not been correctly configured, the ERSERR error flag is set
WRPERR: Write Protection Error
WRPERR is set if one of the following conditions occurs:
If a part of code is programmed in the flash, the user must guarantee that this part of code has not been executed since the last reset. If this condition can not be filled safely, it is recommended to flush the Caches.
If a flash program or erase operation hits one or several data section already loaded in the cache, it is the responsibility of the user to guarantee that these data will not be accessed during code execution. Therefore during these operations, it is recommended to flush and/or deactivate the Caches.
Note: Data coherency between caches and Flash memory is the responsibility of the user code
Note: The ART cache can be flushed only if the ART accelerator is disabled (ARTEN = 0).
Read-while-write (RWW)
Thanks to the dual bank mode (active when nDBANK option bit is 0), the Flash memory structure allows read-while-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank.
Note: Write-while-write operations are not allowed. As an exampled, It is not possible to perform
an erase or program operation on one bank while erasing or programming the other one,
except mass erase which erase both banks at same time
Read from bank 1 while erasing bank 2
While executing a program code from bank 1, it is possible to perform an erase operation on bank 2 (and vice versa). Follow the procedure below:
Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.
Read from bank 1 while programming bank 2
While executing a program code (instruction fetch) from bank 1,it is possible to perform an program operation to the bank 2 (and vice versa). Follow the procedure below:
Note: After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.
Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables interrupt generation when an erase or program operation ends, that is when the busy bit (BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the following error flags is set in the FLASH_SR register:
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| End of operation | EOP | EOPIE |
| Write protection error | WRPERR | ERRIE |
| Programming error | PGAERR, PGPERR, ERSERR | ERRIE |
The option bytes are configured by the end user depending on the application requirements. Table 10 shows the organization of these bytes inside the information block.
The option bytes can be read from the user configuration memory locations or from the Option byte registers:
| AXI address | [63:16] | [15:0] |
|---|---|---|
| 0x1FFF 0000 | Reserved | ROP & user option bytes (RDP & USER) |
| 0x1FFF 0008 | Reserved |
IWDG_STOP, IWDG_STBY and nDBANK, nDBOOT and Write protection nWRP/NWRPDB (sector 0 to 11) and user option bytes |
| 0x1FFF 0010 | Reserved | BOOT_ADD0 |
| 0x1FFF 0018 | Reserved | BOOT_ADD1 |
Memory address: 0x1FFF 0000
ST programmed value: 0x5500AAFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 14 13 12 11 10 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
RDP | nRST_ STDBY |
nRST_ STOP |
IWDG_ SW |
WWDG _SW |
BOR_LEV[1:0] | Res. | Res. |
|
| r | r | r | r | r | r | r | ||||||||||||||||||
| Bits 31:13 | Not used. |
| Bits 15:8 | RDP: Read Out Protection |
|
The read protection helps the user protect the software code stored in Flash memory. |
|
| Bit 7 |
nRST_STDBY
|
|
0: Reset generated when entering Standby mode. 1: No reset generated. |
|
| Bit 6 |
nRST_STOP
|
|
0: Reset generated when entering Stop mode. 1: No reset generated. |
|
| Bit 5 | IWDG_SW: Independant watchdog selection |
|
0: Hardware independant watchdog. 1: Software independant watchdog. |
|
| Bit 4 | WWDG_SW: Window watchdog selection |
|
0: Hardware window watchdog. 1: Software window watchdog. |
|
| Bits 3:2 | BOR_LEV: BOR reset Level |
|
These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory. 00: BOR Level 3 (VBOR3), brownout threshold level 3 For full details on BOR characteristics, refer to the “Electrical characteristics” section of the product datasheet. |
|
| Bits 1:0 | Not used |
Memory address: 0x1FFF 0008
ST programmed value: 0x0000FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. | res. |
IWDG_ STOP |
IWDG_ STDBY |
nDBAN K |
nDBOO T |
nWRPi |
|||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||
| Bits 31:16 | Not used. |
| Bit 15 | IWDG_STOP: Independent watchdog counter freeze in stop mode |
|
0: Freeze IWDG counter in stop mode. |
|
| Bit 14 | IWDG_STDBY: Independent watchdog counter freeze in Standby mode |
|
1: IWDG counter active in standby mode. |
|
| Bit 13 | nDBANK: Not dual bank mode |
|
1: The Flash user area is seen as a single bank with 256 bits read access. |
|
| Bit 12 | nDBOOT: Dual Boot mode (valid only when nDBANK=0) |
|
1: Dual Boot disabled. Boot according to boot address option (Default) |
|
| Bits 11:0 | nWRPi: Non Write Protection of sectors |
|
0: Write protection active. 1: Write protection not active.
Refer to Section 3.5.2: Write protections.
|
Memory address: 0x1FFF 0010
ST programmed value: 0xFF7F 0080 (ITCM-FLASH base address)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
BOOT_ADD0[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Not used. |
| Bits 15:0 | BOOT_ADD0[15:0]: Boot memory base address when Boot pin =0 |
|
BOOT_ADD0[15:0] correspond to address [29:14], |
Memory address: 0x1FFF 0018
ST programmed value: 0xFFBF0040 (system memory bootoader address)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
BOOT_ADD1[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 |
Not used
|
| Bits 15:0 | BOOT_ADD1[15:0]: Boot memory base address when Boot pin =1 BOOT_ADD1[15:0] correspond to address [29:14], The boot base address supports address range only from 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB. Example: BOOT_ADD1 = 0x0000: Boot from ITCM RAM(0x0000 0000) BOOT_ADD1 = 0x0040: Boot from system memory bootloader (0x0010 0000) BOOT_ADD1 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000) BOOT_ADD1 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000) BOOT_ADD1 = 0x8000: Boot from DTCM RAM (0x2000 0000) BOOT_ADD1 = 0x8004: Boot from SRAM1 (0x2002 0000) BOOT_ADD1 = 0x8013: Boot from SRAM2 (0x2004 C000) |
To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have to perform the following sequence:
The user option bytes can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.
Modifying user option bytes
To modify the user option value, follow the sequence below:
Note: The value of an option is automatically modified by first erasing the information block and
then programming all the option bytes with the values contained in the FLASH_OPTCR
register.
Note: When setting the OPTSTRT bit in the FLASH_OPTCR register and before polling the BSY
bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a
previous access to the FLASH_OPTCR register.
The user area in the Flash memory can be protected against read operations by an entrusted code. Three read protection levels are defined:
Level 0: no read protection
When the read protection level is set to Level 0 by writing 0xAA into the read protection option byte (RDP), all read/write operations (if no write protection is set) from/to the Flash memory or the backup SRAM are possible in all boot configurations (Flash user boot, debug or boot from RAM).
Level 1: read protection enabled
It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:
When Level 1 is active, programming the protection option byte (RDP) to Level 0 causes the Flash memory and the backup SRAM to be mass-erased. As a result the user code area is cleared before the read protection is removed. The mass erase only erases the user code area. The other option bytes including write protections remain unchanged from before the mass-erase operation. The OTP area is not affected by mass erase and remains unchanged. Mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.
Level 2: debug/chip read disabled
The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When the read protection Level 2 is set:
Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.
Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.
Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply
a POR (power-on reset).
| Memory area | Protection Level |
Debug features, Boot from RAM or from System memory bootloader | Booting from Flash memory |
||||
|---|---|---|---|---|---|---|---|
| Read | Write | Erase | Read | Write | Erase | ||
| Main Flash Memory and Backup SRAM |
Level 1 | NO | NO(1) | YES |
|||
| Level 2 | NO | YES |
|||||
| Option Bytes |
Level 1 | YES | YES |
||||
| Level 2 | NO | NO |
|||||
| OTP |
Level 1 | NO | NA | YES | NA |
||
| Level 2 | NO | NA | YES | NA |
|||
Figure 4 shows how to go from one RDP level to another.
| (omitted) |
User sectors in the Flash memory can be protected against unwanted write operations due to loss of program counter contexts. When the non-write protection nWRPi bits in the FLASH_OPTCR register is low, the corresponding sector cannot be erased or programmed.
If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.
Write protection user options in single bank mode (nBANK=1)
The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:
nWRP[0] bit is write protection bit for sector 0
nWRP[1] bit is write protection bit for sector 1
...
nWRP[5] bit is write protection bit for sector 5
nWRP[6] bit is write protection bit for sector 6
nWRP[7] bit is write protection bit for sector 7
...
nWRP[11] bit is write protection bit for sector 11
When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.
Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Write protection user options in dual bank mode (nBANK=0)
The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:
nWRP[0] bit is write protection bit for bank 1 sector 0/ sector 1
nWRP[1] bit is write protection bit for bank 1 sector 2/ sector 3
...
nWRP[5] bit is write protection bit for bank 1 sector 10/ sector 11
nWRP[6] bit is write protection bit for bank 2 sector 12/ sector 13
nWRP[7] bit is write protection bit for bank 2 sector 14/ sector 15
...
nWRP[11] bit is write protection bit for bank 2 sector 22/ sector 23
When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.
Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Write protection error flag
If an erase/program operation to a write protected part of the Flash memory is performed, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
If an erase operation is requested, the WRPERR bit is set when:
When in single bank mode (nDBANK=1)
When in dual bank mode (nDBANK=0)
If a program operation is requested, the WRPERR bit is set when:
Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area.
| OTP Block | [255:224] | [223:193] | [192:161] | [160:128] | [127:96] | [95:64] | [63:32] | [31:0] |
Address byte 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0 |
OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | 0x1FF0 F000 |
| OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | OTP0 | 0x1FF0 F020 |
|
| 1 |
OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | 0x1FF0 F040 |
| OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | OTP1 | 0x1FF0 F060 |
|
|
- - - |
- | - | - | - | - | - | - | - | - |
| 14 |
OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | 0x1FF0 F380 |
| OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | OPT14 | 0x1FF0 F3A0 | |
| 15 |
OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | 0x1FF0 F3C0 |
| OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | OPT15 | 0x1FF0 F3E0 |
|
| Lock block | reserved | reserved | reserved | reserved |
LOCK15... LOCKB12 |
LOCK11... LOCKB8 |
LOCK7... LOCKB4 |
LOCK3... LOCKB0 |
0x1FF0 F400 |
The OTP area is divided into 16 OTP data blocks of 64 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly.
The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | ARTRST | Res. | ARTEN | PRFTEN | Res. | Res. | Res. | Res. | LATENCY |
|||
| rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept cleared. |
| Bit 11 | ARTRST: ART Accelerator reset |
|
0: ART Accelerator is not reset 1: ART Accelerator is reset |
|
| Bit 10 | Reserved, must be kept cleared. |
| Bit 9 | ARTEN: ART Accelerator Enable |
|
0: ART Accelerator is disabled 1: ART Accelerator is enabled |
|
| Bit 8 | PRFTEN: Prefetch enable |
|
0: Prefetch is disabled 1: Prefetch is enabled |
|
| Bits 7:4 | Reserved, must be kept cleared. |
| Bits 3:0 | LATENCY[3:0]: Latency |
|
These bits represent the ratio of the CPU clock period to the Flash memory access time. |
The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY[31:16] |
KEY[15:0] |
||||||||||||||||||||||||||||||
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | FKEYR: FPEC key |
|
The following values must be programmed consecutively to unlock the FLASH_CR register and allow programming/erasing it:
|
The Flash option key register is used to allow program and erase operations in the information block.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OPTKEYR[31:16] |
OPTKEYR[15:0] |
||||||||||||||||||||||||||||||
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | OPTKEYR[31:0]: Option byte key |
|
The following values must be programmed consecutively to unlock the FLASH_OPTCR register and allow programming it:
|
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BSY |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ERSERR | PGPERR | PGAERR | WRPERR | Res. | Res. | OPERR | EOP |
| r |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:17 | Reserved, must be kept cleared. |
| Bit 16 | BSY: Busy |
|
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs. 0: no Flash memory operation ongoing |
|
| Bits 15:8 | Reserved, must be kept cleared. |
| Bit 7 | ERSERR: Erase Sequence Error |
|
Set by hardware when a write access to the Flash memory is performed by the code while the control register has not been correctly configured. |
|
| Bit 6 | PGPERR: Programming parallelism error |
|
Set by hardware when the size of the access (byte, half-word, word, double word) during the program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, x64). |
|
| Bit 5 | PGAERR: Programming alignment error |
|
Set by hardware when the data to program cannot be contained in the same 128-bit Flash memory row. |
|
| Bit 4 | WRPERR: Write protection error |
|
Set by hardware when an address to be erased/programmed belongs to a write-protected part of the Flash memory. |
|
| Bits 3:2 | Reserved, must be kept cleared. |
| Bit 1 | OPERR: Operation error |
|
Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1). |
|
| Bit 0 | EOP: End of operation |
|
Set by hardware when one or more Flash memory operations (program/erase) has/have completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1). |
The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOCK | Res. | Res. | Res. | Res. | Res. | ERRIE | EOPIE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STRT |
MER2 | Res. | Res. | Res. | Res. | Res. | PSIZE[1:0] | SNB[4:0] | MER/ MER1 |
SER | PG |
|||||
| rs | rw | rw | rs |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||
| Bit 31 | LOCK: Lock |
|
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. |
|
| Bits 30:26 | Reserved, must be kept cleared. |
| Bit 25 | ERRIE: Error interrupt enable |
|
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set to 1. |
|
| Bit 24 | EOPIE: End of operation interrupt enable |
|
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1. |
|
| Bits 23:17 | Reserved, must be kept cleared. |
| Bit 16 | STRT: Start |
|
This bit triggers an erase operation when set. It is set only by software and cleared when the BSY bit is cleared. |
|
| Bit 15 | MER2: Bank 2 Mass Erase |
|
if nDBANK=1, this bit must be kept cleared |
|
| Bits 14:10 | Reserved, must be kept cleared. |
| Bits 9:8 | PSIZE: Program size |
|
These bits select the program parallelism. |
|
| Bits 7:3 | SNB[4:0]: Sector number |
|
if nDBANK=1 in single bank mode These bits select the sector to erase. if nDBANK=0 in dual bank mode These bits select the sector to erase from bank 1 or bank 2, where MSB bit selects the bank |
|
| Bit 2 | MER/MER1: Mass Erase/Bank 1 Mass Erase |
|
If nDBANK=1, MER activates erase of all user sectors in Flash memory. |
|
| Bit 1 | SER: Sector Erase |
|
Sector Erase activated. |
|
| Bit 0 | PG: Programming |
|
Flash programming activated. |
The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0xFFFFAAFD. The option bytes are loaded with values from Flash memory at reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IWDG_ STOP |
IWDG_ STDBY |
nDBANK | nDBOOT | nWRP[11:0] |
RDP[7:0] | nRST_ STDBY |
nRST_ STOP |
IWDG_ SW |
WWDG _SW |
BOR_LEV[1:0] | OPTST RT |
OPTLO CK |
|||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rs | rs |
||||
| Bit 31 | IWDG_STOP: Independent watchdog counter freeze in Stop mode |
|
0: Freeze IWDG counter in STOP mode. |
|
| Bit 30 | IWDG_STDBY: Independent watchdog counter freeze in standby mode |
|
0: Freeze IWDG counter in standby mode. 1: IWDG counter active in standby mode. |
|
| Bit 29 | nDBANK: Not dual bank mode |
|
1: The Flash user area is seen as a single bank with 256 bits read access. |
|
| Bit 28 | nDBOOT: Dual Boot mode (valid only when nDBANK=0) |
|
Dual Boot mode (valid only when nDBANK=0) |
|
| Bits 27:16 | nWRP[11:0]: Not write protect |
|
if nDBANK=1 (Single bank mode) if nDBANK=0 (Dual bank mode) |
|
| Bits 15:8 | RDP[7:0]: Read protect |
|
These bits contain the value of the read-protection option level after reset. They can be written to program a new read protection value into Flash memory. |
|
| Bits 7:4 | USER: User option bytes |
|
These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory. nRST_STDBY nRST_STOP IWDG_SW WWDG_SW |
|
| Bits 3:2 | BOR_LEV[1:0]: BOR reset Level |
|
These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD) drops below the selected BOR level, a device reset is generated. For full details on BOR characteristics, refer to the “Electrical characteristics” section of |
|
| Bit 1 | OPTSTRT: Option start |
|
This bit triggers a user option operation when set. It is set only by software and cleared when the BSY bit is cleared. |
|
| Bit 0 | OPTLOCK: Option lock |
|
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This bit is cleared by hardware after detecting the unlock sequence. |
Note: When modifying the IWDG_SW, IWDG_STOP or IWDG_STDBY option byte, a system
reset is required to make the change effective.
The FLASH_OPTCR1 register is used to modify the user option bytes.
Address offset: 0x18
Reset value: 0x0040 0080 (ITCM-FLASH). The option bytes are loaded with values from Flash memory at reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 |
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| BOOT_ADD1[15:0] |
BOOT_ADD0[15:0] |
| rw |
| rw |
| Bits 31:16 | BOOT_ADD1[15:0]: Boot base address when Boot pin =1 |
|
BOOT_ADD1[15:0] correspond to address [29:14], |
|
| Bits 15:0 | BOOT_ADD0[15:0]: Boot base address when Boot pin =0 |
|
BOOT_ADD0[15:0] correspond to address [29:14], |
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
FLASH_ACR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARTRST | Res. | ARTEN | PRFTEN | Res. | Res. | Res. | Res. | LATENCY[3:0] |
|||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x04 |
FLASH_KEYR | KEY[31:16] | KEY[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x08 |
FLASH_ OPTKEYR |
OPTKEYR[31:16] | OPTKEYR[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C |
FLASH_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BSY | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ERSERR | PGPERR | PGAERR | WRPERR | Res. | Res. | OPERR | EOP |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x10 |
FLASH_CR
|
LOCK | Res. | Res. | Res. | Res. | Res. | ERRIE | EOPIE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STRT | MER2 | Res. | Res. | Res. | Res. | Res. | PSIZE[1:0] | SNB[4:0] |
MER/MER1 | SER | PG | |||||
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x14 |
FLASH_OPTCR
|
IWDG_STOP | IWDG_STDBY | nDBANK | nDBOOT | nWRP[11:0] | RDP[7:0] |
nRST_STDBY | nRST_STOP | IWDG_SW | WWDG_SW | BOR_LEV[1:0] | OPTSTRT | OPTLOCK | |||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
| 0x18 |
FLASH_ OPTCR1 |
BOOT_ADD1[15:0] | BOOT_ADD0[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
The device requires a 1.8 to 3.6 V operating voltage supply (VDD). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the VBAT voltage when the main VDD supply is powered off.
Note: Depending on the operating power supply range, some peripheral may be used with limited
functionality and performance. For more details refer to section "General operating
conditions" in STM32F76xxx and STM32F77xxx datasheets.
| (omitted) |
To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on VREF. The voltage on VREF ranges from 1.8 V to VDDA.
The VDDUSB is an independent USB power supply for full speed transceivers (USB OTG FS and USB OTG HS in FS mode). It can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer Figure 6 and Figure 7). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected:
| (omitted) |
| (omitted) |
The VDDSDMMC is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7, PG9..12). It can be connected either to VDD or an external independent power supply.
For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to VDDSDMMC. When the VDDSDMMC is connected to a separated power supply, it is independent from VDD and VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected:
The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins:
If DSI functionality is not used at all, then:
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source.
To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT
pin powers the following blocks:
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset block.
Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR
is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with a 100 nF external decoupling ceramic capacitor in parallel.
When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available:
Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PI8 and PC13 to PC15 are restricted: the speed has to be limited to 2 MHz with a
maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available:
Backup domain access
After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 32 backup data registers (128 bytes) which are reset when a tamper detection event occurs. For more details refer to Section 32:
Real-time clock (RTC).
Backup SRAM
The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or VBAT mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when VBAT is always present.
When the backup domain is supplied by VDD (analog switch connected to VDD), the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life.
When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the backup SRAM is powered by a dedicated low-power regulator. This regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and VBAT modes or not. The power-down of this regulator is controlled
by a dedicated bit, the BRE control bit of the PWR_CSR1 register (see Section 4.4.2: PWR
power control/status register (PWR_CSR1)).
The backup SRAM is not mass erased by an tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. Refer to the description of Read protection (RDP) option byte.
| (omitted) |
An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires two external capacitors to be connected to two dedicated pins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be connected either to VSS or VDD to activate or deactivate the voltage regulator. These pins depend on the package.
When activated by software, the voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes (Run, Stop, or Standby mode).
In Run mode, the main regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale 3 can be configured through VOS[1:0] bits of the PWR_CR1 register). The scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock source. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected.
The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency. After exit from Stop mode, the voltage
scale 3 is automatically selected.(see Section 4.4.1: PWR power control register
(PWR_CR1).
2 operating modes are available:
In Stop mode: the main regulator or low-power regulator supplies a low-power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM.
The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured by software as follows:
Note: Over-drive and under-drive mode are not available when the regulator is bypassed.
For more details, refer to the voltage regulator section in the datasheets.
| Voltage regulator configuration | Run mode | Sleep mode | Stop mode | Standby mode |
|---|---|---|---|---|
| Normal mode | MR | MR | MR or LPR | - |
| Over-drive mode(2) |
MR | MR | - | - |
| Under-drive mode | - | - | MR or LPR | - |
| Power-down mode | - | - | - | Yes |
Entering Over-drive mode
It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase.
To enter Over-drive mode, follow the sequence below:
Note: The PLLI2S and PLLSAI can be configured at the same time as the system PLL.
During the Over-drive switch activation, no peripheral clocks should be enabled. The
peripheral clocks must be enabled once the Over-drive mode is activated.
Entering Stop mode disables the Over-drive mode, as well as the PLL. The application
software has to configure again the Over-drive mode and the PLL after exiting from Stop
mode.
Exiting from Over-drive mode
It is recommended to exit from Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE.There are two sequences that allow exiting from over-drive mode:
Example of sequence 1:
Example of sequence 2:
Note: During step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not
active (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled
and the voltage regulator is switched back to the initial voltage.
The device has an integrated POR/PDR circuitry that allows proper operation starting
from 1.8 V.
The device remains in Reset mode when VDD/VDDA is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.
| (omitted) |
During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified VBOR threshold.
VBOR is configured through device option bytes. By default, BOR is off. 3 programmable VBOR threshold levels can be selected:
Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section in
the device datasheet.
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is generated.
The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR (see Section 4.2.1: Power-on reset (POR)/power-down reset (PDR)).
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).
| (omitted) |
You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.
| (omitted) |
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.
The devices feature three low-power modes:
In addition, the power consumption in Run mode can be reduce by one of the following means:
Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M7 System Control register is set on Return from ISR.
Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending.
Exiting low-power mode
The MCU exits from Sleep and Stop modes low-power mode depending on the way the low-power mode was entered:
NVIC IRQ interrupt:
When SEVONPEND = 0 in the Cortex®-M7 System Control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
When SEVONPEND = 1 in the Cortex®-M7 System Control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones.Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
Event
This is done by configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.
The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 348: RTC block diagram).
After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
| Mode name | Entry | Wakeup | Effect on 1.2 V domain clocks |
Effect on VDD domain clocks |
Voltage regulator |
|---|---|---|---|---|---|
| Sleep (Sleep now or Sleep-on- exit) |
WFI | Any interrupt | CPU CLK OFF no effect on other clocks or analog clock sources |
None | ON |
| WFE | Wakeup event | ||||
| Stop | SLEEPDEEP bit + WFI or WFE |
Any EXTI line (configured in the EXTI registers, internal and external lines) |
All 1.2 V domain clocks OFF |
HSI and HSE oscillators OFF |
Main regulator or Low-Power regulator (depends on PWR power control register (PWR_CR1) |
|
Standby
|
PDDS bit + SLEEPDEEP bit + WFI or WFE | WKUP pin rising or falling edge, RTC alarm (Alarm A or Alarm B), RTC Wakeup event, RTC tamper events, RTC time stamp event, external reset in NRST pin, IWDG reset |
OFF |
| Peripheral |
Run | Sleep | Stop | Standby |
VBAT | ||||
|---|---|---|---|---|---|---|---|---|---|
| Wakeup | Wakeup | ||||||||
| CPU | Y | - | - | - | - | - | - |
||
| Flash access | Y | Y | - | - | - | - | - |
||
| DTCM RAM | Y | Y | Y | - | - | - |
|||
| ITCM RAM | Y | Y | Y | - | - | - |
|||
| SRAM1 | Y | Y | Y | - | - | - | - |
||
| SRAM2 | Y | Y | Y | - | - | - | - |
||
| FMC | O | O | - | - | - | - | - |
||
| QUADSPI | O | O | - | - | - | - | - |
||
| Backup Registers | Y | Y | Y | - | Y | - | Y |
||
| Backup RAM | Y | Y | Y | - | Y | - | Y |
||
| Brown-out reset (BOR) | Y | Y | Y | Y | Y | Y |
|||
| Programmable Voltage Detector (PVD) | O | O | O | O | - | - | - |
||
| High Speed Internal (HSI) | O | O | (2) | - | - | - | - |
||
| High Speed External (HSE) | O | O | - | - | - | - | - |
||
| Low Speed Internal (LSI) | O | O | O | - | O | - | - |
||
| Low Speed External (LSE) | O | O | O | - | O | - | O |
||
| RTC | O | O | O | O | O | O | O | ||
| Number of RTC tamper pins | 3 | 3 | 3 | 3 | 3 | 3 | 2 |
||
| CRC calculation unit | O | O | - | - | - | - | - |
||
| GPIOs | Y | Y | Y | Y | 6 pins | 2 tamper |
|||
| DMA | O | O | - | - | - | - | - |
||
| Chrom-Art Accelerator (DMA2D) | O | O | - | - | - | - | - |
||
| LCD-TFT | O | O | - | - | - | - | - |
||
| DCMI | O | O | - | - | - | - | - |
||
| USARTx (x=1..8) | O | O | - | - | - | - | - |
||
| I2Cx (x=1,2,3,4) | O | O | - | - | - | - | - |
||
| SPIx (x=1..6) | O | O | - | - | - | - | - |
||
| SAIx (x=1,2) | O | O | - | - | - | - | - |
||
| SPDIFRX | O | O | - | - | - | - | - |
||
| ADCx (x=1,2,3) | O | O | - | - | - | - | - |
||
| DACx (x=1,2) | O | O | - | - | - | - | - |
||
| Temperature sensor | O | O | - | - | - | - | - |
||
| Timers (TIMx) | O | O | - | - | - | - | - |
||
| Low-power timer 1 (LPTIM1) | O | O | O | O | - | - | - |
||
| Independent watchdog (IWDG) | O | O | O | O | O | O | - |
||
| Window watchdog (WWDG) | O | O | - | - | - | - | - |
||
| Systick timer | O | O | - | - | - | - | - |
||
| Random number generator (RNG) | O | O | - | - | - | - | - |
||
| Cryptographic processor (CRYP) | O | O | - | - | - | - | - |
||
| Hash processor (HASH) | O | O | - | - | - | - |
|||
| SDMMC1, SDMMC2 | O | O | - | - | - | - | - |
||
| CANx (x=1,3) | O | O | - | - | - | - | - |
||
| USB OTG FS | O | O | - | O | - | - | - |
||
| USB OTG HS | O | O | - | O | - | - | - |
||
| Ethernet | O | O | - | O | - | - | - |
||
| HDMI-CEC | O | O | - | - | - | - | - |
||
| DSI-Host | O | O | - | - | - | - | - |
||
| JPEG codec | O | O | - | - | - | - | - |
||
| MDIO slave | O | O | O | O | - | - | - |
||
| DFSDM1 | O | O | - | - | - | - | - |
||
By default, the debug connection is lost when the devices enters in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M7 core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 40.16.1: Debug support for low-power modes.
Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.
For more details refer to Section 5.3.3: RCC clock configuration register (RCC_CFGR).
Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 peripheral clock enable register (RCC_AHB3ENR) (see Section 5.3.10: RCC AHB1
peripheral clock register (RCC_AHB1ENR), Section 5.3.11: RCC AHB2 peripheral clock
enable register (RCC_AHB2ENR), and Section 5.3.12: RCC AHB3 peripheral clock enable
register (RCC_AHB3ENR).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
Entering low-power mode
Low-power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE (Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M7 System Control register is set on Return from ISR.
Exiting low-power mode
From Sleep and Stop modes the MCU exits low-power mode depending on the way the mode was entered:
NVIC IRQ interrupt
- When SEVEONPEND=0 in the Cortex®-M7 System Control register.
By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- When SEVEONPEND=1 in the Cortex®-M7 System Control register.
By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and (when enabled) the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones.
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.
From Standby mode the MCU exits Low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event (see Figure 348: RTC block diagram).
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex®-M7 System Control register:
Refer to Table 17 and Table 18 for details on how to enter Sleep mode.
Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 17 and Table 18 for more details on how to exit Sleep mode.
| Sleep-now mode | Description |
|---|---|
|
Mode entry
|
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Refer to the Cortex®-M7 System Control register. |
|
On Return from ISR while:
Refer to the Cortex®-M7 System Control register. |
|
|
Mode exit
|
If WFI or Return from ISR was used for entry: Interrupt: Refer to Table 43: STM32F75xxx and STM32F74xxx vector If WFE was used for entry and SEVONPEND = 0 Wakeup event: Refer to Section 11.3: Wakeup event management If WFE was used for entry and SEVONPEND = 1 Interrupt even when disabled in NVIC: refer to Table 43: STM32F75xxx |
| Wakeup latency | None |
| Sleep-on-exit | Description |
|---|---|
|
Mode entry
|
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Refer to the Cortex®-M7 System Control register. |
|
On Return from ISR while:
Refer to the Cortex®-M7 System Control register. |
|
| Mode exit | Interrupt: refer to Table 43: STM32F75xxx and STM32F74xxx vector table |
| Wakeup latency | None |
The Stop mode is based on the Cortex®-M7 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
In Stop mode, the power consumption can be further reduced by using additional settings in the PWR_CR1 register. However this will induce an additional startup delay when waking up from Stop mode (see Table 19).
| Voltage Regulator Mode | UDEN[1:0] bits | MRUDS bit | LPUDS bit |
LPDS bit | FPDS bit | Wakeup latency |
|
|---|---|---|---|---|---|---|---|
| Normal mode |
STOP MR (Main Regulator) |
- | 0 | - | 0 | 0 | HSI RC startup time |
| STOP MR- FPD | - | 0 | - | 0 | 1 |
HSI RC startup time + Flash wakeup time from power- |
|
| STOP LP | - | 0 | 0 | 1 | 0 |
HSI RC startup time + regulator wakeup time from LP mode |
|
| STOP LP-FPD | - | - | 0 | 1 | 1 |
HSI RC startup time + Flash wakeup time from power- regulator wakeup time from LP mode |
|
| Under- drive Mode |
STOP UMR- FPD |
3 | 1 | - | 0 | - |
HSI RC startup time + Flash wakeup time from power- Main regulator wakeup time from under-drive mode + Core logic to nominal mode |
| STOP ULP-FPD | 3 | - | 1 | 1 | - |
HSI RC startup time + Flash wakeup time from power- regulator wakeup time from LP under-drive mode + Core logic to nominal mode |
|
I/O states in Stop mode
In stop mode, all I/Os pins keep the same state as in the run mode
Entering Stop mode
The Stop mode is entered according to Entering low-power mode, when the SLEEPDEEP bit in Cortex®-M7 System Control register is set.
Refer to Table 20 for details on how to enter the Stop mode.
When the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power or low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and UDEN bits of the PWR power control register (PWR_CR1).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.
If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled during when the Stop mode is activated.
In Stop mode, the following features can be selected by programming individual control bits:
The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.
Note: Before entering Stop mode, it is recommended to enable the clock security system (CSS)
feature to prevent external oscillator (HSE) failure from impacting the internal MCU
behavior.
Exiting Stop mode
Refer to Table 20 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.
When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.
| Stop mode | Description |
|---|---|
|
Mode entry
|
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
|
On Return from ISR while:
|
|
|
Note: To enter Stop mode, all EXTI Line pending bits (in Pending register |
|
|
Mode exit
|
If WFI or Return from ISR was used for entry: All EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 46: STM32F76xxx and STM32F77xxx vector table on page 313. If WFE was used for entry and SEVONPEND = 0: All EXTI Lines configured in event mode. Refer to Section 11.3: Wakeup If WFE was used for entry and SEVONPEND = 1:
|
| Wakeup latency | Refer to Table 19: Stop operating modes |
The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex®-M7 deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see Figure 5).
Entering Standby mode
The Standby mode is entered according to Entering low-power mode, when the SLEEPDEEP bit in the Cortex®-M7 System Control register is set.
Refer to Table 21 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control bits:
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG Reset, a rising or falling edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp
event is detected. All registers are reset after wakeup from Standby except for PWR power
control/status register (PWR_CSR1).
After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, vector reset is fetched, etc.). The SBF status flag in the PWR
power control/status register (PWR_CSR1) indicates that the MCU was in Standby mode.
Refer to Table 21 for more details on how to exit Standby mode.
| Standby mode | Description |
|---|---|
|
Mode entry
|
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
|
On return from ISR while:
|
|
|
Mode exit
|
WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. |
| Wakeup latency | Reset phase. |
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
The MCU can be woken up from a low-power mode by an RTC alternate function.
The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and Standby low-power modes.
The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.
The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.
For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register
(RCC_BDCR):
RTC alternate functions to wake up the device from the Stop mode
RTC alternate functions to wake up the device from the Standby mode
Safe RTC alternate function wakeup flag clearing sequence
To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:
Address offset: 0x00
Reset value: 0x0000 C000 (reset by wakeup from Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDEN[1:0] | ODSWE N |
ODEN |
VOS[1:0] | ADCDC1 | Res. | MRUDS | LPUDS | FPDS | DBP | PLS[2:0] | PVDE | CSBF | Res. | PDDS | LPDS |
||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rc_w1 | rw | rw |
||||||||||||||
| Bits 31:20 | Reserved, must be kept at reset value. |
| Bits 19:18 | UDEN[1:0]: Under-drive enable in stop mode |
|
These bits are set by software. They allow to achieve a lower power consumption in Stop mode but with a longer wakeup time. |
|
| Bit 17 | ODSWEN: Over-drive switching enabled. |
|
This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode. On any over-drive switch (enabled or disabled), the system clock will be stalled during |
|
| Bit 16 | ODEN: Over-drive enable |
|
This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode. It is used to enabled the Over-drive mode in order to reach a higher frequency. To set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the ODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be set before setting the ODSWEN bit. |
|
| Bits 15:14 | VOS[1:0]: Regulator voltage scaling output selection |
|
These bits control the main internal voltage regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the STM32F76xxx and STM32F77xxx datasheets for more details). |
|
| Bit 13 | ADCDC1: |
|
0: No effect. 1: Refer to AN4073 for details on how to use this bit.
This bit can only be set when operating at supply voltage range 2.7 to 3.6V.
|
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bit 11 | MRUDS: Main regulator in deepsleep under-drive mode |
|
This bit is set and cleared by software. 0: Main regulator ON when the device is in Stop mode |
|
| Bit 10 | LPUDS: Low-power regulator in deepsleep under-drive mode |
|
This bit is set and cleared by software. 0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode |
|
| Bit 9 | FPDS: Flash power-down in Stop mode |
|
When set, the Flash memory enters power-down mode when the device enters Stop mode. This allows to achieve a lower consumption in stop mode but a longer restart time. |
|
| Bit 8 | DBP: Disable backup domain write protection |
|
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), and the BRE bit of the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and RTC Backup registers and backup SRAM disabled |
|
| Bits 7:5 | PLS[2:0]: PVD level selection |
|
These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.0 V
Refer to the electrical characteristics of the datasheet for more details.
These bits cannot be reset by a peripheral reset through the PWRRST bit in the
These bits are write protected when PVD_LOCK is set in the system configuration.
|
|
| Bit 4 | PVDE: Power voltage detector enable |
|
This bit is set and cleared by software. 0: PVD disabled
This bit cannot be reset by a peripheral reset through the PWRRST bit in the
This bit is write protected when PVD_LOCK is set in the system configuration.
|
|
| Bit 3 | CSBF: Clear standby flag |
|
This bit is always read as 0. 0: No effect |
|
| Bit 2 | Reserved, must be kept at reset value |
| Bit 1 | PDDS: Power-down deepsleep |
|
This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit. |
|
| Bit 0 | LPDS: Low-power deepsleep |
|
This bit is set and cleared by software. It works together with the PDDS bit. 0:Main voltage regulator ON during Stop mode |
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDRDY[1:0] | ODSWRDY | ODRDY |
Res. | VOS RDY |
Res. | Res. | Res. | Res. | BRE | Res. | Res. | Res. | Res. | Res. | BRR | PVDO | SBF | WUIF |
|
| rc_w1 | rc_w1 | r | r |
r | rw | r | r | r | r |
||||||||||||||||||||||
| Bits 31:20 | Reserved, must be kept at reset value. |
| Bits 19:18 | UDRDY[1:0]: Under-drive ready flag |
|
These bits are set by hardware when MCU enters stop Under-drive mode and exits. When the Under-drive mode is enabled, these bits are not set as long as the MCU has not entered stop mode yet. they are cleared by programming them to 1. |
|
| Bit 17 | ODSWRDY: Over-drive mode switching ready |
|
0: Over-drive mode is not active. |
|
| Bit 16 | ODRDY: Over-drive mode ready |
|
0: Over-drive mode not ready. |
|
| Bit 14 | VOSRDY: Regulator voltage scaling output selection ready bit |
|
0: Not ready 1: Ready |
|
| Bits 13:10 | Reserved, must be kept at reset value. |
| Bit 9 | BRE: Backup regulator enable |
|
When set, the Backup regulator (used to maintain backup SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the RAM will be maintained in the Standby and VBAT modes. This bit is not reset when the device wakes up from Standby mode, by a system reset, |
|
| Bits 8:4 | Reserved, must be kept at reset value. |
| Bit 3 | BRR: Backup regulator ready |
|
Set by hardware to indicate that the Backup Regulator is ready. This bit is not reset when the device wakes up from Standby mode or by a system reset |
|
| Bit 2 | PVDO: PVD output |
|
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits. The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after |
|
| Bit 1 | SBF: Standby flag |
|
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR1) |
|
| Bit 0 | WUIF: Wakeup internal flag |
|
This bit is set when a wakeup is detected on the internal wakeup line in standby mode. It is cleared when all internal wakeup sources are cleared. |
Address offset: 0x08
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | WUPP6 | WUPP5 | WUPP4 | WUPP3 | WUPP2 | WUPP1 | Res. | Res. | CWUPF6 | CWUPF5 | CWUPF4 | CWUPF3 | CWUPF2 | CWUPF1 |
| rw | rw | rw | rw | rw | rw | r | r | r | r | r | r |
| Bits 31:14 | Reserved, always read as 0. |
| Bit 13 | WUPP6: Wakeup pin polarity bit for PI11 |
|
These bits define the polarity used for event detection on external wake-up pin PI11. |
|
| Bit 12 | WUPP5: Wakeup pin polarity bit for PI8 |
|
These bits define the polarity used for event detection on external wake-up pin PI8. |
|
| Bit 11 | WUPP4: Wakeup pin polarity bit for PC13 |
|
These bits define the polarity used for event detection on external wake-up pin PC13. |
|
| Bit 10 | WUPP3: Wakeup pin polarity bit for PC1 |
|
These bits define the polarity used for event detection on external wake-up pin PC1. |
|
| Bit 9 | WUPP2: Wakeup pin polarity bit for PA2 |
|
These bits define the polarity used for event detection on external wake-up pin PA2. |
|
| Bit 8 | WUPP1: Wakeup pin polarity bit for PA0 |
|
These bits define the polarity used for event detection on external wake-up pin PA0. |
|
| Bits 7:6 | Reserved, always read as 0 |
| Bit 5 | CWUPF6: Clear Wakeup Pin flag for PI11 |
|
These bits are always read as 0 |
|
| Bit 4 | CWUPF5: Clear Wakeup Pin flag for PI8 |
|
These bits are always read as 0 |
|
| Bit 3 | CWUPF4: Clear Wakeup Pin flag for PC13 |
|
These bits are always read as 0 |
|
| Bit 2 | CWUPF3: Clear Wakeup Pin flag for PC1 |
|
These bits are always read as 0 |
|
| Bit 1 | CWUPF2: Clear Wakeup Pin flag for PA2 |
|
These bits are always read as 0 |
|
| Bit 0 | CWUPF1: Clear Wakeup Pin flag for PA0 |
|
These bits are always read as 0 |
Address offset: 0x0C
Reset value: 0x0000 0000 (reset by wakeup from Standby mode, except wakeup flags which are reset by RESET pin)
Additional APB cycles are needed to read this register versus a standard APB read.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | EWUP6 | EWUP5 | EWUP4 | EWUP3 | EWUP2 | EWUP1 | Res. | Res. | WUPF6 | WUPF5 | WUPF4 | WUPF3 | WUPF2 | WUPF1 |
| rw | rw | rw | rw | rw | rw | r | r | r | r | r | r |
| Bits 31:14 | Reserved, always read as 0. |
| Bit 13 | EWUP6: Enable Wakeup pin for PI11 |
|
This bit is set and cleared by software. |
|
| Bit 12 | EWUP5: Enable Wakeup pin for PI8 |
|
This bit is set and cleared by software. |
|
| Bit 11 | EWUP4: Enable Wakeup pin for PC13 |
|
This bit is set and cleared by software. |
|
| Bit 10 | EWUP3: Enable Wakeup pin for PC1 |
|
This bit is set and cleared by software. |
|
| Bit 9 | EWUP2: Enable Wakeup pin for PA2 |
|
This bit is set and cleared by software. |
|
| Bit 8 | EWUP1: Enable Wakeup pin for PA0 |
|
This bit is set and cleared by software. |
|
| Bits 7:6 | Reserved, always read as 0 |
| Bit 5 | WUPF6: Wakeup Pin flag for PI11 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF6 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP6 |
|
| Bit 4 | WUPF5: Wakeup Pin flag for PI8 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF5 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP5 |
|
| Bit 3 | WUPF4: Wakeup Pin flag for PC13 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF4 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP4 |
|
| Bit 2 | WUPF3: Wakeup Pin flag for PC1 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF3 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP3 |
|
| Bit 1 | WUPF2: Wakeup Pin flag for PA2 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF2 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP2 |
|
| Bit 0 | WUPF1: Wakeup Pin flag for PA0 |
|
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF1 bit in the PWR power control register 2 (PWR_CR2). An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP1 |
The following table summarizes the PWR registers.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 |
PWR_CR1 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDEN[1:0] | ODSWEN | ODEN | VOS[1:0] | ADCDC1 | Res. | MRUDS | LPUDS | FPDS | DBP | PLS[2:0] |
PVDE | CSBF | Res. | PDDS | LPDS | ||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x004 |
PWR_CSR1 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDRDY[1:0] | ODSWRDY | ODRDY | Res. | VOSRDY | Res. | Res. | Res. | Res. |
0 BRE |
Res. | Res. | Res. | Res. | Res. |
0 BRR |
0 PVDO |
0 SBF |
0 WUIF |
|
| 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||||
| 0x008 |
PWR_CR2 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
0 WUPP6 |
0 WUPP5 |
0 WUPP4 |
0 WUPP3 |
0 WUPP2 |
0 WUPP1 |
Res. | Res. |
0 CWUPF6 |
0 CWUPF5 |
0 CWUPF4 |
0CWUPF3 | 0CWUPF2 |
0CWUPF1 |
| 0x00C |
PWR_CSR2 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
0 EWUP6 |
0 EWUP5 |
0 EWUP4 |
0 EWUP3 |
0 EWUP2 |
0 EWUP1 |
Res. | Res. | 0WUPF6 | 0WUPF5 | 0WUPF4 | 0WUPF3 | 0WUPF2 | 0WUPF1 |
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
There are three types of reset, defined as system Reset, power Reset and backup domain Reset.
A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 12).
A system reset is generated when one of the following events occurs:
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex®-M7 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex®-M7 technical reference manual for more details.
Low-power management reset
There are two ways of generating a low-power management reset:
Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering the Standby mode.
Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode.
A power reset is generated when one of the following events occurs:
A power reset sets all registers to their reset values except the Backup domain (see Figure 12)
These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.
| (omitted) |
The Backup domain has two specific resets that affect only the Backup domain (see Figure 12).
The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. The BKPSRAM is not affected by this reset. The only way of resetting the BKPSRAM is through the Flash interface by requesting a protection level change from 1 to 0.
A backup domain reset is generated when one of the following events occurs:
Three different clock sources can be used to drive the system clock (SYSCLK):
The devices have the two following secondary clock sources:
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
| (omitted) |
The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency
All peripheral clocks are derived from their bus clock (HCLK,PLCK1, PCLK2) except for:
I2S clock
To achieve high-quality audio performance, the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For more information about I2S clock frequency and precision, refer to Section 35.7.5:
Clock generator.
LTDC clock
The LTDC clock is generated from a specific PLL (PLLSAI). LTCD clock is not only used by LCD TFT controller but also by DSI HOST.
Section 42.4.4: MII/RMII selection in the Ethernet peripheral description. When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.
If TIMPRE bit in RCC_DKCFGR1 register is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock frequencies (TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
If TIMPRE bit in RCC_DKCFGR1 register is set:
If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four times the frequency of the APB domain to which the timers are connected: TIMxCLK = 4xPCLKx.
The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock (HCLK), configurable in the SysTick control and status register.
FCLK acts as Cortex®-M7 free-running clock. For more details, refer to the Cortex®-M7 technical reference manual.
The high speed external clock signal (HSE) can be generated from two possible clock sources:
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
| (omitted) |
External source (HSE bypass)
In this mode, an external clock source must be provided. You select this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left HI-Z. See Figure 14.
External crystal/ceramic resonator (HSE crystal)
The HSE has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 14. Refer to the electrical characteristics section of the datasheet for more details.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the RCC clock control register (RCC_CR).
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.7: Clock security system (CSS) on page 158.
The devices feature three PLLs:
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as PLL clock source, and configuration of division factors M, N, P, and Q).
The PLLI2S and PLLSAI use the same input clock as PLL (PLLM[5:0] and PLLSRC bits are common to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable and division factors (N and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, the configuration parameters cannot be changed.
The three PLLs are disabled by hardware when entering Stop and Standby modes, or when an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC
PLL configuration register (RCC_PLLCFGR), RCC clock configuration register
(RCC_CFGR) and RCC dedicated clocks configuration register (RCC_DCKCFGR1) can be used to configure PLL, PLLI2S, and PLLSAI.
The LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE oscillator is switched on and off using the LSEON bit in RCC backup domain
control register (RCC_BDCR).
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock
interrupt register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left HI-Z. See Figure 14.
The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the RCC clock control &
status register (RCC_CSR).
The LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
After a system reset, the HSI oscillator is selected as the system clock. When a clock source is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source is ready. Status bits in the RCC clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as the system clock.
The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M7 NMI (non-maskable interrupt) exception vector.
Note: When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the failure occurred, PLL is also disabled. In this case, if the PLLI2S or PLLSAI was enabled, it is also disabled when the HSE fails.
Once the RTCCLK clock source has been selected, the only possible way of modifying the selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC
clock configuration register (RCC_CFGR). This selection cannot be modified without resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not guaranteed if the system supply disappears. If the HSE oscillator divided by a value between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a consequence:
Note: To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
If the independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.
Two microcontroller clock output (MCO) pins are available:
MCO1
You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5):
The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in the RCC clock configuration register (RCC_CFGR).
MCO2
You can output four different clock sources onto the MCO2 pin (PC9) using the configurable prescaler (from 1 to 5):
The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the RCC clock configuration register (RCC_CFGR).
For the different MCO pins, the corresponding GPIO port has to be programmed in alternate function mode.
It is possible to indirectly measure the frequencies of all on-board clock source generators by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 15
and Figure 15.
Internal/external clock measurement using TIM5 channel4
TIM5 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits in the TIM5_OR register.
The primary purpose of having the LSE connected to the channel4 input capture is to be able to precisely measure the HSI (this requires to have the HSI used as the system clock source). The number of HSI clock counts between consecutive edges of the LSE signal provides a measurement of the internal clock period. Taking advantage of the high precision
of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.
The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement.
It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal. The ultra-low-power LSI oscillator has a large manufacturing process deviation: by measuring it versus the HSI clock source, it is possible to determine its frequency with the precision of the HSI. The measured value can be used to have more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an IWDG timeout with an acceptable accuracy.
Use the following procedure to measure the LSI frequency:
| (omitted) |
Internal/external clock measurement using TIM11 channel1
TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is connected to channel 1 input capture to have a rough indication of the external crystal frequency. This requires that the HSI is the system clock source. This can be useful for instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be able to determine harmonic or subharmonic frequencies (–50/+100% deviations).
| (omitted) |
Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR or RCC_APBxENRy registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are not supported.The peripheral enable bit has a synchronization mechanism to create a glitch free clock for the peripheral.
After the enable bit is set, there is a 2 peripheral clock cycles delay before the clock being active.
Caution: Just after enabling the clock for a peripheral, software must wait for a 2 peripheral clock cycles delay before accessing the peripheral registers.
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | PLLSAI RDY |
PLLSAI ON |
PLLI2S RDY |
PLLI2S ON |
PLLRD Y |
PLLON | Res. | Res. | Res. | Res. | CSS ON |
HSE BYP |
HSE RDY |
HSE ON |
HSICAL[7:0] | HSITRIM[4:0] | Res. | HSI RDY | HSION |
|||||||||||
| r | rw | r | rw | r | rw | rw | rw | r | rw |
r | r | r | r | r | r | r | r | rw | rw | rw | rw | rw | r | rw |
|||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bit 29 | PLLSAIRDY: PLLSAI clock ready flag |
|
Set by hardware to indicate that the PLLSAI is locked. |
|
| Bit 28 | PLLSAION: PLLSAI enable |
|
Set and cleared by software to enable PLLSAI. |
|
| Bit 27 | PLLI2SRDY: PLLI2S clock ready flag |
|
Set by hardware to indicate that the PLLI2S is locked. |
|
| Bit 26 | PLLI2SON: PLLI2S enable |
|
Set and cleared by software to enable PLLI2S. |
|
| Bit 25 | PLLRDY: Main PLL (PLL) clock ready flag |
|
Set by hardware to indicate that PLL is locked. |
|
| Bit 24 | PLLON: Main PLL (PLL) enable |
|
Set and cleared by software to enable PLL. |
|
| Bits 23:20 | Reserved, must be kept at reset value. |
| Bit 19 | CSSON: Clock security system enable |
|
Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected. |
|
| Bit 18 | HSEBYP: HSE clock bypass |
|
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. |
|
| Bit 17 | HSERDY: HSE clock ready flag |
|
Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, HSERDY goes low after 6 HSE oscillator clock cycles. |
|
| Bit 16 | HSEON: HSE clock enable |
|
Set and cleared by software. |
|
| Bits 15:8 | HSICAL[7:0]: Internal high-speed clock calibration |
|
These bits are initialized automatically at startup. |
|
| Bits 7:3 | HSITRIM[4:0]: Internal high-speed clock trimming |
|
These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | HSIRDY: Internal high-speed clock ready flag |
|
Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 HSI clock cycles. |
|
| Bit 0 | HSION: Internal high-speed clock enable |
|
Set and cleared by software. |
Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | PLLR[2:0] | PLLQ[3:0] | Res. | PLLSR C |
Res. | Res. | Res. | Res. | PLLP[1:0] |
Res. | PLLN[8:0] | PLLM[5:0] |
|||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:28 | PLLR[2:0]: PLL division factor for DSI clock |
|
Set and reset by software to control the frequency of the DSI clock. |
|
| Bits 27:24 | PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDMMC1/2 and random number generator clocks |
|
Set and cleared by software to control the frequency of USB OTG FS clock, the random number generator clock and the SDMMC clock. These bits should be written only if PLL is disabled. The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC and the random number generator need a frequency lower than or equal to 48 MHz to work correctly. 0000: PLLQ = 0, wrong configuration |
|
| Bit 23 | Reserved, must be kept at reset value. |
| Bit 22 | PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source |
|
Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled. |
|
| Bits 21:18 | Reserved, must be kept at reset value. |
| Bits 17:16 | PLLP[1:0]: Main PLL (PLL) division factor for main system clock |
|
Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled. The software has to set these bits correctly not to exceed 216 MHz on this domain. 00: PLLP = 2 |
|
| Bits 14:6 | PLLN[8:0]: Main PLL (PLL) multiplication factor for VCO |
|
Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLL is disabled. Only half-word and word accesses are allowed to write these bits. The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz. 000000000: PLLN = 0, wrong configuration Between 50 and 99, multiplication factors are possible for VCO input frequency higher |
|
| Bits 5:0 | PLLM[5:0]: Division factor for the main PLLs (PLL, PLLI2S and PLLSAI) input clock |
|
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO. These bits can be written only when the PLL and PLLI2S are disabled. The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. 000000: PLLM = 0, wrong configuration |
Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MCO2 | MCO2 PRE[2:0] | MCO1 PRE[2:0] | I2SSC R |
MCO1 | RTCPRE[4:0] |
PPRE2[2:0] | PPRE1[2:0] | Res. | Res. | HPRE[3:0] | SWS1 | SWS0 | SW1 | SW0 |
|||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | r | r | rw | rw |
||||
| Bits 31:30 | MCO2[1:0]: Microcontroller clock output 2 |
|
Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset before enabling the external oscillators and the PLLs. |
|
| Bits 27:29 | MCO2PRE: MCO2 prescaler |
|
Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs. |
|
| Bits 24:26 | MCO1PRE: MCO1 prescaler |
|
Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLL. |
|
| Bit 23 | I2SSRC: I2S clock selection |
|
Set and cleared by software. This bit allows to select the I2S clock source between the PLLI2S clock and the external clock. It is highly recommended to change this bit only after reset and before enabling the I2S module. |
|
| Bits 22:21 | MCO1: Microcontroller clock output 1 |
|
Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL. |
|
| Bits 20:16 | RTCPRE: HSE division factor for RTC clock |
|
Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock for RTC. The software has to set these bits correctly to ensure that the clock supplied to the RTC is 1 MHz. These bits must be configured if needed before selecting the RTC clock source. 00001: no clock |
|
| Bits 15:13 | PPRE2: APB high-speed prescaler (APB2) |
|
Set and cleared by software to control APB high-speed clock division factor. The software has to set these bits correctly not to exceed 90 MHz on this domain. The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after PPRE2 write. 100: AHB clock divided by 2 |
|
| Bits 12:10 | PPRE1: APB Low-speed prescaler (APB1) |
|
Set and cleared by software to control APB low-speed clock division factor. The software has to set these bits correctly not to exceed 45 MHz on this domain. The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after PPRE1 write. 100: AHB clock divided by 2 |
|
| Bits 9:8 | Reserved, must be kept at reset value. |
| Bits 7:4 | HPRE: AHB prescaler |
|
Set and cleared by software to control AHB clock division factor. The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write. The AHB clock frequency must be at least 25 MHz when the Ethernet is used. 1000: system clock divided by 2 |
|
| Bits 3:2 | SWS: System clock switch status |
|
Set and cleared by hardware to indicate which clock source is used as the system clock. |
|
| Bits 1:0 | SW: System clock switch |
|
Set and cleared by software to select the system clock source. |
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CSSC | PLLSAI RDYC |
PLLI2S RDYC |
PLL RDYC |
HSE RDYC |
HSI RDYC |
LSE RDYC |
LSI RDYC |
Res. | PLLSAI RDYIE |
PLLI2S RDYIE |
PLL RDYIE |
HSE RDYIE |
HSI RDYIE |
LSE RDYIE |
LSI RDYIE | CSSF | PLLSAI RDYF |
PLLI2S RDYF |
PLL RDYF |
HSE RDYF |
HSI RDYF |
LSE RDYF |
LSI RDYF |
| w | w | w | w | w | w | w | w |
rw | rw | rw | rw | rw | rw | rw | r | r | r | r | r | r | r | r |
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bit 23 | CSSC: Clock security system interrupt clear |
|
This bit is set by software to clear the CSSF flag. |
|
| Bit 22 | PLLSAIRDYC: PLLSAI Ready Interrupt Clear |
|
This bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the PLLSAIRDYF is cleared. |
|
| Bit 21 | PLLI2SRDYC: PLLI2S ready interrupt clear |
|
This bit is set by software to clear the PLLI2SRDYF flag. |
|
| Bit 20 | PLLRDYC: Main PLL(PLL) ready interrupt clear |
|
This bit is set by software to clear the PLLRDYF flag. |
|
| Bit 19 | HSERDYC: HSE ready interrupt clear |
|
This bit is set by software to clear the HSERDYF flag. |
|
| Bit 18 | HSIRDYC: HSI ready interrupt clear |
|
This bit is set software to clear the HSIRDYF flag. |
|
| Bit 17 | LSERDYC: LSE ready interrupt clear |
|
This bit is set by software to clear the LSERDYF flag. |
|
| Bit 16 | LSIRDYC: LSI ready interrupt clear |
|
This bit is set by software to clear the LSIRDYF flag. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | PLLSAIRDYIE: PLLSAI Ready Interrupt Enable |
|
This bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock. |
|
| Bit 13 | PLLI2SRDYIE: PLLI2S ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock. |
|
| Bit 12 | PLLRDYIE: Main PLL (PLL) ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by PLL lock. |
|
| Bit 11 | HSERDYIE: HSE ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. |
|
| Bit 10 | HSIRDYIE: HSI ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. |
|
| Bit 9 | LSERDYIE: LSE ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. |
|
| Bit 8 | LSIRDYIE: LSI ready interrupt enable |
|
This bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator stabilization. |
|
| Bit 7 | CSSF: Clock security system interrupt flag |
|
This bit is set by hardware when a failure is detected in the HSE oscillator. |
|
| Bit 6 | PLLSAIRDYF: PLLSAI Ready Interrupt flag |
|
This bit is set by hardware when the PLLSAI is locked and PLLSAIRDYDIE is set. |
|
| Bit 5 | PLLI2SRDYF: PLLI2S ready interrupt flag |
|
This bit is set by hardware when the PLLI2S is locked and PLLI2SRDYDIE is set. |
|
| Bit 4 | PLLRDYF: Main PLL (PLL) ready interrupt flag |
|
This bit is set by hardware when PLL is locked and PLLRDYDIE is set. |
|
| Bit 3 | HSERDYF: HSE ready interrupt flag |
|
This bit is set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. |
|
| Bit 2 | HSIRDYF: HSI ready interrupt flag |
|
This bit is set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. |
|
| Bit 1 | LSERDYF: LSE ready interrupt flag |
|
This bit is set by hardware when the External low-speed clock becomes stable and LSERDYDIE is set. |
|
| Bit 0 | LSIRDYF: LSI ready interrupt flag |
|
This bit is set by hardware when the internal low-speed clock becomes stable and LSIRDYDIE is set. |
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. |
OTGH S RST |
Res. | Res. | Res. | ETHMAC RST |
Res. | DMA2D RST |
DMA2 RST |
DMA1 RST |
Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | CRCR ST |
Res. | GPIOK RST |
GPIOJ RST |
GPIOI RST |
GPIOH RST |
GPIOGG RST |
GPIOF RST |
GPIOE RST |
GPIOD RST |
GPIOC RST |
GPIOB RST |
GPIOA RST |
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bit 29 | OTGHSRST: USB OTG HS module reset |
|
This bit is set and cleared by software. |
|
| Bits 28:26 | Reserved, must be kept at reset value. |
| Bit 25 | ETHMACRST: Ethernet MAC reset |
|
This bit is set and cleared by software. |
|
| Bit 24 | Reserved, must be kept at reset value. |
| Bit 23 | DMA2DRST: DMA2D reset |
|
This bit is set and reset by software. |
|
| Bit 22 | DMA2RST: DMA2 reset |
|
This bit is set and cleared by software. |
|
| Bit 21 | DMA1RST: DMA2 reset |
|
This bit is set and cleared by software. |
|
| Bits 20:13 | Reserved, must be kept at reset value. |
| Bit 12 | CRCRST: CRC reset |
|
This bit is set and cleared by software. |
|
| Bit 11 | Reserved, must be kept at reset value. |
| Bit 10 | GPIOKRST: IO port K reset |
|
This bit is set and cleared by software. |
|
| Bit 9 | GPIOJRST: IO port J reset |
|
This bit is set and cleared by software. |
|
| Bit 8 | GPIOIRST: IO port I reset |
|
This bit is set and cleared by software. |
|
| Bit 7 | GPIOHRST: IO port H reset |
|
This bit is set and cleared by software. |
|
| Bit 6 | GPIOGRST: IO port G reset |
|
This bit is set and cleared by software. |
|
| Bit 5 | GPIOFRST: IO port F reset |
|
This bit is set and cleared by software. |
|
| Bit 4 | GPIOERST: IO port E reset |
|
This bit is set and cleared by software. |
|
| Bit 3 | GPIODRST: IO port D reset |
|
This bit is set and cleared by software. |
|
| Bit 2 | GPIOCRST: IO port C reset |
|
This bit is set and cleared by software. |
|
| Bit 1 | GPIOBRST: IO port B reset |
|
This bit is set and cleared by software. |
|
| Bit 0 | GPIOARST: IO port A reset |
|
This bit is set and cleared by software. |
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFS RST |
RNG RST |
HASH RST |
CRYP RST |
Res. | Res. | JPEG RST |
DCMI RST |
| rw | rw | rw | rw | rw | rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | OTGFSRST: USB OTG FS module reset |
|
Set and cleared by software. |
|
| Bit 6 | RNGRST: Random number generator module reset |
|
Set and cleared by software. |
|
| Bit 5 | HASHRST: Hash module reset |
|
Set and cleared by software. |
|
| Bit 4 | CRYPRST: Cryptographic module reset |
|
Set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | JPEGRST: JPEG module reset |
|
Set and cleared by software. |
|
| Bit 0 | DCMIRST: Camera interface reset |
|
Set and cleared by software. |
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPIRST | FMCRST |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | QSPIRST: Quad SPI memory controller reset |
|
Set and cleared by software. |
|
| Bit 0 | FMCRST: Flexible memory controller module reset |
|
Set and cleared by software. |
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UART8R ST |
UART7R ST |
DACRST | PWR RST |
CECRST | CAN2 RST |
CAN1 RST |
I2C4RST | I2C3 RST |
I2C2 RST |
I2C1 RST |
UART5 RST |
UART4 RST |
UART3 RST |
UART2 RST |
SPDIFR XRST |
SPI3 RST |
SPI2 RST |
CAN3 RST |
Res. | WWDG RST |
Res. | LPTIM1 RST |
TIM14 RST |
TIM13 RST |
TIM12 RST |
TIM7 RST |
TIM6 RST |
TIM5 RST |
TIM4 RST |
TIM3 RST |
TIM2 RST |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | UART8RST: UART8 reset |
|
Set and cleared by software. |
|
| Bit 30 | UART7RST: UART7 reset |
|
Set and cleared by software. |
|
| Bit 29 | DACRST: DAC reset |
|
Set and cleared by software. |
|
| Bit 28 | PWRRST: Power interface reset |
|
Set and cleared by software. |
|
| Bit 27 | CECRST: HDMI-CEC reset |
|
Set and cleared by software. |
|
| Bit 26 | CAN2RST: CAN2 reset |
|
Set and cleared by software. |
|
| Bit 25 | CAN1RST: CAN1 reset |
|
Set and cleared by software. |
|
| Bit 24 | I2C4RST: I2C4 reset |
|
Set and cleared by software. |
|
| Bit 23 | I2C3RST: I2C3 reset |
|
Set and cleared by software. |
|
| Bit 22 | I2C2RST: I2C2 reset |
|
Set and cleared by software. |
|
| Bit 21 | I2C1RST: I2C1 reset |
|
Set and cleared by software. |
|
| Bit 20 | UART5RST: UART5 reset |
|
Set and cleared by software. |
|
| Bit 19 | UART4RST: USART4 reset |
|
Set and cleared by software. |
|
| Bit 18 | USART3RST: USART3 reset |
|
Set and cleared by software. |
|
| Bit 17 | USART2RST: USART2 reset |
|
Set and cleared by software. |
|
| Bit 16 | SPDIFRXRST: SPDIFRX reset |
|
Set and cleared by software. |
|
| Bit 15 | SPI3RST: SPI3 reset |
|
Set and cleared by software. |
|
| Bit 14 | SPI2RST: SPI2 reset |
|
Set and cleared by software. |
|
| Bit 13 | CAN3RST: CAN 3 reset |
|
Set and cleared by software. |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bit 11 | WWDGRST: Window watchdog reset |
|
Set and cleared by software. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bit 9 | LPTIM1RST: Low-power timer 1 reset |
|
Set and cleared by software. 0: does not reset LPTMI1 1: resets LPTMI1 |
|
| Bit 8 | TIM14RST: TIM14 reset |
|
Set and cleared by software. |
|
| Bit 7 | TIM13RST: TIM13 reset |
|
Set and cleared by software. |
|
| Bit 6 | TIM12RST: TIM12 reset |
|
Set and cleared by software. |
|
| Bit 5 | TIM7RST: TIM7 reset |
|
Set and cleared by software. |
|
| Bit 4 | TIM6RST: TIM6 reset |
|
Set and cleared by software. |
|
| Bit 3 | TIM5RST: TIM5 reset |
|
Set and cleared by software. |
|
| Bit 2 | TIM4RST: TIM4 reset |
|
Set and cleared by software. |
|
| Bit 1 | TIM3RST: TIM3 reset |
|
Set and cleared by software. |
|
| Bit 0 | TIM2RST: TIM2 reset |
|
Set and cleared by software. |
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | MDIO RST |
DFSDM1 RST |
Res. | DSI RST |
LTDC RST |
Res. | Res. | SAI2RST | SAI1 RST |
SPI6 RST |
SPI5 RST |
Res. | TIM11 RST |
TIM10 RST |
TIM9 RST |
Res. | SYSCFG RST |
SPI4 RST |
SPI1 RST |
SDMMC1 RST |
Res. | Res. | ADC RST |
SDMMC2 RST |
Res. | USART6 RST |
USART1 RST |
Res. | Res. | TIM8 RST |
TIM1 RST |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 30 | MDIORST: MDIO module reset |
|
This bit is set and reset by software. |
|
| Bit 29 | DFSDM1RST: DFSDM1 module reset |
|
This bit is set and reset by software. |
|
| Bit 28 | Reserved, must be kept at reset value. |
| Bit 27 | DSIRST: DSIHOST module reset |
|
This bit is set and reset by software. |
|
| Bit 26 | LTDCRST: LTDC reset |
|
This bit is set and reset by software. |
|
| Bits 25:24 | Reserved, must be kept at reset value. |
| Bit 23 | SAI2RST: SAI2 reset |
|
This bit is set and cleared by software. |
|
| Bit 22 | SAI1RST: SAI1 reset |
|
This bit is set and reset by software. |
|
| Bit 21 | SPI6RST: SPI6 reset |
|
This bit is set and cleared by software. |
|
| Bit 20 | SPI5RST: SPI5 reset |
|
This bit is set and cleared by software. |
|
| Bit 19 | Reserved, must be kept at reset value. |
| Bit 18 | TIM11RST: TIM11 reset |
|
This bit is set and cleared by software. |
|
| Bit 17 | TIM10RST: TIM10 reset |
|
This bit is set and cleared by software. |
|
| Bit 16 | TIM9RST: TIM9 reset |
|
This bit is set and cleared by software. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | SYSCFGRST: System configuration controller reset |
|
This bit is set and cleared by software. |
|
| Bit 13 | SPI4RST: SPI4 reset |
|
This bit is set and cleared by software. |
|
| Bit 12 | SPI1RST: SPI1 reset |
|
This bit is set and cleared by software. |
|
| Bit 11 | SDMMC1RST: SDMMC1 reset |
|
This bit is set and cleared by software. |
|
| Bits 10:9 | Reserved, must be kept at reset value. |
| Bit 8 | ADCRST: ADC interface reset (common to all ADCs) |
|
This bit is set and cleared by software. |
|
| Bit 7 | SDMMC2RST: SDMMC2 module reset |
|
This bit is set and cleared by software. |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bit 5 | USART6RST: USART6 reset |
|
This bit is set and cleared by software. |
|
| Bit 4 | USART1RST: USART1 reset This bit is set and cleared by software. 0: does not reset USART1 1: resets USART1 |
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | TIM8RST: TIM8 reset |
|
This bit is set and cleared by software. |
|
| Bit 0 | TIM1RST: TIM1 reset |
|
This bit is set and cleared by software. |
Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | OTGHS ULPIEN |
OTGHS EN |
ETHM ACPTP EN |
ETHM ACRX EN |
ETHM ACTX EN |
ETHMA CEN |
Res. | DMA2D EN |
DMA2 EN |
DMA1 EN |
DTCMRA MEN |
Res. | BKPSR AMEN |
Res. | Res. |
Res. | Res. | Res. | CRC EN |
Res. | GPIOK EN |
GPIOJ EN |
GPIOI EN |
GPIOH EN |
GPIOG EN |
GPIOF EN |
GPIOE EN |
GPIOD EN |
GPIOC EN |
GPIO BEN |
GPIO AEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | OTGHSULPIEN: USB OTG HSULPI clock enable |
|
This bit is set and cleared by software. |
|
| Bit 29 | OTGHSEN: USB OTG HS clock enable |
|
This bit is set and cleared by software. |
|
| Bit 28 | ETHMACPTPEN: Ethernet PTP clock enable |
|
This bit is set and cleared by software. |
|
| Bit 27 | ETHMACRXEN: Ethernet Reception clock enable |
|
This bit is set and cleared by software. |
|
| Bit 26 | ETHMACTXEN: Ethernet Transmission clock enable |
|
This bit is set and cleared by software. |
|
| Bit 25 | ETHMACEN: Ethernet MAC clock enable |
|
This bit is set and cleared by software. |
|
| Bit 24 | Reserved, must be kept at reset value. |
| Bit 23 | DMA2DEN: DMA2D clock enable |
|
This bit is set and cleared by software. |
|
| Bit 22 | DMA2EN: DMA2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 21 | DMA1EN: DMA1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 20 | DTCMRAMEN: DTCM data RAM clock enable |
|
This bit is set and cleared by software. 0: DTCM RAM clock disabled |
|
| Bit 19 | Reserved, must be kept at reset value. |
| Bit 18 | BKPSRAMEN: Backup SRAM interface clock enable |
|
This bit is set and cleared by software. |
|
| Bits 17:13 | Reserved, must be kept at reset value. |
| Bit 12 | CRCEN: CRC clock enable |
|
This bit is set and cleared by software. |
|
| Bit 11 | Reserved, must be kept at reset value. |
| Bit 10 | GPIOKEN: IO port K clock enable |
|
This bit is set and cleared by software. |
|
| Bit 9 | GPIOJEN: IO port J clock enable |
|
This bit is set and cleared by software. |
|
| Bit 8 | GPIOIEN: IO port I clock enable |
|
This bit is set and cleared by software. |
|
| Bit 7 | GPIOHEN: IO port H clock enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | GPIOGEN: IO port G clock enable |
|
This bit is set and cleared by software. |
|
| Bit 5 | GPIOFEN: IO port F clock enable |
|
This bit is set and cleared by software. |
|
| Bit 4 | GPIOEEN: IO port E clock enable |
|
This bit is set and cleared by software. |
|
| Bit 3 | GPIODEN: IO port D clock enable |
|
This bit is set and cleared by software. 0: IO port D clock disabled |
|
| Bit 2 | GPIOCEN: IO port C clock enable |
|
This bit is set and cleared by software. |
|
| Bit 1 | GPIOBEN: IO port B clock enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | GPIOAEN: IO port A clock enable |
|
This bit is set and cleared by software. |
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFS EN |
RNG EN |
HASH EN |
CRYP EN |
Res. | Res. | JPEG EN |
DCMI EN |
| rw | rw | rw | rw | rw | rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | OTGFSEN: USB OTG FS clock enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | RNGEN: Random number generator clock enable |
|
This bit is set and cleared by software. |
|
| Bit 5 | HASHEN: Hash modules clock enable |
|
This bit is set and cleared by software. |
|
| Bit 4 | CRYPEN: Cryptographic modules clock enable |
|
This bit is set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | JPEGEN: JPEG module clock enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | DCMIEN: Camera interface enable |
|
This bit is set and cleared by software. |
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPIEN | FMCEN |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | QSPIEN: Quad SPI memory controller clock enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | FMCEN: Flexible memory controller clock enable |
|
This bit is set and cleared by software. |
Address offset: 0x40
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UART8 EN |
UART7 EN |
DAC EN |
PWR EN |
CEC EN |
CAN2 EN |
CAN1 EN |
I2C4 EN |
I2C3 EN |
I2C2 EN |
I2C1 EN |
UART5 EN |
UART4 EN |
USART 3 EN |
USART 2 EN |
SPDIFRX EN |
SPI3 EN |
SPI2 EN |
CAN3 EN |
Res. | WWDG EN |
RTCAPB EN |
LPTIM1 EN |
TIM14 EN |
TIM13 EN |
TIM12 EN |
TIM7 EN |
TIM6 EN |
TIM5 EN |
TIM4 EN |
TIM3 EN |
TIM2 EN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | UART8EN: UART8 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 30 | UART7EN: UART7 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 29 | DACEN: DAC interface clock enable |
|
This bit is set and cleared by software. |
|
| Bit 28 | PWREN: Power interface clock enable |
|
This bit is set and cleared by software. |
|
| Bit 27 | CECEN: HDMI-CEC clock enable |
|
This bit is set and cleared by software. |
|
| Bit 26 | CAN2EN: CAN 2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 25 | CAN1EN: CAN 1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 24 | I2C4: I2C4 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 23 | I2C3EN: I2C3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 22 | I2C2EN: I2C2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 21 | I2C1EN: I2C1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 20 | UART5EN: UART5 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 19 | UART4EN: UART4 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 18 | USART3EN: USART3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 17 | USART2EN: USART2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 16 | SPDIFRXEN: SPDIFRX clock enable |
|
This bit is set and cleared by software. |
|
| Bit 15 | SPI3EN: SPI3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 14 | SPI2EN: SPI2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 13 | CAN3EN: CAN 3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bit 11 | WWDGEN: Window watchdog clock enable |
|
This bit is set and cleared by software. |
|
| Bit 10 | RTCAPBEN: RTC register interface clock enable |
|
This bit is set and cleared by software. |
|
| Bit 9 | LPTMI1EN: Low-power timer 1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 8 | TIM14EN: TIM14 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 7 | TIM13EN: TIM13 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | TIM12EN: TIM12 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 5 | TIM7EN: TIM7 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 4 | TIM6EN: TIM6 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 3 | TIM5EN: TIM5 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 2 | TIM4EN: TIM4 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 1 | TIM3EN: TIM3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | TIM2EN: TIM2 clock enable |
|
This bit is set and cleared by software. |
Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | MDIO EN |
DFSDM1 EN |
Res. | DSI EN |
LTDC EN |
Res. | Res. | SAI2EN | SAI1EN | SPI6EN | SPI5EN | Res. | TIM11 EN |
TIM10 EN |
TIM9 EN |
Res. | SYSCFG EN |
SPI4 EN |
SPI1 EN |
SDMMC1 EN |
ADC3 EN |
ADC2 EN |
ADC1 EN |
SDMMC2 EN |
Res. | USART6 EN |
USART1 EN |
Res. | Res. | TIM8 EN |
TIM1 EN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | MDIOEN: MDIO clock enable |
|
This bit is set and reset by software. |
|
| Bit 29 | DFSDM1EN: DFSDM1 module reset |
|
This bit is set and reset by software. |
|
| Bit 28 | Reserved, must be kept at reset value. |
| Bit 27 | DSIEN: DSIHOST clock enable |
|
This bit is set and reset by software. |
|
| Bit 26 | LTDCEN: LTDC clock enable |
|
This bit is set and cleared by software. |
|
| Bit 25 | 24 Reserved, must be kept at reset value. |
| Bit 23 | SAI2EN: SAI2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 22 | SAI1EN: SAI1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 21 | SPI6EN: SPI6 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 20 | SPI5EN: SPI5 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 18 | TIM11EN: TIM11 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 17 | TIM10EN: TIM10 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 16 | TIM9EN: TIM9 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | SYSCFGEN: System configuration controller clock enable |
|
This bit is set and cleared by software. |
|
| Bit 13 | SPI4EN: SPI4 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 12 | SPI1EN: SPI1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 11 | SDMMC1EN: SDMMC1 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 10 | ADC3EN: ADC3 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 9 | ADC2EN: ADC2 clock enable This bit is set and cleared by software. 0: ADC2 clock disabled 1: ADC2 clock enabled |
| Bit 8 | ADC1EN: ADC1 clock enable This bit is set and cleared by software. 0: ADC1 clock disabled 1: ADC1 clock enabled |
| Bit 7 | SDMMC2EN: SDMMC2 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bit 5 | USART6EN: USART6 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 4 | USART1EN: USART1 clock enable |
|
This bit is set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | TIM8EN: TIM8 clock enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | TIM1EN: TIM1 clock enable |
|
This bit is set and cleared by software. |
Address offset: 0x50
Reset value: 0x7EF7 B7FFh
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. |
OTGHS ULPI LPEN |
OTGHS LPEN |
ETHPTP LPEN |
ETHRX LPEN |
ETHTX LPEN |
ETHMA C LPEN |
Res. | DMA2D LPEN |
DMA2 LPEN |
DMA1 LPEN |
DTCM LPEN |
Res. |
BKPS RAM LPEN |
SRAM2 LPEN |
SRAM1 LPEN |
FLITF LPEN |
Res. | AXI LPEN |
CRC LPEN |
Res. | GPIOK LPEN |
GPIOIJ LPEN |
GPIOI LPEN |
GPIOH LPEN |
GPIOGG LPEN |
GPIOF LPEN |
GPIOE LPEN |
GPIOD LPEN |
GPIOC LPEN |
GPIOB LPEN |
GPIOA LPEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 29 | OTGHSLPEN: USB OTG HS clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 28 | ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 27 | ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 26 | ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 25 | ETHMACLPEN: Ethernet MAC clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 24 | Reserved, must be kept at reset value. |
| Bit 23 | DMA2DLPEN: DMA2D clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 22 | DMA2LPEN: DMA2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 21 | DMA1LPEN: DMA1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 20 | DTCMLPEN: DTCM RAM interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 19 | Reserved, must be kept at reset value. |
| Bit 18 | BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 17 | SRAM2LPEN: SRAM2 interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 16 | SRAM1LPEN: SRAM1 interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 15 | FLITFLPEN: Flash interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 14 | Reserved, must be kept at reset value. |
| Bit 13 | AXILPEN: AXI to AHB bridge clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 12 | CRCLPEN: CRC clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 11 | Reserved, must be kept at reset value. |
| Bit 10 | GPIOKLPEN: IO port K clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 9 | GPIOJLPEN: IO port J clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 8 | GPIOILPEN: IO port I clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 7 | GPIOHLPEN: IO port H clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 6 | GPIOGLPEN: IO port G clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 5 | GPIOFLPEN: IO port F clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 4 | GPIOELPEN: IO port E clock enable during Sleep mode |
|
Set and cleared by software. |
|
| Bit 3 | GPIODLPEN: IO port D clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 2 | GPIOCLPEN: IO port C clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 1 | GPIOBLPEN: IO port B clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 0 | GPIOALPEN: IO port A clock enable during sleep mode |
|
This bit is set and cleared by software. |
Address offset: 0x54
Reset value: 0x0000 00F3
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFS LPEN |
RNG LPEN |
HASH LPEN |
CRYP LPEN |
Res. | Res. | JPEG LPEN |
DCMI LPEN |
| rw | rw | rw | rw | rw | rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | OTGFSLPEN: USB OTG FS clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 6 | RNGLPEN: Random number generator clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 5 | HASHLPEN: Hash modules clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 4 | CRYPLPEN: Cryptography modules clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | JPEGLPEN: JPEG module enabled during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 0 | DCMILPEN: Camera interface enable during Sleep mode |
|
This bit is set and cleared by software. |
Address offset: 0x58
Reset value: 0x0000 0003
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPI LPEN |
FMC LPEN |
| rw | rw |
Bits 31:2Reserved, must be kept at reset value.
| Bit 1 | QSPILPEN: QUADSPI memory controller clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 0 | FMCLPEN: Flexible memory controller module clock enable during Sleep mode |
|
This bit is set and cleared by software. |
Address offset: 0x60
Reset value: 0xFFFF EFFFh
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UART8 LPEN |
UART7 LPEN |
DAC LPEN |
PWR LPEN |
CEC LPEN |
CAN2 LPEN |
CAN1 LPEN |
I2C4 LPEN |
I2C3 LPEN |
I2C2 LPEN |
I2C1 LPEN |
UART5 LPEN |
UART4 LPEN |
USART3 LPEN |
USART2 LPEN |
SPDIFRX LPEN |
SPI3 LPEN |
SPI2 LPEN |
CAN3 LPEN |
Res. | WWDG LPEN |
RTCAPB LPEN |
LPTMI1 LPEN |
TIM14 LPEN |
TIM13 LPEN |
TIM12 LPEN |
TIM7 LPEN |
TIM6 LPEN |
TIM5 LPEN |
TIM4 LPEN |
TIM3 LPEN |
TIM2 LPEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | UART8LPEN: UART8 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 30 | UART7LPEN: UART7 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 29 | DACLPEN: DAC interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 28 | PWRLPEN: Power interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 27 | CECLPEN: HDMI-CEC clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 26 | CAN2LPEN: CAN 2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 25 | CAN1LPEN: CAN 1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 24 | I2C4LPEN: I2C4 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 23 | I2C3LPEN: I2C3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 22 | I2C2LPEN: I2C2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 21 | I2C1LPEN: I2C1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 20 | UART5LPEN: UART5 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 19 | UART4LPEN: UART4 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 18 | USART3LPEN: USART3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 17 | USART2LPEN: USART2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 16 | SPDIFRXLPEN: SPDIFRX clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 15 | SPI3LPEN: SPI3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 14 | SPI2LPEN: SPI2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 13 | CAN3LPEN: CAN 3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bit 11 | WWDGLPEN: Window watchdog clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 10 | RTCAPBLPEN: RTC register interface clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 9 | LPTIM1LPEN: low-power timer 1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 8 | TIM14LPEN: TIM14 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 7 | TIM13LPEN: TIM13 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 6 | TIM12LPEN: TIM12 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 5 | TIM7LPEN: TIM7 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 4 | TIM6LPEN: TIM6 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 3 | TIM5LPEN: TIM5 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 2 | TIM4LPEN: TIM4 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 1 | TIM3LPEN: TIM3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 0 | TIM2LPEN: TIM2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
Address offset: 0x64
Reset value: 0x06F7 7FB3h
Access: no wait state, word, half-word and byte access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | MDIO LPEN |
DFSDM1 LPEN |
Res. | DSI LPEN |
LTDC LPEN |
Res. | Res. | SAI2 LPEN |
SAI1 LPEN |
SPI6 LPEN |
SPI5 LPEN |
Res. | TIM11 LPEN |
TIM10 LPEN |
TIM9 LPEN |
Res. | SYSCFG LPEN |
SPI4 LPEN |
SPI1 LPEN |
SDMMC1 LPEN |
ADC3 LPEN |
ADC2 LPEN |
ADC1 LPEN |
SDMMC2 LPEN |
Res. | USART6 LPEN |
USART1 LPEN |
Res. | Res. | TIM8 LPEN |
TIM1 LPEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | MDIOLPEN: MDIO clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 29 | DFSDM1LPEN: DFSDM1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 28 | Reserved, must be kept at reset value. |
| Bit 27 | DSILPEN: DSIHOST clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 26 | LTDCLPEN: LTDC clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bits 25:24 | Reserved, must be kept at reset value. |
| Bit 23 | SAI2LPEN: SAI2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 22 | SAI1LPEN: SAI1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 21 | SPI6LPEN: SPI6 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 20 | SPI5LPEN: SPI5 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 19 | Reserved, must be kept at reset value. |
| Bit 18 | TIM11LPEN: TIM11 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 17 | TIM10LPEN: TIM10 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 16 | TIM9LPEN: TIM9 clock enable during sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | SYSCFGLPEN: System configuration controller clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 13 | SPI4LPEN: SPI4 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 12 | SPI1LPEN: SPI1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 11 | SDMMC1LPEN: SDMMC1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 10 | ADC3LPEN: ADC 3 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 9 | ADC2LPEN: ADC2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 8 | ADC1LPEN: ADC1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 7 | SDMMC2LPEN: SDMMC2 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bit 5 | USART6LPEN: USART6 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 4 | USART1LPEN: USART1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | TIM8LPEN: TIM8 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
|
| Bit 0 | TIM1LPEN: TIM1 clock enable during Sleep mode |
|
This bit is set and cleared by software. |
Address offset: 0x70
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, LSEDRV[1:0], RTCSEL and RTCEN bits in the RCC backup domain
control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-protected and the DBP bit in the PWR power control register (PWR_CR1) has to be set before these can be modified. Refer to Section 5.1.1: System reset on page 151 for further information. These bits are only reset after a Backup domain Reset (see Section 5.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BDRST |
RTCEN | Res. | Res. | Res. | Res. | Res. | RTCSEL[1:0] | Res. | Res. | Res. | LSEDRV[1:0] | LSEBYP | LSERDY | LSEON |
||
| rw |
rw | rw | rw | rw | rw | rw | r | rw | |||||||||||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | BDRST: Backup domain software reset |
|
This bit is set and cleared by software. The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is |
|
| Bit 15 | RTCEN: RTC clock enable |
|
This bit is set and cleared by software. |
|
| Bits 14:10 | Reserved, must be kept at reset value. |
| Bits 9:8 | RTCSEL[1:0]: RTC clock source selection |
|
These bits are set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:3 | LSEDRV[1:0]: LSE oscillator drive capability |
|
Set by software to modulate the LSE oscillator’s drive capability. |
|
| Bit 2 | LSEBYP: External low-speed oscillator bypass |
|
This bit is set and cleared by software to bypass the oscillator. This bit can be written only when the LSE clock is disabled. |
|
| Bit 1 | LSERDY: External low-speed oscillator ready |
|
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. |
|
| Bit 0 | LSEON: External low-speed oscillator enable |
|
This bit is set and cleared by software. |
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LPWR RSTF |
WWDG RSTF |
IWDG RSTF |
SFT RSTF |
POR RSTF |
PIN RSTF |
BOR RSTF | RMVF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSIRDY | LSION |
| r | r | r | r | r | r | r | rw |
r | rw |
| Bit 31 | LPWRRSTF: Low-power reset flag |
|
This bit is set by hardware when a Low-power management reset occurs. |
|
| Bit 30 | WWDGRSTF: Window watchdog reset flag |
|
This bit is set by hardware when a window watchdog reset occurs. |
|
| Bit 29 | IWDGRSTF: Independent watchdog reset flag |
|
This bit is set by hardware when an independent watchdog reset from VDD domain occurs. |
|
| Bit 28 | SFTRSTF: Software reset flag |
|
This bit is set by hardware when a software reset occurs. |
|
| Bit 27 | PORRSTF: POR/PDR reset flag |
|
This bit is set by hardware when a POR/PDR reset occurs. |
|
| Bit 26 | PINRSTF: PIN reset flag |
|
This bit is set by hardware when a reset from the NRST pin occurs. |
|
| Bit 25 | BORRSTF: BOR reset flag |
|
Cleared by software by writing the RMVF bit. |
|
| Bit 24 | RMVF: Remove reset flag |
|
This bit is set by software to clear the reset flags. |
|
| Bits 23:2 | Reserved, must be kept at reset value. |
| Bit 1 | LSIRDY: Internal low-speed oscillator ready |
|
This bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles. |
|
| Bit 0 | LSION: Internal low-speed oscillator enable |
|
This bit is set and cleared by software. |
Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Note: For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the “Electrical characteristics” section in your device datasheet.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SSCG EN |
SPR EAD SEL |
Res. | Res. | INCSTEP[14:0] |
INCSTEP | MODPER[12:0] |
|||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||
| Bit 31 | SSCGEN: Spread spectrum modulation enable |
|
This bit is set and cleared by software. |
|
| Bit 30 | SPREADSEL: Spread Select |
|
This bit is set and cleared by software. |
|
| Bits 29:28 | Reserved, must be kept at reset value. |
| Bits 27:13 | INCSTEP[14:0]: Incrementation step |
|
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit. |
|
| Bits 12:0 | MODPER[12:0]: Modulation period |
|
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit. |
Address offset: 0x84
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)
f(PLLI2S_P) = f(VCO clock) / PLLI2SP
f(PLLI2S_Q) = f(VCO clock) / PLLI2SQ
f(PLLI2S_R) = f(VCO clock) / PLLI2SR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | PLLI2SR[2:0] | PLLI2SQ[0:3] | Res. | Res. | Res. | Res. | Res. | Res. | PLLI2SP[1:0] |
Res. | PLLI2SN[8:0] | Res. | Res. | Res. | Res. | Res. | Res. |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:28 | PLLI2SR[2:0]: PLLI2S division factor for I2S clocks |
|
These bits are set and cleared by software to control the I2S clock frequency. These bits should be written only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0% error with audio crystals. For more information about I2S clock frequency and precision, refer to Section 35.7.4: Start-up description in the I2S chapter. The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly. 000: PLLR = 0, wrong configuration |
|
| Bits 27:24 | PLLI2SQ[3:0]: PLLI2S division factor for SAIs clock |
|
These bits are set and cleared by software to control the SAIs clock frequency. |
|
| Bits 23:18 | Reserved, must be kept at reset value. |
| Bits 17:16 | PLLI2SP[1:0]: PLLI2S division factor for SPDIFRX clock |
|
These bits are set and cleared by software to control the SPDIFRX clock. These |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:6 | PLLI2SN[8:0]: PLLI2S multiplication factor for VCO |
|
These bits are set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits. The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz. 000000000: PLLI2SN = 0, wrong configuration Between 50 and 99, multiplication factors are possible for VCO input frequency higher |
|
| Bits 5:0 | Reserved, must be kept at reset value. |
Address offset: 0x88
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLSAI clock outputs according to the formulas:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | PLLSAIR[2:0] | PLLSAIQ[4:0] | Res. | Res. | Res. | Res. | Res. | Res. | PLLSAIP[1:0] |
Res. | PLLSAIN[8:0] | Res. | Res. | Res. | Res. | Res. | Res. |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:28 | PLLSAIR[2:0]: PLLSAI division factor for LCD clock |
|
Set and reset by software to control the LCD clock frequency. |
|
| Bits 27:24 | PLLSAIQ[3:0]: PLLSAI division factor for SAI clock |
|
Set and reset by software to control the frequency of SAI clock. |
|
| Bits 23:18 | Reserved, must be kept at reset value. |
| Bits 17:16 | PLLSAIP[1:0]: PLLSAI division factor for 48MHz clock |
|
Set and reset by software to control the frequency of the PLLSAI output clock (PLLSAI48CLK). This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits should be written only if the PLLSAI is disabled. PLLSAI48 output clock frequency = VCO frequency / PLLSAIP with PLLSAI P = 2, 4, 6, or 8 |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:6 | PLLSAIN[8:0]: PLLSAI division factor for VCO |
|
Set and reset by software to control the multiplication factor of the VCO. The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz. 000000000: PLLSAIN = 0, wrong configuration Between 50 and 99, multiplication factors are possible for VCO input frequency higher |
|
| Bits 5:0 | Reserved, must be kept at reset value |
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to configure the timer clock prescalers and the PLLSAI and PLLI2S output clock dividers for SAIs and LTDC peripherals according to the following formula:
f(PLLSAIDIVQ clock output) = f(PLLSAI_Q) / PLLSAIDIVQ
f(PLLSAIDIVR clock output) = f(PLLSAI_R) / PLLSAIDIVR
f(PLLI2SDIVQ clock output) = f(PLLI2S_Q) / PLLI2SDIVQ
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | ADFSDM 1SEL |
DFSDM 1SEL |
TIMPRE | SAI2SEL[1:0] | SAI1SEL[1:0] | Res. | Res. | PLLSAIDIVR[1:0] |
Res. | Res. | Res. | PLLSAIDIVQ[4:0] | Res. | Res. | Res. | PLLI2SDIVQ[4:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | ADFSDM1SEL: DFSDM1 AUDIO clock source selection: |
|
These bits are set and cleared by software to control the clock source for DFSDM1 Audio clock between SAI1 clock and SAI2 clock. |
|
| Bit 25 | DFSDM1SEL: DFSDM1 clock source selection: |
|
These bits are set and cleared by software to control the DFSDM1 Kernel clock source: |
|
| Bit 24 | TIMPRE: Timers clocks prescalers selection |
|
This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domain. |
|
| Bits 23:22 | SAI2SEL[1:0]: SAI2 clock source selection: |
|
These bits are set and cleared by software to control the SAI2 clock frequency. |
|
| Bits 21:20 | SAI1SEL[1:0]: SAI1 clock source selection |
|
These bits are set and cleared by software to control the SAI1 clock frequency. |
|
| Bit 19 | 18 Reserved, must be kept at reset value. |
| Bits 17:16 | PLLSAIDIVR[1:0]: division factor for LCD_CLK |
|
These bits are set and cleared by software to control the frequency of LCD_CLK. |
|
| Bit 15 | 13 Reserved, must be kept at reset value. |
| Bits 12:8 | PLLSAIDIVQ[4:0]: PLLSAI division factor for SAI1 clock |
|
These bits are set and reset by software to control the SAI1 clock frequency. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:0 | PLLI2SDIV[4:0]: PLLI2S division factor for SAI1 clock |
|
These bits are set and reset by software to control the SAI1 clock frequency. |
Address: 0x90h
Reset value: 0x0000 0000h
Access: no wait state, word, half-word and byte access
This register allows to select the source clock for the 48MHz, SDMMC, HDMI-CEC, LPTIM1, UARTs, USARTs and I2Cs clocks.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | DSI SEL |
SDMMC2 SEL |
SDMMC1 SEL |
CK48M SEL |
CECSE L |
LPTIM1SEL | I2C4SEL | I2C3SEL | I2C2SEL | I2C1SEL |
UART8SEL | UART7SEL | USART6SEL | UART5SEL | UART4SEL | UART3SEL | UART2SEL | UART1SEL |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | DSISEL: DSI clock source selection |
|
Set and reset by software. This bit allows to select the DSI byte lane clock source between |
|
| Bit 29 | SDMMC2SEL: SDMMC2 clock source selection |
|
Set and reset by software. |
|
| Bit 28 | SDMMC1SEL: SDMMC1 clock source selection |
|
Set and reset by software. |
|
| Bit 27 | CK48MSEL: 48MHz clock source selection |
|
Set and reset by software. |
|
| Bit 26 | CECSEL: HDMI-CEC clock source selection |
|
Set and reset by software. |
|
| Bits 25:24 | LPTIM1SEL: Low-power timer 1 clock source selection |
|
Set and reset by software. |
|
| Bits 23:22 | I2C4SEL: I2C4 clock source selection |
|
Set and reset by software. |
|
| Bits 21:20 | I2C3SEL: I2C3 clock source selection |
|
Set and reset by software. |
|
| Bits 19:18 | I2C2SEL: I2C2 clock source selection |
|
Set and reset by software. |
|
| Bits 17:16 | I2C1SEL: I2C1 clock source selection |
|
Set and reset by software. |
|
| Bits 15:14 | UART8SEL[1:0]: UART 8 clock source selection |
|
Set and reset by software. |
|
| Bits 13:12 | UART7SEL[1:0]: UART 7 clock source selection |
|
Set and reset by software. |
|
| Bits 11:10 | USART6SEL[1:0]: USART 6 clock source selection |
|
Set and reset by software. |
|
| Bits 9:8 | UART5SEL[1:0]: UART 5 clock source selection |
|
Set and reset by software. |
|
| Bits 7:6 | UART4SEL[1:0]: UART 4 clock source selection |
|
Set and reset by software. |
|
| Bits 5:4 | USART3SEL[1:0]: USART 3 clock source selection |
|
Set and reset by software. |
|
| Bits 3:2 | USART2SEL[1:0]: USART 2 clock source selection |
|
Set and reset by software. |
|
| Bits 1:0 | USART1SEL[1:0]: USART 1 clock source selection |
|
Set and reset by software. |
Table 23 gives the register map and reset values.
| Addr. offset |
Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | RCC_CR |
Res. | Res. | PLL SAIRDY | PLL SAION | PLL I2SRDY | PLL I2SON | PLL RDY | PLL ON | Res. | Res. | Res. | Res. | CSSON | HSEBYP | HSERDY | HSEON | HSICAL 7 | HSICAL 6 | HSICAL 5 | HSICAL 4 | HSICAL 3 | HSICAL 2 | HSICAL 1 | HSICAL 0 | HSITRIM 4 | HSITRIM 3 | HSITRIM 2 | HSITRIM 1 | HSITRIM 0 | Reserved | HSIRDY | HSION |
| 0x04 | RCC_PLLCFG R |
Res. | PLLR 2 | PLLR 1 | PLLR 0 | PLLQ 3 | PLLQ 2 | PLLQ 1 | PLLQ 0 | Res. | PLLSRC | Res. | Res. | Res. | Res. | PLLP 1 | PLLP 0 | Res. | PLLN 8 | PLLN 7 | PLLN 6 | PLLN 5 | PLLN 4 | PLLN 3 | PLLN 2 | PLLN 1 | PLLN 0 | PLLM 5 | PLLM 4 | PLLM 3 | PLLM 2 | PLLM 1 | PLLM 0 |
| 0x08 | RCC_CFGR |
MCO2 1 | MCO2 0 | MCO2PRE2 | MCO2PRE1 | MCO2PRE0 | MCO1PRE2 | MCO1PRE1 | MCO1PRE0 | I2SSRC | MCO1 1 | MCO1 0 | RTCPRE 4 | RTCPRE 3 | RTCPRE 2 | RTCPRE 1 | RTCPRE 0 | PPRE2 2 | PPRE2 1 | PPRE2 0 | PPRE1 2 | PPRE1 1 | PPRE1 0 | Res. | Res. | HPRE 3 | HPRE 2 | HPRE 1 | HPRE 0 | SWS 1 | SWS 0 | SW 1 | SW 0 |
| 0x0C | RCC_CIR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CSSC | PLLSAIRDYC | PLLI2SRDYC | PLLRDYC | HSERDYC | HSIRDYC | LSERDYC | LSIRDYC | Res. | PLLSAIRDYIE | PLLI2SRDYIE | PLLRDYIE | HSERDYIE | HSIRDYIE | LSERDYIE | LSIRDYIE | CSSF | PLLSAIRDYF | PLLI2SRDYF | PLLRDYF | HSERDYF | HSIRDYF | LSERDYF | LSIRDYF |
| 0x10 | RCC_AHB1RS TR |
Res. | Res. | OTGHSRST | Res. | Res. | Res. | ETHMACRST | Res. | DMA2DRST | DMA2RST | DMA1RST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCRST | Res. | GPIOKRST | GPIOJRST | GPIOIRST | GPIOHRST | GPIOGRST | GPIOFRST | GPIOERST | GPIODRST | GPIOCRST | GPIOBRST | GPIOARST |
| 0x14 | RCC_AHB2RS TR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFSRS | RNGRST | HASHRST | CRYPRST | Res. | Res. | JPEGRST | DCMIRST |
| 0x18 | RCC_AHB3RS TR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPIRST | FMCRST |
| 0x1C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x20 | RCC_APB1RS TR |
UART8RST | UART7RST | DACRST | PWRRST | CECRST | CAN2RST | CAN1RST | I2C4RST | I2C3RST | I2C2RST | I2C1RST | UART5RST | UART4RST | UART3RST | UART2RST | SPDIFRXRST | SPI3RST | SPI2RST | CAN3RST | Res. | WWDGRST | Res. | LPTIM1RST | TIM14RST | TIM13RST | TIM12RST | TIM7RST | TIM6RST | TIM5RST | TIM4RST | TIM3RST | TIM2RST |
| 0x24 | RCC_APB2RS TR |
Res. | MDIORST | DFSDM1RST | Res. | DSIRST | LTDCRST | Res. | Res. | SAI2RST | SAI1RST | SPI6RST | SPI5RST | Res. | TIM11RST | TIM10RST | TIM9RST | Res. | SYSCFGRST | SP45RST | SPI1RST | SDMMC1RST | Res. | Res. | ADCRST | SDMMC2RST | Res. | USART6RST | USART1RST | Res. | Res. | TIM8RST | TIM1RST |
| 0x28 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x2C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x30 | RCC_ AHB1ENR |
Res. | OTGHSULPIEN | OTGHSEN | ETHMACPTPEN | ETHMACRXEN | ETHMACTXEN | ETHMACEN | Res. | DMA2DEN | DMA2EN | DMA1EN | DTCMRAMEN | Reserved | BKPSRAMEN | Res. | Res. | Res. | Res. | Res. | CRCEN | Res. | GPIOKEN | GPIOJEN | GPIOIEN | GPIOHEN | GPIOGEN | GPIOFEN | GPIOEEN | GPIODEN | GPIOCEN | GPIOBEN | GPIOAEN |
| 0x34 | RCC_ AHB2ENR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFSEN | RNGEN | HASHEN | CRYPEN | Res. | Res. | JPEGEN | DCMIEN |
| 0x38 | RCC_ AHB3ENR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPIEN | FMCEN |
| 0x3C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x40 | RCC_ APB1ENR |
SPI8EN | SPI7EN | DACEN | PWREN | CECEN | CAN2EN | CAN1EN | I2C4EN | I2C3EN | I2C2EN | I2C1EN | UART5EN | UART4EN | USART3EN | USART2EN | SPDIFRXEN | SPI3EN | SPI2EN | CAN3EN | Res. | WWDGEN | Res. | LPTIM1EN | TIM14EN | TIM13EN | TIM12EN | TIM7EN | TIM6EN | TIM5EN | TIM4EN | TIM3EN | TIM2EN |
| 0x44 | RCC_ APB2ENR |
Res. | MDIOEN | DFSDM1EN | Res. | DSIEN | LTDCEN | Res. | Res. | SAI2EN | SAI1EN | SPI6EN | SPI5EN | Res. | TIM11EN | TIM10EN | TIM9EN | Res. | SYSCFGEN | SPI4EN | SPI1EN | SDMMC1EN | ADC3EN | ADC2EN | ADC1EN | SDMMC2EN | Res. | USART6EN | USART1EN | Res. | Res. | TIM8EN | TIM1EN |
| 0x48 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x4C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x50 | RCC_AHB1LP ENR |
Res. | OTGHSULPILPEN | OTGHSLPEN | ETHMACPTPLPEN | ETHMACRXLPEN | ETHMACTXLPEN | ETHMACLPEN | Res. | DMA2DLPEN | DMA2LPEN | DMA1LPEN | DTCMLPEN | Res. | BKPSRAMLPEN | SRAM2LPEN | SRAM1LPEN | FLITFLPEN | Res. | AXILPEN | CRCLPEN | Res. | GPIOKLPEN | GPIOJLPEN | GPIOILPEN | GPIOHLPEN | GPIOGLPEN | GPIOFLPEN | GPIOELPEN | GPIODLPEN | GPIOCLPEN | GPIOBLPEN | GPIOALPEN |
| 0x54 | RCC_AHB2LP ENR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OTGFSLPEN | RNGLPEN | HASHLPEN | CRYPLPEN | Res. | Res. | JPEGLPEN | DCMILPEN |
| 0x58 | RCC_AHB3LP ENR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | QSPILPEN | FMCLPEN |
| 0x5C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x60 | RCC_APB1LP ENR |
UART8LPEN | UART7LPEN | DACLPEN | PWRLPEN | CECLPEN | CAN2LPEN | CAN1LPEN | I2C4LPEN | I2C3LPEN | I2C2LPEN | I2C1LPEN | UART5LPEN | UART4LPEN | USART3LPEN | USART2LPEN | SPDIFRXLPEN | SPI3LPEN | SPI2LPEN | CAN3LPEN | Res. | WWDGLPEN | Res. | LPTIM1LPEN | TIM14LPEN | TIM13LPEN | TIM12LPEN | TIM7LPEN | TIM6LPEN | TIM5LPEN | TIM4LPEN | TIM3LPEN | TIM2LPEN |
| 0x64 | RCC_APB2LP ENR |
Res. | MDIOLPEN | DFSDM1LPEN | Res. | DSILPEN | LTDCLPEN | Res. | Res. | SAI2LPEN | SAI1LPEN | SPI6LPEN | SPI5LPEN | Res. | TIM11LPEN | TIM10LPEN | TIM9LPEN | Res. | SYSCFGLPEN | SPI4LPEN | SPI1LPEN | SDMMC1LPEN | ADC3LPEN | ADC2LPEN | ADC1LPEN | SDMMC2LPEN | Res. | USART6LPEN | USART1LPEN | Res. | Res. | TIM8LPEN | TIM1LPEN |
| 0x68 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x6C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x70 | RCC_BDCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BDRST | RTCEN | Res. | Res. | Res. | Res. | Res. | RTCSEL 1 | RTCSEL 0 | Res. | Res. | Res. | LSEDRV[1:0] | LSEBYP | LSERDY | LSEON | |
| 0x74 | RCC_CSR |
LPWRRSTF | WWDGRSTF | WDGRSTF | SFTRSTF | PORRSTF | PINRSTF | BORRSTF | RMVF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSIRDY | LSION |
| 0x78 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x7C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x80 | RCC_SSCGR |
SSCGEN | SPREADSEL | Res. | Res. | INCSTEP | MODPER |
||||||||||||||||||||||||||
| 0x84 | RCC_PLLI2SC FGR |
Res. | PLLI2SR[2: 0] |
PLLI2SQ[3:0] |
Res. | Res. | Res. | Res. | Res. | Res. | PLLI2SP[1:0] | Res. | PLLI2SN[8:0] |
Res. | Res. | Res. | Res. | Res. | Res. | ||||||||||||||
| 0x88 | RCC_PLLSAI CFGR |
Res. | PLLSAIR[2:0] | PLLSAIQ[4:0] | Res. | Res. | Res. | Res. | Res. | Res. | PLLSAIP[1:0] | Res. | PLLSAIN[8:0] | Res. | Res. | Res. | Res. | Res. | Res. | ||||||||||||||
| 0x8C | RCC_DCKCF GR1 |
Res. | Res. | Res. | Res. | Res. | ADFSDM1SEL | DFSDM1SEL | TIMPRE | SAI2SEL[1:0] | SAI1SEL[1:0] | Res. | Res. | PLLSAIDIVR[1:0] | Res. | Res. | Res. | PLLSAIDIVQ[4:0] |
Res. | Res. | Res. | PLLI2SDIVQ[4:0] |
|||||||||||
| 0x90 | RCC_DCKCF GR2 |
Res. | DSISEL | SDMMC2SEL | SDMMC1SEL | CK48MSEL | CECSEL | LPTIM1SEL | I2C4SEL | I2C3SEL | I2C2SEL | I2C1SEL | UART8SEL | UART7SEL | UART6SEL | UART5SEL | UART4SEL | UART3SEL | UART2SEL | UART1SEL | |||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Figure 17 and Figure 18 shows the basic structures of a standard and a 5-Volt tolerant I/O port bit, respectively. Table 24 gives the possible port bit configurations.
| (omitted) |
| (omitted) |
| MODE(i) [1:0] |
OTYPER(i) | OSPEED(i) [1:0] |
PUPD(i) [1:0] |
I/O configuration |
|||
|---|---|---|---|---|---|---|---|
| 01 |
0 |
SPEED [1:0] |
0 | 0 | GP output | PP |
|
| 0 | 0 | 1 | GP output | PP + PU |
|||
| 0 | 1 | 0 | GP output | PP + PD |
|||
| 0 | 1 | 1 | Reserved | ||||
| 1 | 0 | 0 | GP output | OD | |||
| 1 | 0 | 1 | GP output | OD + PU |
|||
| 1 | 1 | 0 | GP output | OD + PD |
|||
| 1 | 1 | 1 | Reserved (GP output OD) |
||||
| 10 |
0 |
SPEED [1:0] |
0 | 0 | AF | PP |
|
| 0 | 0 | 1 | AF | PP + PU |
|||
| 0 | 1 | 0 | AF | PP + PD |
|||
| 0 | 1 | 1 | Reserved |
||||
| 1 | 0 | 0 | AF | OD |
|||
| 1 | 0 | 1 | AF | OD + PU |
|||
| 1 | 1 | 0 | AF | OD + PD |
|||
| 1 | 1 | 1 | Reserved |
||||
| 00 |
x | x | x | 0 | 0 | Input | Floating |
| x | x | x | 0 | 1 | Input | PU |
|
| x | x | x | 1 | 0 | Input | PD |
|
| x | x | x | 1 | 1 | Reserved (input floating) |
||
| 11 |
x | x | x | 0 | 0 | Input/output | Analog |
| x | x | x | 0 | 1 |
Reserved |
||
| x | x | x | 1 | 0 | |||
| x | x | x | 1 | 1 | |||
During and just after reset, the alternate functions are not active and most of the I/O ports are configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.
The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins.
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register.
See Section 6.4.5: GPIO port input data register (GPIOx_IDR) (x = A..K) and Section 6.4.6:
GPIO port output data register (GPIOx_ODR) (x = A..K) for the register descriptions.
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.
It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 6.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A..K)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
For more details refer to LCKR register description in Section 6.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A..K).
Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.
All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. Refer to Section 11: Extended interrupts and events controller
(EXTI) and to Section 11.3: Wakeup event management.
When the I/O port is programmed as input:
Figure 19 shows the input configuration of the I/O port bit.
| (omitted) |
When the I/O port is programmed as output:
Figure 20 shows the output configuration of the I/O port bit.
| (omitted) |
When the I/O port is programmed as alternate function:
Figure 21 shows the Alternate function configuration of the I/O port bit.
| (omitted) |
When the I/O port is programmed as analog configuration:
Figure 22 shows the high-impedance, analog-input configuration of the I/O port bits.
| (omitted) |
When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.
The PC13/PC14/PC15/PI8 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 25.
The peripheral registers can be written in word, half word or byte mode.
Address offset:0x00
Reset values:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MODER15[1:0] | MODER14[1:0] | MODER13[1:0] | MODER12[1:0] | MODER11[1:0] | MODER10[1:0] | MODER9[1:0] | MODER8[1:0] |
MODER7[1:0] | MODER6[1:0] | MODER5[1:0] | MODER4[1:0] | MODER3[1:0] | MODER2[1:0] | MODER1[1:0] | MODER0[1:0] |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O mode.
00: Input mode (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OT15 | OT14 | OT13 | OT12 | OT11 | OT10 | OT9 | OT8 | OT7 | OT6 | OT5 | OT4 | OT3 | OT2 | OT1 | OT0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | OTy: Port x configuration bits (y = 0..15) |
|
These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) |
Address offset: 0x08
Reset value:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OSPEEDR15 [1:0] |
OSPEEDR14 [1:0] |
OSPEEDR13 [1:0] |
OSPEEDR12 [1:0] |
OSPEEDR11 [1:0] |
OSPEEDR10 [1:0] |
OSPEEDR9 [1:0] |
OSPEEDR8 [1:0] |
OSPEEDR7 [1:0] |
OSPEEDR6 [1:0] |
OSPEEDR5 [1:0] |
OSPEEDR4 [1:0] |
OSPEEDR3 [1:0] |
OSPEEDR2 [1:0] |
OSPEEDR1 [1:0] |
OSPEEDR0 [1:0] |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD range
and external load.
Address offset: 0x0C
Reset values:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PUPDR15[1:0] | PUPDR14[1:0] | PUPDR13[1:0] | PUPDR12[1:0] | PUPDR11[1:0] | PUPDR10[1:0] | PUPDR9[1:0] | PUPDR8[1:0] |
PUPDR7[1:0] | PUPDR6[1:0] | PUPDR5[1:0] | PUPDR4[1:0] | PUPDR3[1:0] | PUPDR2[1:0] | PUPDR1[1:0] | PUPDR0[1:0] |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
Address offset: 0x10
Reset value: 0x0000 XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
IDR15 | IDR14 | IDR13 | IDR12 | IDR11 | IDR10 | IDR9 | IDR8 | IDR7 | IDR6 | IDR5 | IDR4 | IDR3 | IDR2 | IDR1 | IDR0 |
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | IDRy: Port input data bit (y = 0..15) |
|
These bits are read-only. They contain the input value of the corresponding I/O port. |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
ODR15 | ODR14 | ODR13 | ODR12 | ODR11 | ODR10 | ODR9 | ODR8 | ODR7 | ODR6 | ODR5 | ODR4 | ODR3 | ODR2 | ODR1 | ODR0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | ODRy: Port output data bit (y = 0..15) |
|
These bits can be read and written by software. For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to |
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BR15 | BR14 | BR13 | BR12 | BR11 | BR10 | BR9 | BR8 | BR7 | BR6 | BR5 | BR4 | BR3 | BR2 | BR1 | BR0 |
BS15 | BS14 | BS13 | BS12 | BS11 | BS10 | BS9 | BS8 | BS7 | BS6 | BS5 | BS4 | BS3 | BS2 | BS1 | BS0 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:16 | BRy: Port x reset bit y (y = 0..15) |
|
These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit
If both BSx and BRx are set, BSx has priority.
|
|
| Bits 15:0 | BSy: Port x set bit y (y= 0..15) |
|
These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit |
This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LCKK |
LCK15 | LCK14 | LCK13 | LCK12 | LCK11 | LCK10 | LCK9 | LCK8 | LCK7 | LCK6 | LCK5 | LCK4 | LCK3 | LCK2 | LCK1 | LCK0 |
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | LCKK: Lock key |
|
This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active
During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will |
|
| Bits 15:0 | LCKy: Port x lock bit y (y= 0..15) |
|
These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked |
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AFR7[3:0] | AFR6[3:0] | AFR5[3:0] | AFR4[3:0] |
AFR3[3:0] | AFR2[3:0] | AFR1[3:0] | AFR0[3:0] |
||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | AFRy[3:0]: Alternate function selection for port x pin y (y = 0..7) |
|
These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AFR15[3:0] | AFR14[3:0] | AFR13[3:0] | AFR12[3:0] |
AFR11[3:0] | AFR10[3:0] | AFR9[3:0] | AFR8[3:0] |
||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | AFRy[3:0]: Alternate function selection for port x pin y (y = 8..15) |
|
These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 |
The following table gives the GPIO register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
GPIOA_MODER
|
MODER15[1:0] | MODER14[1:0] | MODER13[1:0] | MODER12[1:0] | MODER11[1:0] | MODER10[1:0] | MODER9[1:0] | MODER8[1:0] | MODER7[1:0] | MODER6[1:0] | MODER5[1:0] | MODER4[1:0] | MODER3[1:0] | MODER2[1:0] | MODER1[1:0] | MODER0[1:0] | ||||||||||||||||
| Reset value | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00 |
GPIOB_MODER
|
MODER15[1:0] | MODER14[1:0] | MODER13[1:0] | MODER12[1:0] | MODER11[1:0] | MODER10[1:0] | MODER9[1:0] | MODER8[1:0] | MODER7[1:0] | MODER6[1:0] | MODER5[1:0] | MODER4[1:0] | MODER3[1:0] | MODER2[1:0] | MODER1[1:0] | MODER0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00 |
GPIOx_MODER (where x = C..K) |
MODER15[1:0] | MODER14[1:0] | MODER13[1:0] | MODER12[1:0] | MODER11[1:0] | MODER10[1:0] | MODER9[1:0] | MODER8[1:0] | MODER7[1:0] | MODER6[1:0] | MODER5[1:0] | MODER4[1:0] | MODER3[1:0] | MODER2[1:0] | MODER1[1:0] | MODER0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x04 |
GPIOx_OTYPER (where x = A..K) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OT15 | OT14 | OT13 | OT12 | OT11 | OT10 | OT9 | OT8 | OT7 | OT6 | OT5 | OT4 | OT3 | OT2 | OT1 | OT0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x08 |
GPIOA_OSPEEDR
|
OSPEEDR15[1:0] | OSPEEDR14[1:0] | OSPEEDR13[1:0] | OSPEEDR12[1:0] | OSPEEDR11[1:0] | OSPEEDR10[1:0] | OSPEEDR9[1:0] | OSPEEDR8[1:0] | OSPEEDR7[1:0] | OSPEEDR6[1:0] | OSPEEDR5[1:0] | OSPEEDR4[1:0] | OSPEEDR3[1:0] | OSPEEDR2[1:0] | OSPEEDR1[1:0] | OSPEEDR0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x08 |
GPIOB_OSPEEDR
|
OSPEEDR15[1:0] | OSPEEDR14[1:0] | OSPEEDR13[1:0] | OSPEEDR12[1:0] | OSPEEDR11[1:0] | OSPEEDR10[1:0] | OSPEEDR9[1:0] | OSPEEDR8[1:0] | OSPEEDR7[1:0] | OSPEEDR6[1:0] | OSPEEDR5[1:0] | OSPEEDR4[1:0] | OSPEEDR3[1:0] | OSPEEDR2[1:0] | OSPEEDR1[1:0] | OSPEEDR0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x08 |
GPIOx_OSPEEDR (where x = C..K) |
OSPEEDR15[1:0] | OSPEEDR14[1:0] | OSPEEDR13[1:0] | OSPEEDR12[1:0] | OSPEEDR11[1:0] | OSPEEDR10[1:0] | OSPEEDR9[1:0] | OSPEEDR8[1:0] | OSPEEDR7[1:0] | OSPEEDR6[1:0] | OSPEEDR5[1:0] | OSPEEDR4[1:0] | OSPEEDR3[1:0] | OSPEEDR2[1:0] | OSPEEDR1[1:0] | OSPEEDR0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C |
GPIOA_PUPDR
|
PUPDR15[1:0] | PUPDR14[1:0] | PUPDR13[1:0] | PUPDR12[1:0] | PUPDR11[1:0] | PUPDR10[1:0] | PUPDR9[1:0] | PUPDR8[1:0] | PUPDR7[1:0] | PUPDR6[1:0] | PUPDR5[1:0] | PUPDR4[1:0] | PUPDR3[1:0] | PUPDR2[1:0] | PUPDR1[1:0] | PUPDR0[1:0] | ||||||||||||||||
| Reset value | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x0C |
GPIOB_PUPDR
|
PUPDR15[1:0] | PUPDR14[1:0] | PUPDR13[1:0] | PUPDR12[1:0] | PUPDR11[1:0] | PUPDR10[1:0] | PUPDR9[1:0] | PUPDR8[1:0] | PUPDR7[1:0] | PUPDR6[1:0] | PUPDR5[1:0] | PUPDR4[1:0] | PUPDR3[1:0] | PUPDR2[1:0] | PUPDR1[1:0] | PUPDR0[1:0] | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 |
GPIOx_IDR (where x = A..I/J/K) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IDR15 | IDR14 | IDR13 | IDR12 | IDR11 | IDR10 | IDR9 | IDR8 | IDR7 | IDR6 | IDR5 | IDR4 | IDR3 | IDR2 | IDR1 | IDR0 |
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|||||||||||||||||
| 0x14 |
GPIOx_ODR (where x = A..K) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ODR15 | ODR14 | ODR13 | ODR12 | ODR11 | ODR10 | ODR9 | ODR8 | ODR7 | ODR6 | ODR5 | ODR4 | ODR3 | ODR2 | ODR1 | ODR0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x18 |
GPIOx_BSRR (where x = A..I/J/K) |
BR15 | BR14 | BR13 | BR12 | BR11 | BR10 | BR9 | BR8 | BR7 | BR6 | BR5 | BR4 | BR3 | BR2 | BR1 | BR0 | BS15 | BS14 | BS13 | BS12 | BS11 | BS10 | BS9 | BS8 | BS7 | BS6 | BS5 | BS4 | BS3 | BS2 | BS1 | BS0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1C |
GPIOx_LCKR (where x = A..K) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LCKK | LCK15 | LCK14 | LCK13 | LCK12 | LCK11 | LCK10 | LCK9 | LCK8 | LCK7 | LCK6 | LCK5 | LCK4 | LCK3 | LCK2 | LCK1 | LCK0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x20 |
GPIOx_AFRL (where x = A..K) |
AFR7[3:0] | AFR6[3:0] | AFR5[3:0] | AFR4[3:0] | AFR3[3:0] | AFR2[3:0] | AFR1[3:0] | AFR0[3:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x24 |
GPIOx_AFRH (where x = A..J) |
AFR15[3:0] | AFR14[3:0] | AFR13[3:0] | AFR12[3:0] | AFR11[3:0] | AFR10[3:0] | AFR9[3:0] | AFR8[3:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2 for the register boundary addresses.
The system configuration controller is mainly used to:
By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply.
When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.
This register is used for specific configurations on memory mapping:
Address offset: 0x00
Reset value: 0x0000 0000
)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | SWP_FMC[1:0] | Res. | SWP_FB | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MEM_ BOOT |
|
| rw | rw | rw | r | ||||||||||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:10 | SWP_FMC[1:0]: FMC memory mapping swap |
|
Set and cleared by software. These bits are used to swap the FMC SDRAM banks and FMC NOR/PSRAM in order to enable the code execution from SDRAM Banks without modifying the default MPU attribute |
|
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | SWP_FB: Flash Bank swap |
|
Set and Clear by software. This bit controls the Flash Bank 1 & Flash Bank 2 mapping. It is not recommended to write the SWP_FB bit while executing from Flash |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | MEM_BOOT: Memory boot mapping |
|
This bit indicates which option bytes BOOT_ADD0 or BOOT_ADD1 defines the boot memory base address. 0: Boot memory base address is defined by BOOT_ADD0 option byte Refer to section 2.3: Memory map for details about the boot memory base |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 17 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MII_RMII _SEL |
Res. | Res. | Res. | Res. | ADCxDC2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PB9_ FMP |
PB8_ FMP |
PB7_ FMP |
PB6_ FMP |
I2C4_ FMP |
I2C3_ FMP |
I2C2_ FMP |
I2C1_ FMP |
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bit 23 | MII_RMII_SEL: Ethernet PHY interface selection |
|
Set and Cleared by software.These bits control the PHY interface for the Ethernet MAC. This configuration must be done while the MAC is under reset and before |
|
| Bits 22:19 | Reserved, must be kept at reset value. |
| Bits 18:16 | ADCxDC2: |
|
0: No effect.
These bits can be set only if the following conditions are met:
- ADC clock higher or equal to 30 MHz.
- Only one ADCxDC2 bit must be selected if ADC conversions do not start
at the same time and the sampling times differ.
- These bits must not be set when the ADCDC1 bit is set in PWR_CR
register.
|
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bit 7 | PB9_FMP: Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 6 | PB8_FMP: PB8_FMP Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 5 | PB7_FMP: PB7_FMP Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 4 | PB6_FMP: PB6_FMP Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 3 | I2C4_FMP: I2C4_FMP I2C4 Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 2 | I2C3_FMP: I2C3_FMP I2C3 Fast Mode + Enable |
|
Set and cleared by software. |
|
| Bit 1 | I2C2_FMP: I2C2_FMP I2C2 Fast Mode + Enable |
|
Set and cleared by software. 0: Default value. 1: It forces FM+ drive capability on I2C2 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits |
|
| Bit 0 | I2C1_FMP: I2C1_FMP I2C1 Fast Mode + Enable |
|
Set and cleared by software. 0: Default value. 1: It forces FM+ drive capability on I2C1 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXTI3[3:0] | EXTI2[3:0] | EXTI1[3:0] | EXTI0[3:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | EXTIx[3:0]: EXTI x configuration (x = 0 to 3) |
|
These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin |
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXTI7[3:0] | EXTI6[3:0] | EXTI5[3:0] | EXTI4[3:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | EXTIx[3:0]: EXTI x configuration (x = 4 to 7) |
|
These bits are written by software to select the source input for the EXTIx external interrupt. |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXTI11[3:0] | EXTI10[3:0] | EXTI9[3:0] | EXTI8[3:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | EXTIx[3:0]: EXTI x configuration (x = 8 to 11) |
|
These bits are written by software to select the source input for the EXTIx external interrupt.
PK[11:8] are not used
|
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXTI15[3:0] | EXTI14[3:0] | EXTI13[3:0] | EXTI12[3:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | EXTIx[3:0]: EXTI x configuration (x = 12 to 15) |
|
These bits are written by software to select the source input for the EXTIx external interrupt. PK[15:12] are not used |
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PVDL | Res. | CLL |
| rs | rs |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | PVDL: PVD Lock |
|
Set by software, cleared by system reset only. |
|
| Bit 1 | Reserved, must be kept at reset value. |
| Bit 0 | CLL: Core Lockup Lock |
|
Set by software, cleared by system reset only. |
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | READY | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CMP_PD |
| r | rw |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | READY: Compensation cell ready flag |
|
0: I/O compensation cell not ready |
|
| Bits 7:2 | Reserved, must be kept at reset value. |
| Bit 0 | CMP_PD: Compensation cell power-down |
|
0: I/O compensation cell power-down mode |
The following table gives the SYSCFG register map and the reset values.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
SYSCFG_ MEMRMP |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWP_FMC[1:0] | Res. | SWP_FB | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MEM_BOOT | |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x04 | SYSCFG_PMC |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MII_RMII_SEL | Res. | Res. | Res. | Res. | ADC3DC2 | ADC2DC2 | ADC1DC2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PB9_FMP | PB8_FMP | PB7_FMP | PB6_FMP | I2C4_FB | I2C3_FB | I2C2_FB | I2C1_FB |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x08 |
SYSCFG_EXTICR1 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI3[3:0] | EXTI2[3:0] | EXTI1[3:0] | EXTI0[3:0] |
||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0C |
SYSCFG_EXTICR2 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI7[3:0] | EXTI6[3:0] | EXTI5[3:0] | EXTI4[3:0] |
||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x10 |
SYSCFG_EXTICR3 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI11[3:0] | EXTI10[3:0] | EXTI9[3:0] | EXTI8[3:0] |
||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x14 |
SYSCFG_EXTICR4 Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EXTI15[3:0] | EXTI14[3:0] | EXTI13[3:0] | EXTI12[3:0] |
||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x1C |
SYSCFG_CBR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PVD | Res. | CLL |
| 0 | 0 |
||||||||||||||||||||||||||||||||
| 0x20 |
SYSCFG_CMPCR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | READY | Res. | Res. | Res. | Res. | Res. | Res. | CMP_PD |
| 0 | 0 | ||||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture.
The two DMA controllers (DMA1 and DMA2) have 16 streams in total (8 for each controller), each dedicated to managing memory access requests from one or more peripherals.
Each stream can have up to 16 channels (requests) in total.
Each DMA controller has an arbiter for handling the priority between DMA requests.
The main DMA features are:
Figure 23 shows the block diagram of a DMA.
| (omitted) |
The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.
It carries out the following transactions:
The DMA controller provides two AHB master ports: the AHB memory port, intended to be connected to memories and the AHB peripheral port, intended to be connected to peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit accesses).
Note: The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case
of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory
transfers.
See Figure 1 for the implementation of the system of two DMA controllers.
A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-programmable.
Each DMA transfer consists of three operations:
After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the DMA controller. The peripheral releases its request as soon as it gets the Acknowledge signal from the DMA controller. Once the request has been deasserted by the peripheral, the DMA controller releases the Acknowledge signal. If there are more requests, the peripheral can initiate the next transaction.
Each stream is associated with a DMA request that can be selected out of 16 possible channel requests. The selection is controlled by the CHSEL[3:0] bits in the DMA_SxCR register.
| (omitted) |
The 16 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently connected to each channel and their connection depends on the product implementation.
Table 27 and Table 28 give examples of DMA request mappings.
| Peripheral requests | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|---|---|---|---|---|---|---|---|---|
| Channel 0 | SPI3_RX | SPDIFRX_DT | SPI3_RX | SPI2_RX | SPI2_TX | SPI3_TX | SPDIFRX_CS | SPI3_TX |
| Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP | - | TIM7_UP | I2C1_RX | I2C1_TX | I2C1_TX |
| Channel 2 | TIM4_CH1 | - | I2C4 _RX | TIM4_CH2 | - | I2C4 _RX | TIM4_UP | TIM4_CH3 |
| Channel 3 | - | TIM2_UP TIM2_CH3 |
I2C3_RX | - | I2C3_TX | TIM2_CH1 | TIM2_CH2 TIM2_CH4 |
TIM2_UP TIM2_CH4 |
| Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX | UART4_TX | USART2_RX | USART2_TX | UART5_TX |
| Channel 5 | UART8_TX | UART7_TX | TIM3_CH4 TIM3_UP |
UART7_RX | TIM3_CH1 TIM3_TRIG |
TIM3_CH2 | UART8_RX | TIM3_CH3 |
| Channel 6 | TIM5_CH3 TIM5_UP |
TIM5_CH4 TIM5_TRIG |
TIM5_CH1 | TIM5_CH4 TIM5_TRIG |
TIM5_CH2 | - | TIM5_UP | - |
| Channel 7 | - | TIM6_UP | I2C2_RX | I2C2_RX | USART3_TX | DAC1 | DAC2 | I2C2_TX |
| Channel 8 | I2C3_TX | I2C4_RX | - | - | I2C2_TX | - | I2C4_TX | - |
| Channel 9 | - | SPI2_RX | - | - | - | - | SPI2_TX | - |
| Peripheral requests | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|---|---|---|---|---|---|---|---|---|
| Channel 0 | ADC1 | SAI1_A |
TIM8_CH1 TIM8_CH2 TIM8_CH3 |
SAI1_A | ADC1 | SAI1_B |
TIM1_CH1 TIM1_CH2 TIM1_CH3 |
SAI2_B |
| Channel 1 | - | DCMI | ADC2 | ADC2 | SAI1_B | SPI6_TX | SPI6_RX | DCMI |
| Channel 2 | ADC3 | ADC3 | - | SPI5_RX | SPI5_TX | CRYP_OUT | CRYP_IN | HASH_IN |
| Channel 3 | SPI1_RX | - | SPI1_RX | SPI1_TX | SAI2_A | SPI1_TX | SAI2_B | QUADSPI |
| Channel 4 | SPI4_RX | SPI4_TX | USART1_RX | SDMMC1 | - | USART1_RX | SDMMC1 | USART1_TX |
| Channel 5 | - | USART6_RX | USART6_RX | SPI4_RX | SPI4_TX | - | USART6_TX | USART6_TX |
| Channel 6 | TIM1_TRIG | TIM1_CH1 | TIM1_CH2 | TIM1_CH1 |
TIM1_CH4 TIM1_TRIG TIM1_COM |
TIM1_UP | TIM1_CH3 | - |
| Channel 7 | - | TIM8_UP | TIM8_CH1 | TIM8_CH2 | TIM8_CH3 | SPI5_RX | SPI5_TX |
TIM8_CH4 TIM8_TRIG TIM8_COM |
| Channel 8 | DFSDM1_ FLT0 |
DFSDM1_ FLT1 |
DFSDM1_ FLT2 |
DFSDM1_ FLT3 |
DFSDM1_ FLT0 |
DFSDM1_ FLT1 |
DFSDM1_ FLT2 |
DFSDM1_ FLT3 |
| Channel 9 | JPEG_IN | JPEG_OUT | SPI4_TX | JPEG_IN | JPEG_OUT | SPI5_RX | - | - |
| Channel 10 | SAI1_B | SAI2_B | SAI2_A | - | - | - | SAI1_A | - |
| Channel 11 | SDMMC2 | - | QUADSPI | - | - | SDMMC2 | - | - |
An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences.
Priorities are managed in two stages:
Each of the 8 DMA controller streams provides a unidirectional transfer link between a source and a destination.
Each stream can be configured to perform:
The amount of data to be transferred (up to 65535) is programmable and related to the source width of the peripheral that requests the DMA transfer connected to the peripheral AHB port. The register that contains the amount of data items to be transferred is decremented after each transaction.
Both source and destination transfers can address peripherals and memories in the entire 4 Gbytes area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers. Table 29 describes the corresponding source and destination addresses.
| Bits DIR[1:0] of the DMA_SxCR register | Direction | Source address | Destination address |
|---|---|---|---|
| 00 | Peripheral-to-memory | DMA_SxPAR | DMA_SxM0AR |
| 01 | Memory-to-peripheral | DMA_SxM0AR | DMA_SxPAR |
| 10 | Memory-to-memory | DMA_SxPAR | DMA_SxM0AR |
| 11 | Reserved | - | - |
When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.
Peripheral-to-memory mode
Figure 25 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register.
| (omitted) |
Memory-to-peripheral mode
Figure 26 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream immediately initiates transfers from the source to entirely fill the FIFO.
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA transfers the preloaded value into the configured destination. It then reloads again the empty internal FIFO with the next data to be transfer. The preloaded data size corresponds to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register.
| (omitted) |
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral. This is the memory-to-memory mode, described in Figure 27.
When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level. When the threshold level is reached, the FIFO contents are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the DMA_SxCR register is cleared by software.
The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register.
Note: When memory-to-memory mode is used, the circular and direct modes are not allowed.
Only the DMA2 controller is able to perform memory-to-memory transfers.
| (omitted) |
Peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR register.
Disabling the increment mode is useful when the peripheral source or destination data is accessed through a single register.
If the increment mode is enabled, the address of the next transfer is the address of the previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the AHB peripheral port. The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with the data size on the peripheral AHB port, or on a 32-bit address (the address is then incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If the PINCOS bit is set, the address of the following transfer is the address of the previous one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE value. The AHB memory port, however, is not impacted by this operation.
The circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register.
When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Note: In the circular mode, it is mandatory to respect the following rule in case of a burst mode
configured for memory:
DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:
For example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in
this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).
If this formula is not respected, the DMA behavior and data integrity are not guaranteed.
NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data
size, otherwise this could result in a bad DMA behavior.
This mode is available for all the DMA1 and DMA2 streams.
The double-buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.
A double-buffer stream works as a regular (single buffer) stream with the difference that it has two memory pointers. When the double-buffer mode is enabled, the circular mode is automatically enabled (CIRC bit in DMA_SxCR is not relevant) and at each end of transaction, the memory pointers are swapped.
In this mode, the DMA controller swaps from one memory target to another at each end of transaction. This allows the software to process one memory area while the second memory area is being filled/used by the DMA transfer. The double-buffer stream can work in both directions (the memory can be either the source or the destination) as described in Table 30: Source and destination address registers in double-buffer mode (DBM = 1).
Note: In double-buffer mode, it is possible to update the base address for the AHB memory port
on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the
following conditions:
To avoid any error condition, it is advised to change the base address as soon as the TCIF
flag is asserted because, at this point, the targeted memory must have changed from
memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in
accordance with one of the two above conditions.
For all the other modes (except the double-buffer mode), the memory address registers are
write-protected as soon as the stream is enabled.
| Bits DIR[1:0] of the DMA_SxCR register | Direction | Source address | Destination address |
|---|---|---|---|
| 00 | Peripheral-to-memory | DMA_SxPAR | DMA_SxM0AR / DMA_SxM1AR |
| 01 | Memory-to-peripheral | DMA_SxM0AR / DMA_SxM1AR | DMA_SxPAR |
| 10 | Not allowed(1) |
||
| 11 | Reserved | - | - |
The number of data items to be transferred has to be programmed into DMA_SxNDTR (number of data items to transfer bit, NDT) before enabling the stream (except when the flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).
When using the internal FIFO, the data widths of the source and destination data are programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-, 16- or 32-bit).
When PSIZE and MSIZE are not equal:
This packing/unpacking procedure may present a risk of data corruption when the operation is interrupted before the data are completely packed/unpacked. So, to ensure data coherence, the stream may be configured to generate burst transfers: in this case, each group of transfers belonging to a burst are indivisible (refer to Section 8.3.12: Single and
burst transfers).
In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is not possible. In this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR register. MSIZE bits are not relevant.
| AHB memory port width |
AHB peripheral port width |
Number of data items to transfer (NDT) |
- |
Memory transfer number |
Memory port address / byte lane |
Peripheral transfer number |
Peripheral port address / byte lane |
|
|---|---|---|---|---|---|---|---|---|
| - | PINCOS = 1 | PINCOS = 0 |
||||||
| 8 | 8 | 4 | - |
1 2 3 4 |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
1 2 3 4 |
0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
| 8 | 16 | 2 | - |
1 2 3 4 |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
1 2 |
0x0 / B1|B0[15:0] 0x4 / B3|B2[15:0] |
0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] |
| 8 | 32 | 1 | - |
1 2 3 4 |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
1 | 0x0 / B3|B2|B1|B0[31:0] |
0x0 / B3|B2|B1|B0[31:0] |
| 16 | 8 | 4 | - |
1 2 |
0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] |
1 2 3 4 |
0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
| 16 | 16 | 2 | - |
1 2 |
0x0 / B1|B0[15:0] 0x2 / B1|B0[15:0] |
1 2 |
0x0 / B1|B0[15:0] 0x4 / B3|B2[15:0] |
0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] |
| 16 | 32 | 1 | - |
1 2 |
0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] |
1 | 0x0 / B3|B2|B1|B0[31:0] |
0x0 / B3|B2|B1|B0[31:0] |
| 32 | 8 | 4 | - |
1 | 0x0 / B3|B2|B1|B0[31:0] | 1 2 3 4 |
0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] |
0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] |
| 32 | 16 | 2 | - |
1 | 0x0 /B3|B2|B1|B0[31:0] | 1 2 |
0x0 / B1|B0[15:0] 0x4 / B3|B2[15:0] |
0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] |
| 32 | 32 | 1 | - | 1 | 0x0 /B3|B2|B1|B0 [31:0] | 1 | 0x0 /B3|B2|B1|B0 [31:0] |
0x0 / B3|B2|B1|B0[31:0] |
Note: Peripheral port may be the source or the destination (it could also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer will not be incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is lower than the data width of the memory port (MSIZE bits). This constraint is summarized in Table 32.
| PSIZE[1:0] of DMA_SxCR | MSIZE[1:0] of DMA_SxCR | NDT[15:0] of DMA_SxNDTR |
|---|---|---|
| 00 (8-bit) | 01 (16-bit) | must be a multiple of 2 |
| 00 (8-bit) | 10 (32-bit) | must be a multiple of 4 |
| 01 (16-bit) | 10 (32-bit) | must be a multiple of 2 |
The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats.
The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
The burst size indicates the number of beats in the burst, not the number of bytes transferred.
To ensure data coherence, each group of transfers that form a burst are indivisible: AHB transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master during the sequence of the burst transfer.
Depending on the single or burst configuration, each DMA request initiates a different number of transfers on the AHB peripheral port:
The same as above has to be considered for the AHB memory port considering the MBURST and MSIZE bits.
In direct mode, the stream can only generate single transfers and the MBURST[1:0] and PBURST[1:0] bits are forced by hardware.
The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer.
The burst configuration has to be selected in order to respect the AHB protocol, where bursts must not cross the 1 Kbyte address boundary because the minimum address space that can be allocated to a single slave is 1 Kbyte. This means that the 1 Kbyte address boundary must not be crossed by a burst block transfer, otherwise an AHB error is generated, that is not reported by the DMA registers.
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them to the destination.
Each stream has an independent 4-word FIFO and the threshold level is software-configurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register.
The structure of the FIFO differs depending on the source and destination data widths, and is described in Figure 28: FIFO structure.
| (omitted) |
FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) is generated when the stream is enabled, then the stream is automatically disabled. The allowed and forbidden configurations are described in Table 33. The forbidden configurations are highlighted in gray in the table.
| MSIZE | FIFO level | MBURST = INCR4 | MBURST = INCR8 | MBURST = INCR16 |
|---|---|---|---|---|
| Byte |
1/4 | 1 burst of 4 beats | Forbidden |
Forbidden |
| 1/2 | 2 bursts of 4 beats | 1 burst of 8 beats | ||
| 3/4 | 3 bursts of 4 beats | Forbidden |
||
| Full | 4 bursts of 4 beats | 2 bursts of 8 beats | 1 burst of 16 beats | |
| Half-word |
1/4 | Forbidden |
Forbidden |
Forbidden |
| 1/2 | 1 burst of 4 beats |
|||
| 3/4 | Forbidden |
|||
| Full | 2 bursts of 4 beats | 1 burst of 8 beats |
||
| Word |
1/4 |
Forbidden |
Forbidden |
|
| 1/2 |
||||
| 3/4 |
||||
| Full | 1 burst of 4 beats |
In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete burst transfer at the end of a DMA transfer may happen if one of the following conditions occurs:
In such cases, the remaining data to be transferred is managed in single mode by the DMA, even if a burst transaction is requested during the DMA stream configuration.
Note: When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time is free to serve the request from the
peripheral.
FIFO flush
The FIFO can be flushed when the stream is disabled by resetting the EN bit in the DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers. If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination (even though stream is effectively disabled). When this flush is completed, the transfer complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.
The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how many data items are currently available in the destination memory.
Note that during the FIFO flush operation, if the number of remaining data items in the FIFO
to be transferred to memory (in bytes) is less than the memory data width (for example 2 bytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the MSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired
value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions are generated to complete the FIFO flush.
Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and the FIFO threshold level is not used. This mode is useful when the system requires an immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-to-peripheral mode, the DMA preloads one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with a high priority.
This mode is restricted to transfers where:
Direct mode must not be used when implementing memory-to-memory transfers.
Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR or DMA_HISR status register:
Note: The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in noncircular mode, after the end of the transfer (that is when the number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).
At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer.
There are two cases:
Note: A transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the
end of transfer due to the stream interruption.
The entity that controls the number of data to be transferred is known as the flow controller. This flow controller is configured independently for each stream using the PFCTRL bit in the DMA_SxCR register.
The flow controller can be:
When the peripheral flow controller is used for a given stream, the value written into the DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it will be forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following schemes:
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula:
Note: When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The circular mode is forbidden in the peripheral flow controller mode.
Table 34 summarizes the different possible DMA configurations. The forbidden configurations are highlighted in gray in the table.
| DMA transfer mode | Source | Destination | Flow controller |
Circular mode |
Transfer type |
Direct mode |
Double- buffer mode |
|---|---|---|---|---|---|---|---|
| Peripheral-to- memory |
AHB peripheral port |
AHB memory port |
DMA | Possible |
single | Possible |
Possible |
| burst | Forbidden |
||||||
| Peripheral | Forbidden |
single | Possible |
Forbidden |
|||
| burst | Forbidden |
||||||
| Memory-to- peripheral |
AHB memory port |
AHB peripheral port |
DMA | Possible |
single | Possible |
Possible |
| burst | Forbidden |
||||||
| Peripheral | Forbidden |
single | Possible |
Forbidden |
|||
| burst | Forbidden |
||||||
| Memory-to- memory |
AHB peripheral port |
AHB memory port |
DMA only | Forbidden |
single |
Forbidden | Forbidden |
| burst |
The following sequence must be followed to configure a DMA stream x (where x is the stream number):
As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream.
Once half the data have been transferred on the AHB destination port, the half-transfer flag (HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is generated if the transfer complete interrupt enable bit (TCIE) is set.
Warning: To switch off a peripheral connected to a DMA stream
request, it is mandatory to, first, switch off the DMA stream to
which the peripheral is connected, then to wait for EN bit = 0.
Only then can the peripheral be safely disabled.
The DMA controller can detect the following errors:
In direct mode, the FIFO error flag can also be set under the following conditions:
If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO threshold level, the faulty stream is automatically disabled through a hardware clear of its EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE, FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note: When a FIFO overrun or underrun condition occurs, the data is not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.
For each DMA stream, an interrupt can be produced on the following events:
Separate interrupt enable control bits are available for flexibility as shown in Table 35.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Half-transfer | HTIF | HTIE |
| Transfer complete | TCIF | TCIE |
| Transfer error | TEIF | TEIE |
| FIFO overrun/underrun | FEIF | FEIE |
| Direct mode error | DMEIF | DMEIE |
Note: Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.
The DMA registers have to be accessed by words (32 bits).
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | TCIF3 | HTIF3 | TEIF3 | DMEIF3 | Res. | FEIF3 | TCIF2 | HTIF2 | TEIF2 | DMEIF2 | Res. | FEIF2 |
Res. | Res. | Res. | Res. | TCIF1 | HTIF1 | TEIF1 | DMEIF1 | Res. | FEIF1 | TCIF0 | HTIF0 | TEIF0 | DMEIF0 | Res. | FEIF0 |
| r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r |
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIF[3:0]: stream x transfer complete interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register.
0: no transfer complete event on stream x
1: a transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIF[3:0]: stream x half transfer interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register.
0: no half transfer event on stream x
1: a half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIF[3:0]: stream x transfer error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register.
0: no transfer error on stream x
1: a transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIF[3:0]: stream x direct mode error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register.
0: No direct mode error on stream x
1: a direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIF[3:0]: stream x FIFO error interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register.
0: no FIFO error event on stream x
1: a FIFO error event occurred on stream x
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | TCIF7 | HTIF7 | TEIF7 | DMEIF7 | Res. | FEIF7 | TCIF6 | HTIF6 | TEIF6 | DMEIF6 | Res. | FEIF6 |
Res. | Res. | Res. | Res. | TCIF5 | HTIF5 | TEIF5 | DMEIF5 | Res. | FEIF5 | TCIF4 | HTIF4 | TEIF4 | DMEIF4 | Res. | FEIF4 |
| r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r |
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIF[7:4]: stream x transfer complete interrupt flag (x = 7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register.
0: no transfer complete event on stream x
1: atransfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIF[7:4]: stream x half transfer interrupt flag (x = 7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register.
0: no half transfer event on stream x
1: a half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIF[7:4]: stream x transfer error interrupt flag (x = 7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register.
0: no transfer error on stream x
1: a transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIF[7:4]: stream x direct mode error interrupt flag (x = 7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register.
0: no direct mode error on stream x
1: a direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIF[7:4]: stream x FIFO error interrupt flag (x = 7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register.
0: no FIFO error event on stream x
1: a FIFO error event occurred on stream x
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | CTCIF3 | CHTIF3 | CTEIF3 | CDMEIF3 | Res. | CFEIF3 | CTCIF2 | CHTIF2 | CTEIF2 | CDMEIF2 | Res. | CFEIF2 |
Res. | Res. | Res. | Res. | CTCIF1 | CHTIF1 | CTEIF1 | CDMEIF1 | Res. | CFEIF1 | CTCIF0 | CHTIF0 | CTEIF0 | CDMEIF0 | Res. | CFEIF0 |
| w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w |
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIF[3:0]: stream x clear transfer complete interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register.
Bits 26, 20, 10, 4 CHTIF[3:0]: stream x clear half transfer interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIF[3:0]: Stream x clear transfer error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register.
Bits 24, 18, 8, 2 CDMEIF[3:0]: stream x clear direct mode error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIF[3:0]: stream x clear FIFO error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register.
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | CTCIF7 | CHTIF7 | CTEIF7 | CDMEIF7 | Res. | CFEIF7 | CTCIF6 | CHTIF6 | CTEIF6 | CDMEIF6 | Res. | CFEIF6 |
Res. | Res. | Res. | Res. | CTCIF5 | CHTIF5 | CTEIF5 | CDMEIF5 | Res. | CFEIF5 | CTCIF4 | CHTIF4 | CTEIF4 | CDMEIF4 | Res. | CFEIF4 |
| w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w |
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIF[7:4]: stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register.
Bits 26, 20, 10, 4 CHTIF[7:4]: stream x clear half transfer interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register.
Bits 25, 19, 9, 3 CTEIF[7:4]: stream x clear transfer error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register.
Bits 24, 18, 8, 2 CDMEIF[7:4]: stream x clear direct mode error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIF[7:4]: stream x clear FIFO error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res. | CT | DBM | PL[1:0] |
PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN |
|||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bits 28:25 | CHSEL[3:0]: channel selection |
|
These bits are set and cleared by software. |
|
| Bits 24:23 | MBURST[1:0]: memory burst transfer configuration |
|
These bits are set and cleared by software. |
|
| Bits 22:21 | PBURST[1:0]: peripheral burst transfer configuration |
|
These bits are set and cleared by software. |
|
| Bit 20 | Reserved, must be kept at reset value. |
| Bit 19 | CT: current target (only in double-buffer mode) |
|
This bit is set and cleared by hardware. It can also be written by software. |
|
| Bit 18 | DBM: double-buffer mode |
|
This bit is set and cleared by software. |
|
| Bits 17:16 | PL[1:0]: priority level |
|
These bits are set and cleared by software. |
|
| Bit 15 | PINCOS: peripheral increment offset size |
|
This bit is set and cleared by software |
|
| Bits 14:13 | MSIZE[1:0]: memory data size |
|
These bits are set and cleared by software. |
|
| Bits 12:11 | PSIZE[1:0]: peripheral data size |
|
These bits are set and cleared by software. |
|
| Bit 10 | MINC: memory increment mode |
|
This bit is set and cleared by software. |
|
| Bit 9 | PINC: peripheral increment mode |
|
This bit is set and cleared by software. |
|
| Bit 8 | CIRC: circular mode |
|
This bit is set and cleared by software and can be cleared by hardware. |
|
| Bits 7:6 | DIR[1:0]: data transfer direction |
|
These bits are set and cleared by software. |
|
| Bit 5 | PFCTRL: peripheral flow controller |
|
This bit is set and cleared by software. |
|
| Bit 4 | TCIE: transfer complete interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 3 | HTIE: half transfer interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 2 | TEIE: transfer error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 1 | DMEIE: direct mode error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | EN: stream enable / flag stream ready when read low |
|
This bit is set and cleared by software.
registers. It is forbidden to write these registers when the EN bit is read as 1. Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the |
Address offset: 0x14 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
NDT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | NDT[15:0]: number of data items to transfer (0 up to 65535) |
|
This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer.
enabled. |
Address offset: 0x18 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PAR[31:16] |
PAR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | PAR[31:0]: peripheral address |
|
Base address of the peripheral data register from/to which the data is read/written. |
Address offset: 0x1C + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M0A[31:16] |
M0A[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | M0A[31:0]: memory 0 address |
|
Base address of memory area 0 from/to which the data is read/written.
|
Address offset: 0x20 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M1A[31:16] |
M1A[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | M1A[31:0]: memory 1 address (used in case of double-buffer mode) |
|
Base address of memory area 1 from/to which the data is read/written.
|
Address offset: 0x24 + 0x24 * x, (x = 0 to 7)
Reset value: 0x0000 0021
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FEIE | Res. | FS[2:0] | DMDIS | FTH[1:0] |
|||
| rw | r | r | r | rw | rw | rw |
|||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | FEIE: FIFO error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bits 5:3 | FS[2:0]: FIFO status |
|
These bits are read-only. |
|
| Bit 2 | DMDIS: direct mode disable |
|
This bit is set and cleared by software. It can be set by hardware. |
|
| Bits 1:0 | FTH[1:0]: FIFO threshold selection |
|
These bits are set and cleared by software. |
Table 36 summarizes the DMA registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 | DMA_LISR |
Res. | Res. | Res. | Res. | TCIF3 | HTIF3 | TEIF3 | DMEIF3 | Res. | FEIF3 | TCIF2 | HTIF2 | TEIF2 | DMEIF2 | Res. | FEIF2 | Res. | Res. | Res. | Res. | TCIF1 | HTIF1 | TEIF1 | DMEIF1 | Res. | FEIF1 | TCIF0 | HTIF0 | TEIF0 | DMEIF0 | Res. | FEIF0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x0004 | DMA_HISR |
Res | Res | Res | Res | TCIF7 | HTIF7 | TEIF7 | DMEIF7 | Res | FEIF7 | TCIF6 | HTIF6 | TEIF6 | DMEIF6 | Res | FEIF6 | Res | Res | Res | Res | TCIF5 | HTIF5 | TEIF5 | DMEIF5 | Res | FEIF5 | TCIF4 | HTIF4 | TEIF4 | DMEIF4 | Res | FEIF4 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x0008 | DMA_LIFCR |
Res | Res | Res | Res | CTCIF3 | CHTIF3 | TEIF3 | CDMEIF3 | Res | CFEIF3 | CTCIF2 | CHTIF2 | CTEIF2 | CDMEIF2 | Res | CFEIF2 | Res | Res | Res | Res | CTCIF1 | CHTIF1 | CTEIF1 | CDMEIF1 | Res | CFEIF1 | CTCIF0 | CHTIF0 | CTEIF0 | CDMEIF0 | Res | CFEIF0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x000C | DMA_HIFCR |
Res | Res | Res | Res | CTCIF7 | CHTIF7 | CTEIF7 | CDMEIF7 | Res | CFEIF7 | CTCIF6 | CHTIF6 | CTEIF6 | CDMEIF6 | Res | CFEIF6 | Res | Res | Res | Res | CTCIF5 | CHTIF5 | CTEIF5 | CDMEIF5 | Res | CFEIF5 | CTCIF4 | CHTIF4 | CTEIF4 | CDMEIF4 | Res | CFEIF4 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x0010 | DMA_S0CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x0014 | DMA_S0NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0018 | DMA_S0PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x001C | DMA_S0M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0020 | DMA_S0M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0024 | DMA_S0FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x0028 | DMA_S1CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x002C | DMA_S1NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0030 | DMA_S1PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x0034 | DMA_S1M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0038 | DMA_S1M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x003C | DMA_S1FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x0040 | DMA_S2CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | [D1I:R0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x0044 | DMA_S2NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0048 | DMA_S2PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x004C | DMA_S2M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0050 | DMA_S2M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0054 | DMA_S2FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x0058 | DMA_S3CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x005C | DMA_S3NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0060 | DMA_S3PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0064 | DMA_S3M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0068 | DMA_S3M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x006C | DMA_S3FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x0070 | DMA_S4CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | [D1I:R0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x0074 | DMA_S4NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0078 | DMA_S4PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x007C | DMA_S4M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0080 | DMA_S4M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0084 | DMA_S4FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x0088 | DMA_S5CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x008C | DMA_S5NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0090 | DMA_S5PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0094 | DMA_S5M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0098 | DMA_S5M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x009C | DMA_S5FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x00A0 | DMA_S6CR |
Res. | Res. | Res. | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res. | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x00A4 | DMA_S6NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x00A8 | DMA_S6PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00AC | DMA_S6M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00B0 | DMA_S6M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00B4 | DMA_S6FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
| 0x00B8 | DMA_S7CR |
Res | Res | Res | CHSEL[3:0] | MBURST[1:0] | PBURST[1:0] | Res | CT | DBM | PL[1:0] | PINCOS | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR[1:0] | PFCTRL | TCIE | HTIE | TEIE | DMEIE | EN | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x00BC | DMA_S7NDTR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | NDT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x00C0 | DMA_S7PAR | PA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00C4 | DMA_S7M0AR | M0A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00C8 | DMA_S7M1AR | M1A[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00CC | DMA_S7FCR |
Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | Res | FEIE | Res | FS[2:0] |
DMDIS | FTH[1:0] | |||
| Reset value | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The Chrom-ART Accelerator™ (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations:
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color look-up tables).
The main DMA2D features are:
The DMA2D controller performs direct memory transfer. As an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in Figure 29: DMA2D block diagram.
| (omitted) |
The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) which allows selecting:
The user application can perform the following operations:
The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel format converter (PFC).
They are programmed through a set of control registers:
When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.
When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor blending operation), only the FG FIFO is activated and acts as a buffer.
When the DMA2D operates in memory-to-memory operation with pixel format conversion (no blending operation), the BG FIFO is not activated.
DMA2D foreground pixel format converter (PFC) and background pixel format converter perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also modify the alpha channel.
The first stage of the converter converts the color format. The original color format of the foreground pixel and background pixels are configured through the CM[3:0] bits of the DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.
The supported input formats are given in Table 37: Supported color mode in input.
| CM[3:0] | Color mode |
|---|---|
| 0000 | ARGB8888 |
| 0001 | RGB888 |
| 0010 | RGB565 |
| 0011 | ARGB1555 |
| 0100 | ARGB4444 |
| 0101 | L8 |
| 0110 | AL44 |
| 0111 | AL88 |
| 1000 | L4 |
| 1001 | A8 |
| 1010 | A4 |
The color format are coded as follows:
Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
L field: luminance
This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.
If the original format was direct color mode (ARGB/RGB), then the extension to 8-bit per channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of the conversion.
If the original format is indirect color mode (L/AL), a CLUT is required and each pixel format converter is associated with a 256 entry 32-bit CLUT.
If the original format does not include an alpha channel, the alpha value is automatically set to 0xFF (opaque).
For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for foreground pixels and in the DMA2D_BGCOLR register for background pixels.
The order of the fields in the system memory is defined in Table 38: Data order in memory.
| Color Mode | @ + 3 | @ + 2 | @ + 1 | @ + 0 |
|---|---|---|---|---|
| ARGB8888 | A0[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| RGB888 |
B1[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| G2[7:0] | B2[7:0] | R1[7:0] | G1[7:0] |
|
| R3[7:0] | G3[7:0] | B3[7:0] | R2[7:0] |
|
| RGB565 | R1[4:0]G1[5:3] | G1[2:0]B1[4:0] | R0[4:0]G0[5:3] | G0[2:0]B0[4:0] |
| ARGB1555 | A1[0]R1[4:0]G1[4:3] | G1[2:0]B1[4:0] | A0[0]R0[4:0]G0[4:3] | G0[2:0]B0[4:0] |
| ARGB4444 | A1[3:0]R1[3:0] | G1[3:0]B1[3:0] | A0[3:0]R0[3:0] | G0[3:0]B0[3:0] |
| L8 | L3[7:0] | L2[7:0] | L1[7:0] | L0[7:0] |
| AL44 | A3[3:0]L3[3:0] | A2[3:0]L2[3:0] | A1[3:0]L1[3:0] | A0[3:0]L0[3:0] |
| AL88 | A1[7:0] | L1[7:0] | A0[7:0] | L0[7:0] |
| L4 | L7[3:0]L6[3:0] | L5[3:0]L4[3:0] | L3[3:0]L2[3:0] | L1[3:0]L0[3:0] |
| A8 | A3[7:0] | A2[7:0] | A1[7:0] | A0[7:0] |
| A4 | A7[3:0]A6[3:0] | A5[3:0]A4[3:0] | A3[3:0]A2[3:0] | A1[3:0]A0[3:0] |
The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
Once the 32-bit value is generated, the alpha channel can be modified according to the AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in Table 39: Alpha mode configuration.
The alpha channel can be:
| AM[1:0] | Alpha mode |
|---|---|
| 00 | No modification |
| 01 | Replaced by value in DMA2D_xxPFCCR |
| 10 | Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255 |
| 11 | Reserved |
Note: To support the alternate format, the incoming alpha value can be inverted setting the AI bit
of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the Alpha
value stored in the DMA2D_FGPFCCR/DMA2D_BGPFCCR and in the CLUT.
The R and B fields can also be swapped setting the RBS bit of the
DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the RGB order used
in the CLUT and in the DMA2D_FGCOLR/DMA2D_BGCOLR registers.
The CLUT interface manages the CLUT memory access and the automatic loading of the CLUT.
Three kinds of accesses are possible:
The CLUT memory loading can be done in two different ways:
Automatic loading
The following sequence should be followed to load the CLUT:
occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in DMA2D_CR.
Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave port to which the local CLUT memory is mapped.The foreground CLUT is located at address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT) as shown in Table 40: Supported CLUT color mode.
| CCM | CLUT color mode |
|---|---|
| 0 | 32-bit ARGB8888 |
| 1 | 24-bit RGB888 |
The way the CLUT data are organized in the system memory is specified in Table 41: CLUT
data order in system memory.
| CLUT Color Mode | @ + 3 | @ + 2 | @ + 1 | @ + 0 |
| ARGB8888 | A0[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| RGB888 |
B1[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| G2[7:0] | B2[7:0] | R1[7:0] | G1[7:0] |
|
| R3[7:0] | G3[7:0] | B3[7:0] | R2[7:0] |
The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:
αFG . αBG
with αMult = 255
αOUT = αFG + αBG - αMult
CFG.αFG + CBG.αBG - CBG.αMult
COUT =
αwith C = R or G or B
OUT
Division is rounded to the nearest lower integer
No configuration register is required by the blender. The blender usage depends on the DMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register.
The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM[2:0] field of the DMA2D output pixel format converter configuration register (DMA2D_OPFCCR).
The supported output formats are given in Table 42: Supported color mode in output
| CM[2:0] | Color mode |
|---|---|
| 000 | ARGB8888 |
| 001 | RGB888 |
| 010 | RGB565 |
| 011 | ARGB1555 |
| 100 | ARGB4444 |
Note: To support the alternate format, the calculated alpha value can be inverted setting the AI bit
of the DMA2D_OPFCCR registers. This applies also to the Alpha value used in the
DMA2D_OCOLR.
The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR
registers. This applies also to the RGB order used in the DMA2D_OCOLR.
The output FIFO programs the pixels according to the color format defined in the output PFC.
The destination area is defined through a set of control registers:
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in Table 43: Data order in memory
| Color Mode | @ + 3 | @ + 2 | @ + 1 | @ + 0 |
|---|---|---|---|---|
| ARGB8888 | A0[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| RGB888 |
B1[7:0] | R0[7:0] | G0[7:0] | B0[7:0] |
| G2[7:0] | B2[7:0] | R1[7:0] | G1[7:0] |
|
| R3[7:0] | G3[7:0] | B3[7:0] | R2[7:0] |
|
| RGB565 | R1[4:0]G1[5:3] | G1[2:0]B1[4:0] | R0[4:0]G0[5:3] | G0[2:0]B0[4:0] |
| ARGB1555 | A1[0]R1[4:0]G1[4:3] | G1[2:0]B1[4:0] | A0[0]R0[4:0]G0[4:3] | G0[2:0]B0[4:0] |
| ARGB4444 | A1[3:0]R1[3:0] | G1[3:0]B1[3:0] | A0[3:0]R0[3:0] | G0[3:0]B0[3:0] |
The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive accesses. This limits the bandwidth usage.
The timer enabling and the dead time value are configured through the AHB master port timer configuration register (DMA2D_AMPTCR).
DMA2D transactions consist of a sequence of a given number of data transfers. The number of data and the width can be programmed by software.
Each DMA2D data transfer is composed of up to 4 steps:
Both source and destination data transfers can target peripherals and memories in the whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and 0xFFFF FFFF.
The DMA2D can operate in any of the four following modes selected through MODE[1:0] bits of the DMA2D_CR register:
Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
The color format is set in the DMA2D_OPFCCR.
The DMA2D does not perform any data fetching from any source. It just writes the color defined in the DMA2D_OCOLR register to the area located at the address pointed by the DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.
Memory-to-memory
In memory-to-memory mode, the DMA2D does not perform any graphical data transformation. The foreground input FIFO acts as a buffer and the data are transferred from the source memory location defined in DMA2D_FGMAR to the destination memory location pointed by DMA2D_OMAR.
The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines the number of bits per pixel for both input and output.
The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination.
Memory-to-memory with PFC
In this mode, the DMA2D performs a pixel format conversion of the source data and stores them in the destination memory location.
The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination.
Data are fetched from the location defined in the DMA2D_FGMAR register and processed by the foreground PFC. The original pixel format is configured through the DMA2D_FGPFCCR register.
If the original pixel format is direct color mode, then the color channels are all expanded to 8 bits.
If the pixel format is indirect color mode, the associated CLUT has to be loaded into the CLUT memory.
The CLUT loading can be done automatically by following the sequence below:
Once the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised, and an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT loading process can not work in parallel with classical DMA2D transfers.
The CLUT can also be filled by the CPU or by any other master through the APB port. The access to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT (indirect color format).
In parallel to the color conversion process, the alpha value can be added or changed depending on the value programmed in the DMA2D_FGPFCCR register. If the original image does not have an alpha channel, a default alpha value of 0xFF is automatically added
to obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits of the DMA2D_FGPFCCR register:
The resulting 32-bit data are encoded by the OUT PFC into the format specified by the CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the indirect mode since no CLUT generation process is supported.
The processed data are written into the destination memory location pointed by DMA2D_OMAR.
Memory-to-memory with PFC and blending
In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.
The two pixel format converters have to be configured as described in the memory-to-memory mode. Their configurations can be different as each pixel format converter are independent and have their own CLUT memory.
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended according to the equation below:
αFG . αBG
255
αOUT = αFG + αBG - αMult
CFG.αFG + CBG.αBG - CBG.αMult
OUT
Division are rounded to the nearest lower integer
The resulting 32-bit pixel value is encoded by the output PFC according to the specified output format, and the data are written into the destination memory location pointed by DMA2D_OMAR.
Configuration error detection
The DMA2D checks that the configuration is correct before any transfer. The configuration error interrupt flag is set by hardware when a wrong configuration is detected when a new transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the DMA2D_CR is set.
The wrong configurations that can be detected are listed below:
Once the DMA2D is configured, the transfer can be launched by setting the START bit of the DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the TCIE bit of the DMA2D_CR is set.
The user application can suspend the DMA2D at any time by setting the SUSP bit of the DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR register.
The user application can abort at any time an ongoing transaction by setting the ABORT bit of the DMA2D_CR register. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the SUSP bit of the DMA2D_CR register.
A watermark can be programmed to generate an interrupt when the last pixel of a given line has been written to the destination memory area.
The line number is defined in the LW[15:0] field of the DMA2D_LWR register.
When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.
Two kind of errors can be triggered:
Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to generate an interrupt if need be (TEIE and CAEIE).
To limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses can be programmed.
This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.
The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This value represents the guaranteed minimum number of cycles between two consecutive transactions on the AHB bus.
The update of the dead time value while the DMA2D is running will be taken into account for the next AHB transfer.
An interrupt can be generated on the following events:
Separate interrupt enable bits are available for flexibility.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Configuration error | CEIF | CEIE |
| CLUT transfer complete | CTCIF | CTCIE |
| CLUT access error | CAEIF | CAEIE |
| Transfer watermark | TWF | TWIE |
| Transfer complete | TCIF | TCIE |
| Transfer error | TEIF | TEIE |
Address offset: 0x0000
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MODE[1:0] |
Res. | Res. | CEIE | CTCIE | CAEIE | TWIE | TCIE | TEIE | Res. | Res. | Res. | Res. | Res. | ABORT | SUSP | START |
|
| rw | rw |
rw | rw | rw | rw | rw | rw | rs | rw | rs |
|||||||||||||||||||||
| Bits 31:18 | Reserved, must be kept at reset value |
| Bits 17:16 | MODE[1:0]: DMA2D mode |
|
These bits are set and cleared by software. They cannot be modified while a transfer is ongoing. |
|
| Bits 15:14 | Reserved, must be kept at reset value |
| Bit 13 | CEIE: Configuration Error Interrupt Enable |
|
This bit is set and cleared by software. |
|
| Bit 12 | CTCIE: CLUT transfer complete interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 11 | CAEIE: CLUT access error interrupt enable |
|
This bit is set and cleared by software. 0: CAE interrupt disable |
|
| Bit 10 | TWIE: Transfer watermark interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 9 | TCIE: Transfer complete interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 8 | TEIE: Transfer error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bits 7:3 | Reserved, must be kept at reset value |
| Bit 2 | ABORT: Abort |
|
This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. |
|
| Bit 1 | SUSP: Suspend |
|
This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. |
|
| Bit 0 | START: Start |
|
This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers. This bit is automatically reset by the following events:
|
Address offset: 0x0004
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CEIF | CTCIF | CAEIF | TWIF | TCIF | TEIF |
| r | r | r | r | r | r |
| Bits 31:6 | Reserved, must be kept at reset value |
| Bit 5 | CEIF: Configuration error interrupt flag |
|
This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. |
|
| Bit 4 | CTCIF: CLUT transfer complete interrupt flag |
|
This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. |
|
| Bit 3 | CAEIF: CLUT access error interrupt flag |
|
This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. |
|
| Bit 2 | TWIF: Transfer watermark interrupt flag |
|
This bit is set when the last pixel of the watermarked line has been transferred. |
|
| Bit 1 | TCIF: Transfer complete interrupt flag |
|
This bit is set when a DMA2D transfer operation is complete (data transfer only). |
|
| Bit 0 | TEIF: Transfer error interrupt flag |
|
This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). |
Address offset: 0x0008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCEIF | CCTCIF | CAECIF | CTWIF | CTCIF | CTEIF |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:6 | Reserved, must be kept at reset value |
| Bit 5 | CCEIF: Clear configuration error interrupt flag |
|
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register |
|
| Bit 4 | CCTCIF: Clear CLUT transfer complete interrupt flag |
|
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register |
|
| Bit 3 | CAECIF: Clear CLUT access error interrupt flag |
|
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register |
|
| Bit 2 | CTWIF: Clear transfer watermark interrupt flag |
|
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register |
|
| Bit 1 | CTCIF: Clear transfer complete interrupt flag |
|
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register |
|
| Bit 0 | CTEIF: Clear Transfer error interrupt flag |
|
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register |
Address offset: 0x000C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MA[31:16] |
MA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MA[31: 0]: Memory address |
|
Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. |
Address offset: 0x0010
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | LO[13:0] |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value |
| Bits 13:0 | LO[13: 0]: Line offset |
|
Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. |
Address offset: 0x0014
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MA[31:16] |
MA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | 0 MA[31: 0]: Memory address |
|
Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read- |
Address offset: 0x0018
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | LO[13:0] |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value |
| Bits 13:0 | LO[13: 0]: Line offset |
|
Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. |
Address offset: 0x001C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALPHA[7:0] | Res. | Res. | RBS | AI | Res. | Res. | AM[1:0] |
CS[7:0] | Res. | Res. | START | CCM | CM[3:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rs | rw | rw | rw | rw | rw |
||||||
| Bits 31:24 | ALPHA[7: 0]: Alpha value |
|
These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. |
|
| Bits 23:22 | Reserved, must be kept at reset value |
| Bit 21 | RBS: Red Blue Swap |
|
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the |
|
| Bit 20 | AI: AI: Alpha Inverted |
|
This bit inverts the alpha value. Once the transfer has started, this bit is read-only. |
|
| Bits 19:18 | Reserved, must be kept at reset value |
| Bits 17:16 | AM[1: 0]: Alpha mode |
|
These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. |
|
| Bits 15:8 | CS[7: 0]: CLUT size |
|
These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. |
|
| Bits 7:6 | Reserved, must be kept at reset value |
| Bit 5 | START: Start |
|
This bit can be set to start the automatic loading of the CLUT. It is automatically reset:
|
|
| Bit 4 | CCM: CLUT color mode |
|
This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. |
|
| Bits 3:0 | CM[3: 0]: Color mode |
|
These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x0020
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[7:0] |
GREEN[7:0] | BLUE[7:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:24 | Reserved, must be kept at reset value |
| Bits 23:16 | RED[7: 0]: Red Value |
|
These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 15:8 | GREEN[7: 0]: Green Value |
|
These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. |
|
| Bits 7:0 | BLUE[7: 0]: Blue Value |
|
These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. |
Address offset: 0x0024
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALPHA[7:0] | Res. | Res. | RBS | AI | Res. | Res. | AM[1:0] |
CS[7:0] | Res. | Res. | START | CCM | CM[3:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rs | rw | rw | rw | rw | rw |
||||||
| Bits 31:24 | ALPHA[7: 0]: Alpha value |
|
These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 23:22 | Reserved, must be kept at reset value |
| Bit 21 | RBS: Red Blue Swap |
|
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the |
|
| Bit 20 | AI: AI: Alpha Inverted |
|
This bit inverts the alpha value. Once the transfer has started, this bit is read-only. |
|
| Bits 19:18 | Reserved, must be kept at reset value |
| Bits 17:16 | AM[1: 0]: Alpha mode |
|
These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 15:8 | CS[7: 0]: CLUT size |
|
These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. |
|
| Bits 7:6 | Reserved, must be kept at reset value |
| Bit 5 | START: Start |
|
This bit is set to start the automatic loading of the CLUT. This bit is automatically reset:
|
|
| Bit 4 | CCM: CLUT Color mode |
|
These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. |
|
| Bits 3:0 | CM[3: 0]: Color mode |
|
These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read- |
Address offset: 0x0028
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[7:0] |
GREEN[7:0] | BLUE[7:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:24 | Reserved, must be kept at reset value |
| Bits 23:16 | RED[7: 0]: Red Value |
|
These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 15:8 | GREEN[7: 0]: Green Value |
|
These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 7:0 | BLUE[7: 0]: Blue Value |
|
These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x002C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MA[31:16] |
MA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | 0 MA[31: 0]: Memory Address |
|
Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. |
Address offset: 0x0030
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MA[31:16] |
MA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | 0 MA[31: 0]: Memory address |
|
Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. |
Address offset: 0x0034
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RBS | AI | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CM[2:0] |
||
| rw | rw |
rw | rw | rw | |||||||||||||||||||||||||||
| Bits 31:22 | Reserved, must be kept at reset value |
| Bit 21 | RBS: Red Blue Swap |
|
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the |
|
| Bit 20 | AI: Alpha Inverted |
|
This bit inverts the alpha value. Once the transfer has started, this bit is read-only. |
|
| Bits 19:3 | Reserved, must be kept at reset value |
| Bits 2:0 | CM[2: 0]: Color mode |
|
These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x0038
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ALPHA[7:0] | RED[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GREEN[7:0] | BLUE[7:0] |
||||||||||||||
| RED[4:0] | GREEN[5:0] | BLUE[4:0] |
|||||||||||||
| A | RED[4:0] | GREEN[4:0] | BLUE[4:0] |
||||||||||||
| ALPHA[3:0] | RED[3:0] | GREEN[3:0] | BLUE[3:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | ALPHA[7: 0]: Alpha Channel Value |
|
These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 23:16 | RED[7: 0]: Red Value |
|
These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 15:8 | GREEN[7: 0]: Green Value |
|
These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 7:0 | BLUE[7: 0]: Blue Value |
|
These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x003C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MA[31:16] |
MA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | 0 MA[31: 0]: Memory Address |
|
Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x0040
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | LO[13:0] |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value |
| Bits 13:0 | LO[13: 0]: Line Offset |
|
Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x0044
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | PL[13:0] |
NL[15:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bits 31:30 | Reserved, must be kept at reset value |
| Bits 29:16 | PL[13: 0]: Pixel per lines |
|
Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
|
| Bits 15:0 | NL[15: 0]: Number of lines |
|
Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x0048
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
LW[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bits 15:0 | LW[15:0]: Line watermark |
|
These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. |
Address offset: 0x004C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DT[7:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||||
| Bits 31:16 | Reserved |
| Bits 15:8 | DT[7: 0]: Dead Time |
|
Dead time value in the AHB clock cycle inserted between two consecutive accesses on the AHB master port. These bits represent the minimum guaranteed number of cycles between two consecutive AHB accesses. |
|
| Bits 7:1 | Reserved |
| Bit 0 | EN: Enable |
|
Enables the dead time functionality. |
The following table summarizes the DMA2D registers. Refer to Section 2.2.2 on page 76 for the DMA2D register base address.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 |
DMA2D_CR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MODE[1:0] | Res. | Res. | CEIE | CTCIE | CAEIE | TWIE | TCIE | TEIE | Res. | Res. | Res. | Res. | Res. | ABORT | SUSP | START | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x0004 |
DMA2D_ISR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CEIF | CTCIF | CAEIF | TWIF | TCIF | TEIF |
| 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0008 |
DMA2D_IFCR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCEIF | CCTCIF | CAECIF | CTWIF | CTCIF | CTEIF |
| 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x000C |
DMA2D_FGMAR Reset value |
MA[31:0] |
|||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x0010 |
DMA2D_FGOR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LO[13:0] |
|||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x0014 |
DMA2D_BGMAR Reset value |
MA[31:0] |
|||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x0018 |
DMA2D_BGOR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LO[13:0] |
|||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x001C |
DMA2D_FGPFCCR Reset value |
ALPHA[7:0] |
Res. | Res. | RBS | AI | Res. | Res. | AM[1:0] | CS[7:0] |
Res. | Res. | START | CCM | CM[3:0] |
||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x0020 |
DMA2D_FGCOLR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[7:0] | GREEN[7:0] | BLUE[7:0] |
|||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0024 |
DMA2D_BGPFCCR Reset value |
ALPHA[7:0] |
Res. | Res. | RBS | AI | Res. | Res. | AM[1:0] | CS[7:0] |
Res. | Res. | START | CCM | CM[3:0] |
||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x0028 |
DMA2D_BGCOLR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[7:0] | GREEN[7:0] | BLUE[7:0] |
|||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x002C |
DMA2D_FGCMAR Reset value |
MA[31:0] |
|||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x0030 |
DMA2D_BGCMAR Reset value |
MA[31:0] |
|||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x0034 |
DMA2D_OPFCCR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RBS | AI | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CM[2:0] |
||
| 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||||
| 0x0038 | DMA2D_OCOLR |
ALPHA[7:0] | RED[7:0] | GREEN[7:0] | BLUE[7:0] |
||||||||||||||||||||||||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[4:0] | GREEN[5:0] | BLUE[4:0] |
|||||||||||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | A | RED[4:0] | GREEN[4:0] | BLUE[4:0] |
||||||||||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALPHA[3:0] | RED[3:0] | GREEN[3:0] | BLUE[3:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x003C | DMA2D_OMAR | MA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0040 |
DMA2D_OOR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LO[13:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x0044 |
DMA2D_NLR |
Res. | Res. | PL[13:0] | NL[15:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||
| 0x0048 |
DMA2D_LWR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LW[15:0] |
|||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x004C |
DMA2D_AMTCR Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DT[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x0050- Ox03FC |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0400- 0x07FC |
DMA2D_FGCLUT Reset value |
ALPHA[7:0][255:0] | RED[7:0][255:0] | GREEN[7:0][255:0] | BLUE[7:0][255:0] |
||||||||||||||||||||||||||||
| X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
||
| 0x0800- 0x0BFF |
DMA2D_BGCLUT Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RED[7:0][255:0] | GREEN[7:0][255:0] | BLUE[7:0][255:0] |
|||||||||||||||||||||
| X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
||||||||||
The nested vector interrupt controller NVIC includes the following features:
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PMxxxx.
The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz).
See Table 46, for the vector table for the STM32F76xxx and STM32F77xxx devices.
| Position | Priority | Type of priority | Acronym | Description | Offset |
|---|---|---|---|---|---|
| - | - | - | - | Reserved | 0x0000 0000 |
| - | -3 | fixed | Reset | Reset | 0x0000 0004 |
| - | -2 | fixed | NMI |
Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. |
0x0000 0008 |
| - | -1 | fixed | HardFault | All class of fault | 0x0000 000C |
| - | 0 | settable | MemManage | Memory management | 0x0000 0010 |
| - | 1 | settable | BusFault | Pre-fetch fault, memory access fault | 0x0000 0014 |
| - | 2 | settable | UsageFault | Undefined instruction or illegal state | 0x0000 0018 |
| - | - | - | - | Reserved | 0x0000 001C - 0x0000 002B |
| - | 3 | settable | SVCall | System service call via SWI instruction | 0x0000 002C |
| - | 4 | settable | Debug Monitor | Debug Monitor | 0x0000 0030 |
| - | - | - | - | Reserved | 0x0000 0034 |
| - | 5 | settable | PendSV | Pendable request for system service | 0x0000 0038 |
| - | 6 | settable | SysTick | System tick timer | 0x0000 003C |
| 0 | 7 | settable | WWDG | Window Watchdog interrupt | 0x0000 0040 |
| 1 | 8 | settable | PVD | PVD through EXTI line detection interrupt | 0x0000 0044 |
| 2 | 9 | settable | TAMP_STAMP | Tamper and TimeStamp interrupts through the EXTI line | 0x0000 0048 |
| 3 | 10 | settable | RTC_WKUP | RTC Wakeup interrupt through the EXTI line | 0x0000 004C |
| 4 | 11 | settable | FLASH | Flash global interrupt | 0x0000 0050 |
| 5 | 12 | settable | RCC | RCC global interrupt | 0x0000 0054 |
| 6 | 13 | settable | EXTI0 | EXTI Line0 interrupt | 0x0000 0058 |
| 7 | 14 | settable | EXTI1 | EXTI Line1 interrupt | 0x0000 005C |
| 8 | 15 | settable | EXTI2 | EXTI Line2 interrupt | 0x0000 0060 |
| 9 | 16 | settable | EXTI3 | EXTI Line3 interrupt | 0x0000 0064 |
| 10 | 17 | settable | EXTI4 | EXTI Line4 interrupt | 0x0000 0068 |
| 11 | 18 | settable | DMA1_Stream0 | DMA1 Stream0 global interrupt | 0x0000 006C |
| 12 | 19 | settable | DMA1_Stream1 | DMA1 Stream1 global interrupt | 0x0000 0070 |
| 13 | 20 | settable | DMA1_Stream2 | DMA1 Stream2 global interrupt | 0x0000 0074 |
| 14 | 21 | settable | DMA1_Stream3 | DMA1 Stream3 global interrupt | 0x0000 0078 |
| 15 | 22 | settable | DMA1_Stream4 | DMA1 Stream4 global interrupt | 0x0000 007C |
| 16 | 23 | settable | DMA1_Stream5 | DMA1 Stream5 global interrupt | 0x0000 0080 |
| 17 | 24 | settable | DMA1_Stream6 | DMA1 Stream6 global interrupt | 0x0000 0084 |
| 18 | 25 | settable | ADC | ADC1, ADC2 and ADC3 global interrupts | 0x0000 0088 |
| 19 | 26 | settable | CAN1_TX | CAN1 TX interrupts | 0x0000 008C |
| 20 | 27 | settable | CAN1_RX0 | CAN1 RX0 interrupts | 0x0000 0090 |
| 21 | 28 | settable | CAN1_RX1 | CAN1 RX1 interrupt | 0x0000 0094 |
| 22 | 29 | settable | CAN1_SCE | CAN1 SCE interrupt | 0x0000 0098 |
| 23 | 30 | settable | EXTI9_5 | EXTI Line[9:5] interrupts | 0x0000 009C |
| 24 | 31 | settable | TIM1_BRK_TIM9 | TIM1 Break interrupt and TIM9 global interrupt | 0x0000 00A0 |
| 25 | 32 | settable | TIM1_UP_TIM10 | TIM1 Update interrupt and TIM10 global interrupt | 0x0000 00A4 |
| 26 | 33 | settable | TIM1_TRG_COM_TIM11 | TIM1 Trigger and Commutation interrupts and TIM11 global interrupt | 0x0000 00A8 |
| 27 | 34 | settable | TIM1_CC | TIM1 Capture Compare interrupt | 0x0000 00AC |
| 28 | 35 | settable | TIM2 | TIM2 global interrupt | 0x0000 00B0 |
| 29 | 36 | settable | TIM3 | TIM3 global interrupt | 0x0000 00B4 |
| 30 | 37 | settable | TIM4 | TIM4 global interrupt | 0x0000 00B8 |
| 31 | 38 | settable | I2C1_EV | I2C1 event interrupt | 0x0000 00BC |
| 32 | 39 | settable | I2C1_ER | I2C1 error interrupt | 0x0000 00C0 |
| 33 | 40 | settable | I2C2_EV | I2C2 event interrupt | 0x0000 00C4 |
| 34 | 41 | settable | I2C2_ER | I2C2 error interrupt | 0x0000 00C8 |
| 35 | 42 | settable | SPI1 | SPI1 global interrupt | 0x0000 00CC |
| 36 | 43 | settable | SPI2 | SPI2 global interrupt | 0x0000 00D0 |
| 37 | 44 | settable | USART1 | USART1 global interrupt | 0x0000 00D4 |
| 38 | 45 | settable | USART2 | USART2 global interrupt | 0x0000 00D8 |
| 39 | 46 | settable | USART3 | USART3 global interrupt | 0x0000 00DC |
| 40 | 47 | settable | EXTI15_10 | EXTI Line[15:10] interrupts | 0x0000 00E0 |
| 41 | 48 | settable | RTC_Alarm | RTC Alarms (A and B) through EXTI line interrupt | 0x0000 00E4 |
| 42 | 49 | settable | OTG_FS_WKUP | USB On-The-Go FS Wakeup through EXTI line interrupt | 0x0000 00E8 |
| 43 | 50 | settable | TIM8_BRK_TIM12 | TIM8 Break interrupt and TIM12 global interrupt | 0x0000 00EC |
| 44 | 51 | settable | TIM8_UP_TIM13 | TIM8 Update interrupt and TIM13 global interrupt | 0x0000 00F0 |
| 45 | 52 | settable | TIM8_TRG_COM_TIM14 | TIM8 Trigger and Commutation interrupts and TIM14 global interrupt | 0x0000 00F4 |
| 46 | 53 | settable | TIM8_CC | TIM8 Capture Compare interrupt | 0x0000 00F8 |
| 47 | 54 | settable | DMA1_Stream7 | DMA1 Stream7 global interrupt | 0x0000 00FC |
| 48 | 55 | settable | FMC | FMC global interrupt | 0x0000 0100 |
| 49 | 56 | settable | SDMMC1 | SDMMC1 global interrupt | 0x0000 0104 |
| 50 | 57 | settable | TIM5 | TIM5 global interrupt | 0x0000 0108 |
| 51 | 58 | settable | SPI3 | SPI3 global interrupt | 0x0000 010C |
| 52 | 59 | settable | UART4 | UART4 global interrupt | 0x0000 0110 |
| 53 | 60 | settable | UART5 | UART5 global interrupt | 0x0000 0114 |
| 54 | 61 | settable | TIM6_DAC |
TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts |
0x0000 0118 |
| 55 | 62 | settable | TIM7 | TIM7 global interrupt | 0x0000 011C |
| 56 | 63 | settable | DMA2_Stream0 | DMA2 Stream0 global interrupt | 0x0000 0120 |
| 57 | 64 | settable | DMA2_Stream1 | DMA2 Stream1 global interrupt | 0x0000 0124 |
| 58 | 65 | settable | DMA2_Stream2 | DMA2 Stream2 global interrupt | 0x0000 0128 |
| 59 | 66 | settable | DMA2_Stream3 | DMA2 Stream3 global interrupt | 0x0000 012C |
| 60 | 67 | settable | DMA2_Stream4 | DMA2 Stream4 global interrupt | 0x0000 0130 |
| 61 | 68 | settable | ETH | Ethernet global interrupt | 0x0000 0134 |
| 62 | 69 | settable | ETH_WKUP | Ethernet Wakeup through EXTI line interrupt | 0x0000 0138 |
| 63 | 70 | settable | CAN2_TX | CAN2 TX interrupts | 0x0000 013C |
| 64 | 71 | settable | CAN2_RX0 | CAN2 RX0 interrupts | 0x0000 0140 |
| 65 | 72 | settable | CAN2_RX1 | CAN2 RX1 interrupt | 0x0000 0144 |
| 66 | 73 | settable | CAN2_SCE | CAN2 SCE interrupt | 0x0000 0148 |
| 67 | 74 | settable | OTG_FS | USB On The Go FS global interrupt | 0x0000 014C |
| 68 | 75 | settable | DMA2_Stream5 | DMA2 Stream5 global interrupt | 0x0000 0150 |
| 69 | 76 | settable | DMA2_Stream6 | DMA2 Stream6 global interrupt | 0x0000 0154 |
| 70 | 77 | settable | DMA2_Stream7 | DMA2 Stream7 global interrupt | 0x0000 0158 |
| 71 | 78 | settable | USART6 | USART6 global interrupt | 0x0000 015C |
| 72 | 79 | settable | I2C3_EV | I2C3 event interrupt | 0x0000 0160 |
| 73 | 80 | settable | I2C3_ER | I2C3 error interrupt | 0x0000 0164 |
| 74 | 81 | settable | OTG_HS_EP1_OUT | USB On The Go HS End Point 1 Out global interrupt | 0x0000 0168 |
| 75 | 82 | settable | OTG_HS_EP1_IN | USB On The Go HS End Point 1 In global interrupt | 0x0000 016C |
| 76 | 83 | settable | OTG_HS_WKUP | USB On The Go HS Wakeup through EXTI interrupt | 0x0000 0170 |
| 77 | 84 | settable | OTG_HS | USB On The Go HS global interrupt | 0x0000 0174 |
| 78 | 85 | settable | DCMI | DCMI global interrupt | 0x0000 0178 |
| 79 | 86 | settable | CRYP | CRYP crypto global interrupt | 0x0000 017C |
| 80 | 87 | settable | HASH_RNG | Hash and Rng global interrupt | 0x0000 0180 |
| 81 | 88 | settable | FPU | FPU global interrupt | 0x0000 0184 |
| 82 | 89 | settable | UART7 | UART7 global interrupt | 0x0000 0188 |
| 83 | 90 | settable | UART8 | UART8 global interrupt | 0x0000 018C |
| 84 | 91 | settable | SPI4 | SPI4 global interrupt | 0x0000 0190 |
| 85 | 92 | settable | SPI5 | SPI5 global interrupt | 0x0000 0194 |
| 86 | 93 | settable | SPI6 | SPI6 global interrupt | 0x0000 0198 |
| 87 | 94 | settable | SAI1 | SAI1 global interrupt | 0x0000 019C |
| 88 | 95 | settable | LCD-TFT | LCD-TFT global interrupt | 0x0000 01A0 |
| 89 | 96 | settable | LCD-TFT | LCD-TFT global Error interrupt | 0x0000 01A4 |
| 90 | 97 | settable | DMA2D | DMA2D global interrupt | 0x0000 01A8 |
| 91 | 98 | settable | SAI2 | SAI2 global interrupt | 0x0000 01AC |
| 92 | 99 | settable | QuadSPI | QuadSPI global interrupt | 0x0000 01B0 |
| 93 | 100 | settable | LP Timer1 | LP Timer1 global interrupt | 0x0000 01B4 |
| 94 | 101 | settable | HDMI-CEC | HDMI-CEC global interrupt | 0x0000 01B8 |
| 95 | 102 | settable | I2C4_EV | I2C4 event interrupt | 0x0000 01BC |
| 96 | 103 | settable | I2C4_ER | I2C4 Error interrupt | 0x0000 01C0 |
| 97 | 104 | settable | SPDIFRX | SPDIFRX global interrupt | 0x0000 01C4 |
| 98 | 105 | settable | DSIHOST | DSI host global interrupt | 0x0000 01C8 |
| 99 | 106 | settable | DFSDM1_FLT0 | DFSDM1 Filter 0 global interrupt | 0x0000 01CC |
| 100 | 107 | settable | DFSDM1_FLT1 | DFSDM1 Filter 1 global interrupt | 0x0000 01D0 |
| 101 | 108 | settable | DFSDM1_FLT2 | DFSDM1 Filter 2 global interrupt | 0x0000 01D4 |
| 102 | 109 | settable | DFSDM1_FLT3 | DFSDM1 Filter 3 global interrupt | 0x0000 01D8 |
| 103 | 110 | settable | SDMMC2 | SDMMC2 global interrupt | 0x0000 01DC |
| 104 | 111 | settable | CAN3_TX | CAN3 TX interrupt | 0x0000 01E0 |
| 105 | 112 | settable | CAN3_RX0 | CAN3 RX0 interrupt | 0x0000 01E4 |
| 106 | 113 | settable | CAN3_RX1 | CAN3 RX1 interrupt | 0x0000 01E8 |
| 107 | 114 | settable | CAN3_SCE | CAN3 SCE interrupt | 0x0000 01EC |
| 108 | 115 | settable | JPEG | JPEG global interrupt | 0x0000 01F0 |
| 109 | 116 | settable | MDIOS | MDIO slave global interrupt | 0x0000 01F4 |
The external interrupt/event controller consists of up to 25 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests.
The main features of the EXTI controller are the following:
Figure 30 shows the block diagram.
| (omitted) |
The STM32F76xxx and STM32F77xxx devices are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by:
To use an external line as a wakeup event, refer to Section 11.4: Functional description.
To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.
An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register.
To configure a line as interrupt sources, use the following procedure:
To configure a line as event sources, use the following procedure:
The line can be configured as software interrupt/event line. The following is the procedure to generate a software interrupt.
Up to 168 GPIOs are connected to the 16 external interrupt/event lines in the following manner:
| (omitted) |
The eight other EXTI lines are connected as follows:
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | MR24 | MR23 | MR22 | MR21 | MR20 | MR19 | MR18 | MR17 | MR16 |
MR15 | MR14 | MR13 | MR12 | MR11 | MR10 | MR9 | MR8 | MR7 | MR6 | MR5 | MR4 | MR3 | MR2 | MR1 | MR0 |
| rw | rw rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | MRx: Interrupt mask on line x |
|
0: Interrupt request from line x is masked |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | MR24 | MR23 | MR22 | MR21 | MR20 | MR19 | MR18 | MR17 | MR16 |
MR15 | MR14 | MR13 | MR12 | MR11 | MR10 | MR9 | MR8 | MR7 | MR6 | MR5 | MR4 | MR3 | MR2 | MR1 | MR0 |
| rw | rw rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | MRx: Event mask on line x |
|
0: Event request from line x is masked |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TR24 | TR23 | TR22 | TR21 | TR20 | TR19 | TR18 | TR17 | TR16 |
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | TRx: Rising trigger event configuration bit of line x |
|
0: Rising trigger disabled (for Event and Interrupt) for input line |
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TR24 | TR23 | TR22 | TR21 | TR20 | TR19 | TR18 | TR17 | TR16 |
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | TRx: Falling trigger event configuration bit of line x |
|
0: Falling trigger disabled (for Event and Interrupt) for input line |
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWIER 23 |
SWIER 23 |
SWIER 22 |
SWIER 21 |
SWIER 20 |
SWIER 19 |
SWIER 18 |
SWIER 17 |
SWIER 16 |
SWIER 15 |
SWIER 14 |
SWIER 13 |
SWIER 12 |
SWIER 11 |
SWIER 10 |
SWIER 9 |
SWIER 8 |
SWIER 7 |
SWIER 6 |
SWIER 5 |
SWIER 4 |
SWIER 3 |
SWIER 2 |
SWIER 1 |
SWIER 0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | SWIERx: Software Interrupt on line x |
|
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit). |
Address offset: 0x14
Reset value: undefined
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR24 | PR23 | PR22 | PR21 | PR20 | PR19 | PR18 | PR17 | PR16 |
PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 |
|||||||||||||||
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | PRx: Pending bit |
|
0: No trigger request occurred |
Table 47 gives the EXTI register map and the reset values.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
EXTI_IMR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | MR[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x04 |
EXTI_EMR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | MR[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x08 |
EXTI_RTSR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TR[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0C |
EXTI_FTSR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TR[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x10 |
EXTI_SWIER
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWIER[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x14 |
EXTI_PR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR[24:0] |
||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
| (omitted) |
| Signal name | Signal type | Description |
|---|---|---|
| crc_hclk | Digital input | AHB clock |
The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).
Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
0x58D43CB2 with bit-reversal done by byte
0xD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.
Address offset: 0x00
Reset value: 0xFFFF FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DR[31:16] |
DR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DR[31:0]: Data register bits |
|
This register is used to write new data to the CRC calculator. |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IDR[7:0] |
| rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | IDR[7:0]: General-purpose 8-bit data register bits |
|
These bits can be used as a temporary storage location for one byte. |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | REV_ OUT |
REV_IN[1:0] | POLYSIZE[1:0] | Res. | Res. | RESET |
||
| rw | rw | rw | rw | rw | rs |
||||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | REV_OUT: Reverse output data |
|
This bit controls the reversal of the bit order of the output data. |
|
| Bits 6:5 | REV_IN[1:0]: Reverse input data |
|
These bits control the reversal of the bit order of the input data |
|
| Bits 4:3 | POLYSIZE[1:0]: Polynomial size |
|
These bits control the size of the polynomial. |
|
| Bits 2:1 | Reserved, must be kept at reset value. |
| Bit 0 | RESET: RESET bit |
|
This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware |
Address offset: 0x10
Reset value: 0xFFFF FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CRC_INIT[31:16] |
CRC_INIT[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 |
CRC_INIT[31:0]
: Programmable initial CRC value
|
|
This register is used to write the CRC initial value. |
Address offset: 0x14
Reset value: 0x04C1 1DB7
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POL[31:16] |
POL[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | POL[31:0]: Programmable polynomial |
|
This register is used to write the coefficients of the polynomial to be used for CRC calculation. |
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
CRC_DR | DR[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x04 |
CRC_IDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IDR[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x08 |
CRC_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | REV_OUT | REV_IN[1:0] | POLYSIZE[1:0] | Res. | Res. | RESET | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x10 |
CRC_INIT | CRC_INIT[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x14 |
CRC_POL | Polynomial coefficients |
|||||||||||||||||||||||||||||||
| Reset value | 0x04C11DB7 | ||||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The Flexible memory controller (FMC) includes three memory controllers:
The FMC functional block makes the interface with: synchronous and asynchronous static memories, SDRAM memories, and NAND Flash memory. Its main purposes are:
All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FMC performs only one access at a time to an external device.
The main features of the FMC controller are the following:
The Write FIFO is common to all memory controllers and consists of:
The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register.
At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes.
The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time.
The FMC consists of the following main blocks:
The block diagram is shown in the figure below.
| (omitted) |
The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories.
AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses except in case of access mode D when the extended mode is enabled.
The FMC generates an AHB error in the following conditions:
The effect of an AHB error depends on the AHB master which has attempted the R/W access:
The AHB clock (HCLK) is the reference clock for the FMC.
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
AHB transaction size and memory data size are equal
There is no issue in this case.
AHB transaction size is greater than the memory size:
In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses.
AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM, SDRAM)
In this case, the FMC allows read/write transactions and accesses the right data through its byte lanes NBL[3:0].
Bytes to be written are addressed by NBL[3:0].
All memory bytes are read (NBL[3:0] are driven low during read transaction) and the useless ones are discarded.
Accesses to devices that do not have the byte select feature (NOR and NAND Flash memories)
This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Since the device cannot be accessed in byte mode (only 16-bit words can be read/written from/to the Flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).
Wrap support for NOR Flash/PSRAM and SDRAM
The synchronous memories must be configured in linear burst mode of undefined length as not all masters can issue a wrap transactions.
If a master generates an AHB wrap transaction:
Configuration registers
The FMC can be configured through a set of registers. Refer to Section 13.5.6, for a detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 13.6.7, for a detailed description of the NAND Flash registers and to Section 13.7.5 for a detailed description of the SDRAM controller registers.
From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 34):
For each bank the type of memory to be used can be configured by the user application through the Configuration register.
| (omitted) |
HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 50.
| HADDR[27:26](1) |
Selected bank |
|---|---|
| 00 | Bank 1 - NOR/PSRAM 1 |
| 01 | Bank 1 - NOR/PSRAM 2 |
| 10 | Bank 1 - NOR/PSRAM 3 |
| 11 | Bank 1 - NOR/PSRAM 4 |
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.
| Memory width(1) |
Data address issued to the memory | Maximum memory capacity (bits) |
|---|---|---|
| 8-bit | HADDR[25:0] | 64 Mbytes x 8 = 512 Mbit |
| 16-bit | HADDR[25:1] >> 1 | 64 Mbytes/2 x 16 = 512 Mbit |
| 32-bit | HADDR[25:2] >> 2 | 64 Mbytes/4 x 32 = 512 Mbit |
The NAND bank is divided into memory areas as indicated in Table 52.
| Start address | End address | FMC bank | Memory space | Timing register |
|---|---|---|---|---|
| 0x8800 0000 | 0x8BFF FFFF |
Bank 3 - NAND Flash |
Attribute | FMC_PATT (0x8C) |
| 0x8000 0000 | 0x83FF FFFF | Common | FMC_PMEM (0x88) |
For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 53 below) located in the lower 256 Kbytes:
| Section name | HADDR[17:16] | Address range |
|---|---|---|
| Address section | 1X | 0x020000-0x03FFFF |
| Command section | 01 | 0x010000-0x01FFFF |
| Data section | 00 | 0x000000-0x0FFFF |
The application software uses the 3 sections to access the NAND Flash memory:
Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.
The HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory banks as indicated in Table 54.
| HADDR[28] | Selected bank | Control register | Timing register |
|---|---|---|---|
| 0 | SDRAM Bank1 | FMC_SDCR1 | FMC_SDTR1 |
| 1 | SDRAM Bank2 | FMC_SDCR2 | FMC_SDTR2 |
The following table shows SDRAM mapping for a 13-bit row, a 11-bit column and a 4 internal bank configuration.
| Memory width(1) |
Internal bank | Row address | Column address(2) |
Maximum memory capacity (Mbytes) |
|---|---|---|---|---|
| 8-bit | HADDR[25:24] | HADDR[23:11] | HADDR[10:0] | 64 Mbytes: 4 x 8K x 2K |
| 16-bit | HADDR[26:25] | HADDR[24:12] | HADDR[11:1] |
128 Mbytes: 4 x 8K x 2K x 2 |
| 32-bit | HADDR[27:26] | HADDR[25:13] | HADDR[12:2] |
256 Mbytes: 4 x 8K x 2K x 4 |
The HADDR[27:0] bits are translated to external SDRAM address depending on the SDRAM controller configuration:
The following tables show the SDRAM address mapping versus the SDRAM controller configuration.
| Row size configuration |
HADDR(AHB Internal Address Lines) |
|||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
11-bit row size configuration |
Res. | Bank [1:0] |
Row[10:0] | Column[7:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[8:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[9:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[10:0] |
|||||||||||||||||||||||||
|
12-bit row size configuration |
Res. | Bank [1:0] |
Row[11:0] | Column[7:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[8:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[9:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[10:0] |
|||||||||||||||||||||||||
|
13-bit row size configuration |
Res. | Bank [1:0] |
Row[12:0] | Column[7:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[8:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[9:0] |
|||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[10:0] |
|||||||||||||||||||||||||
| Row size Configuration |
HADDR(AHB address Lines) |
|||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|
11-bit row size configuration |
Res. | Bank [1:0] |
Row[10:0] | Column[7:0] | BM0(3) |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[8:0] | BM0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[9:0] | BM0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[10:0] | BM0 |
||||||||||||||||||||||||
|
12-bit row size configuration |
Res. | Bank [1:0] |
Row[11:0] | Column[7:0] | BM0 |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[8:0] | BM0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[9:0] | BM0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[10:0] | BM0 |
||||||||||||||||||||||||
|
13-bit row size configuration |
Res. | Bank [1:0] |
Row[12:0] | Column[7:0] | BM0 |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[8:0] | BM0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[9:0] | BM0 |
||||||||||||||||||||||||
| Re s. |
Bank [1:0] |
Row[12:0] | Column[10:0] | BM0 |
||||||||||||||||||||||||
| Row size configuration |
HADDR(AHB address Lines) |
|||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|
11-bit row size configuration |
Res. | Bank [1:0] |
Row[10:0] | Column[7:0] | BM[1:0](3) |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[8:0] | BM[1:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[9:0] | BM[1:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[10:0] | Column[10:0] | BM[1:0] | ||||||||||||||||||||||||
|
12-bit row size configuration |
Res. | Bank [1:0] |
Row[11:0] | Column[7:0] | BM[1:0] |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[8:0] | BM[1:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[9:0] | BM[1:0] |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[11:0] | Column[10:0] | BM[1:0] |
||||||||||||||||||||||||
|
13-bit row size configuration |
Res. | Bank [1:0] |
Row[12:0] | Column[7:0] | BM[1:0 |
|||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[8:0] | BM[1:0 |
||||||||||||||||||||||||
| Res. | Bank [1:0] |
Row[12:0] | Column[9:0] | BM[1:0 |
||||||||||||||||||||||||
| Bank [1:0] |
Row[12:0] | Column[10:0] | BM[1:0 |
|||||||||||||||||||||||||
The FMC generates the appropriate signal timings to drive the following types of memories:
The FMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared.
The FMC supports a wide range of devices through a programmable timings among which:
The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register:
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 13.5.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 59) and support for wait management (for PSRAM and NOR Flash accessed in burst mode).
| Parameter | Function | Access mode | Unit | Min. | Max. |
|---|---|---|---|---|---|
| Address setup |
Duration of the address setup phase | Asynchronous | AHB clock cycle (HCLK) | 0 | 15 |
| Address hold | Duration of the address hold phase | Asynchronous, muxed I/Os | AHB clock cycle (HCLK) | 1 | 15 |
| Data setup | Duration of the data setup phase | Asynchronous | AHB clock cycle (HCLK) | 1 | 256 |
| Bust turn | Duration of the bus turnaround phase | Asynchronous and synchronous read / write |
AHB clock cycle (HCLK) | 0 | 15 |
| Clock divide ratio |
Number of AHB clock cycles (HCLK) to build one memory clock cycle (CLK) | Synchronous | AHB clock cycle (HCLK) | 2 | 16 |
| Data latency |
Number of clock cycles to issue to the memory before the first data of the burst | Synchronous | Memory clock cycle (CLK) | 2 | 17 |
Table 60, Table 61 and Table 62 list the signals that are typically used to interface with NOR Flash memory, SRAM and PSRAM.
Note: The prefix “N” identifies the signals that are active low.
NOR Flash memory, non-multiplexed I/Os
| FMC signal name | I/O | Function |
|---|---|---|
| CLK | O | Clock (for synchronous access) |
| A[25:0] | O | Address bus |
| D[31:0] | I/O | Bidirectional data bus |
| NE[x] | O | Chip select, x = 1..4 |
| NOE | O | Output enable |
| NWE | O | Write enable |
| NL(=NADV) | O | Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) |
| NWAIT | I | NOR Flash wait input signal to the FMC |
The maximum capacity is 512 Mbits (26 address lines).
NOR Flash memory, 16-bit multiplexed I/Os
| FMC signal name | I/O | Function |
|---|---|---|
| CLK | O | Clock (for synchronous access) |
| A[25:16] | O | Address bus |
| AD[15:0] | I/O | 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) |
| NE[x] | O | Chip select, x = 1..4 |
| NOE | O | Output enable |
| NWE | O | Write enable |
| NL(=NADV) | O | Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) |
| NWAIT | I | NOR Flash wait input signal to the FMC |
The maximum capacity is 512 Mbits.
PSRAM/SRAM, non-multiplexed I/Os
| FMC signal name | I/O | Function |
|---|---|---|
| CLK | O | Clock (only for PSRAM synchronous access) |
| A[25:0] | O | Address bus |
| D[31:0] | I/O | Data bidirectional bus |
| NE[x] | O | Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) |
| NOE | O | Output enable |
| NWE | O | Write enable |
| NL(= NADV) | O | Address valid only for PSRAM input (memory signal name: NADV) |
| NWAIT | I | PSRAM wait input signal to the FMC |
| NBL[3:0] | O | Byte lane output. Byte 0 to Byte 3 control (Upper and lower byte enable) |
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
| FMC signal name | I/O | Function |
|---|---|---|
| CLK | O | Clock (for synchronous access) |
| A[25:16] | O | Address bus |
| AD[15:0] | I/O | 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) |
| NE[x] | O | Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) |
| NOE | O | Output enable |
| NWE | O | Write enable |
| NL(= NADV) | O | Address valid PSRAM input (memory signal name: NADV) |
| NWAIT | I | PSRAM wait input signal to the FMC |
| NBL[1:0] | O | Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable) |
The maximum capacity is 512 Mbits (26 address lines).
Table 64 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example.
| Device | Mode | R/W |
AHB data size |
Memory data size |
Allowed/ not allowed |
Comments |
|---|---|---|---|---|---|---|
| NOR Flash (muxed I/Os and nonmuxed I/Os) | Asynchronous | R | 8 | 16 | Y | - |
| Asynchronous | W | 8 | 16 | N | - |
|
| Asynchronous | R | 16 | 16 | Y | - |
|
| Asynchronous | W | 16 | 16 | Y | - |
|
| Asynchronous | R | 32 | 16 | Y | Split into 2 FMC accesses | |
| Asynchronous | W | 32 | 16 | Y | Split into 2 FMC accesses | |
| Asynchronous page | R | - | 16 | N | Mode is not supported | |
| Synchronous | R | 8 | 16 | N | - |
|
| Synchronous | R | 16 | 16 | Y | - |
|
| Synchronous | R | 32 | 16 | Y | - |
|
| PSRAM (multiplexed I/Os and non- multiplexed I/Os) |
Asynchronous | R | 8 | 16 | Y | - |
| Asynchronous | W | 8 | 16 | Y | Use of byte lanes NBL[1:0] | |
| Asynchronous | R | 16 | 16 | Y | - |
|
| Asynchronous | W | 16 | 16 | Y | - |
|
| Asynchronous | R | 32 | 16 | Y | Split into 2 FMC accesses | |
| Asynchronous | W | 32 | 16 | Y | Split into 2 FMC accesses | |
| Asynchronous page | R | - | 16 | N | Mode is not supported | |
| Synchronous | R | 8 | 16 | N | - |
|
| Synchronous | R | 16 | 16 | Y | - |
|
| Synchronous | R | 32 | 16 | Y | - |
|
| Synchronous | W | 8 | 16 | Y | Use of byte lanes NBL[1:0] |
|
| Synchronous | W | 16/32 | 16 | Y | - |
|
| SRAM and ROM |
Asynchronous | R | 8 / 16 | 16 | Y | - |
| Asynchronous | W | 8 / 16 | 16 | Y | Use of byte lanes NBL[1:0] | |
| Asynchronous | R | 32 | 16 | Y | Split into 2 FMC accesses | |
| Asynchronous | W | 32 | 16 | Y | Split into 2 FMC accesses Use of byte lanes NBL[1:0] |
Signals synchronization
Asynchronous static memories (NOR Flash, PSRAM, SRAM)
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.
| (omitted) |
| (omitted) |
The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x0 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | Reserved | 0x0 |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | Don’t care |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | As needed, exclude 0x2 (NOR Flash memory) |
| 1 | MUXE | 0x0 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | Don’t care |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST HCLK cycles for read accesses). |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET |
Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 0. |
Mode A - SRAM/PSRAM (CRAM) OE toggling
| (omitted) |
| (omitted) |
The differences compared with Mode1 are the toggling of NOE and the independent read and write timings.
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x1 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | WAITCFG | Don’t care |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | Don’t care |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | As needed, exclude 0x2 (NOR Flash memory) |
| 1 | MUXEN | 0x0 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x0 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles) for read accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET |
Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x0 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles) for write accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET |
Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. |
Mode 2/B - NOR Flash
| (omitted) |
| (omitted) |
| (omitted) |
The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B).
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x1 for mode B, 0x0 for mode 2 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | WAITCFG | Don’t care |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | 0x1 |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | 0x2 (NOR Flash memory) |
| 1 | MUXEN | 0x0 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x1 if extended mode is set |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the access second phase (DATAST HCLK cycles) for read accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET | Duration of the access first phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x1 if extended mode is set |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the access second phase (DATAST HCLK cycles) for write accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET | Duration of the access first phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. |
Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR Flash - OE toggling
| (omitted) |
| (omitted) |
The differences compared with Mode1 are the toggling of NOE and the independent read and write timings.
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x1 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | WAITCFG | Don’t care |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | 0x1 |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | 0x02 (NOR Flash memory) |
| 1 | MUXEN | 0x0 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x2 |
| 27:24 | DATLAT | 0x0 |
| 23:20 | CLKDIV | 0x0 |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles) for read accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET | Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x2 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles) for write accesses. |
| 7:4 | ADDHLD | Don’t care |
| 3:0 | ADDSET | Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. |
Mode D - asynchronous access with extended address
| (omitted) |
| (omitted) |
The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x1 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | WAITCFG | Don’t care |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | Set according to memory support |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | As needed |
| 1 | MUXEN | 0x0 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x3 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles) for read accesses. |
| 7:4 | ADDHLD | Duration of the middle phase of the read access (ADDHLD HCLK cycles) |
| 3:0 | ADDSET | Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 1. |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x3 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST + 1 HCLK cycles) for write accesses. |
| 7:4 | ADDHLD | Duration of the middle phase of the write access (ADDHLD HCLK cycles) |
| 3:0 | ADDSET | Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 1. |
Muxed mode - multiplexed asynchronous access to NOR Flash memory
| (omitted) |
| (omitted) |
The difference with ModeD is the drive of the lower address byte(s) on the data bus.
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x0 (no effect in asynchronous mode) |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | Set to 1 if the memory supports this feature. Otherwise keep at 0. |
| 14 | EXTMOD | 0x0 |
| 13 | WAITEN | 0x0 (no effect in asynchronous mode) |
| 12 | WREN | As needed |
| 11 | WAITCFG | Don’t care |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | Meaningful only if bit 15 is 1 |
| 8 | BURSTEN | 0x0 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | 0x1 |
| 5:4 | MWID | As needed |
| 3:2 | MTYP | 0x2 (NOR Flash memory) or 0x1(PSRAM) |
| 1 | MUXEN | 0x1 |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x0 |
| 27:24 | DATLAT | Don’t care |
| 23:20 | CLKDIV | Don’t care |
| 19:16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15:8 | DATAST | Duration of the second access phase (DATAST HCLK cycles for read accesses and DATAST+1 HCLK cycles for write accesses). |
| 7:4 | ADDHLD | Duration of the middle phase of the access (ADDHLD HCLK cycles). |
| 3:0 | ADDSET | Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 1. |
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered:
DATAST≥ ( 4× HCLK ) + max_wait_assertion_time
The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time> address_phase+
hold_phase
then:
otherwise
DATAST≥ 4×
HCLK
where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.
Figure 48 and Figure 49 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).
| (omitted) |
| (omitted) |
The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below:
If MWID is 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value.
If MWID is 32-bit, the FMC_CLK divider ratio depends also on AHB data size.
Example:
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.
Data latency versus NOR memory latency
The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count.
Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either:
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.
Single-burst transfer
When the selected bank is configured in burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.
Cross boundary page for CellularRAM™ 1.5
CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FMC controller allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size.
Wait management
For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid. It does not consider the data as valid.
In burst mode, there are two timing configurations for the NOR Flash NWAIT signal:
The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
| (omitted) |
| (omitted) |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31-22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | No effect on synchronous read |
| 18:16 | CPSIZE | 0x0 (no effect in asynchronous mode) |
| 15 | ASYNCWAIT | 0x0 |
| 14 | EXTMOD | 0x0 |
| 13 | WAITEN | To be set to 1 if the memory supports this feature, to be kept at 0 otherwise |
| 12 | WREN | No effect on synchronous read |
| 11 | WAITCFG | To be set according to memory |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | To be set according to memory |
| 8 | BURSTEN | 0x1 |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | Set according to memory support (NOR Flash memory) |
| 5-4 | MWID | As needed |
| 3-2 | MTYP | 0x1 or 0x2 |
| 1 | MUXEN | As needed |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31:30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x0 |
| 27-24 | DATLAT | Data latency |
| 27-24 | DATLAT | Data latency |
| 23-20 | CLKDIV |
0x0 to get CLK = HCLK (Not supported) 0x1 to get CLK = 2 × HCLK .. |
| 19-16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15-8 | DATAST | Don’t care |
| 7-4 | ADDHLD | Don’t care |
| 3-0 | ADDSET | Don’t care |
| (omitted) |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31-22 | Reserved | 0x000 |
| 21 | WFDIS | As needed |
| 20 | CCLKEN | As needed |
| 19 | CBURSTRW | 0x1 |
| 18:16 | CPSIZE | As needed (0x1 for CRAM 1.5) |
| 15 | ASYNCWAIT | 0x0 |
| 14 | EXTMOD | 0x0 |
| 13 | WAITEN | To be set to 1 if the memory supports this feature, to be kept at 0 otherwise. |
| 12 | WREN | 0x1 |
| 11 | WAITCFG | 0x0 |
| 10 | Reserved | 0x0 |
| 9 | WAITPOL | to be set according to memory |
| 8 | BURSTEN | no effect on synchronous write |
| 7 | Reserved | 0x1 |
| 6 | FACCEN | Set according to memory support |
| 5-4 | MWID | As needed |
| 3-2 | MTYP | 0x1 |
| 1 | MUXEN | As needed |
| 0 | MBKEN | 0x1 |
| Bit number | Bit name | Value to set |
|---|---|---|
| 31-30 | Reserved | 0x0 |
| 29:28 | ACCMOD | 0x0 |
| 27-24 | DATLAT | Data latency |
| 23-20 | CLKDIV |
0x0 to get CLK = HCLK (not supported) 0x1 to get CLK = 2 × HCLK |
| 19-16 | BUSTURN | Time between NEx high to NEx low (BUSTURN HCLK). |
| 15-8 | DATAST | Don’t care |
| 7-4 | ADDHLD | Don’t care |
| 3-0 | ADDSET | Don’t care |
SRAM/NOR-Flash chip-select control register for bank x (FMC_BCRx) (x = 1 to
4)
Address offset: 8 * (x – 1), (x = 1 to 4)
Reset value: Bank 1: 0x0000 30DB
Reset value: Bank 2: 0x0000 30D2
Reset value: Bank 3: 0x0000 30D2
Reset value: Bank 4: 0x0000 30D2
This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WFDIS | CCLK EN |
CBURST RW |
CPSIZE[2:0] |
ASYNC WAIT |
EXT MOD |
WAIT EN |
WREN | WAIT CFG |
Res. | WAIT POL |
BURST EN |
Res. | FACC EN |
MWID[1:0] | MTYP[1:0] | MUX EN |
MBK EN |
||||
| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | WFDIS: Write FIFO Disable |
|
This bit disables the Write FIFO used by the FMC controller. The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the |
|
| Bit 20 | CCLKEN: Continuous Clock Enable. |
|
This bit enables the FMC_CLK clock output to external memory devices. The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the If the synchronous mode is used and CCLKEN bit is set, the synchronous memories |
|
| Bit 19 | CBURSTRW: Write burst enable. |
|
For PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. |
|
| Bits 18:16 | CPSIZE[2:0]: CRAM page size. |
|
These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). |
|
| Bit 15 | ASYNCWAIT: Wait signal during asynchronous transfers |
|
This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. |
|
| Bit 14 | EXTMOD: Extended mode enable. |
|
This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations.
When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows:
|
|
| Bit 13 | WAITEN: Wait enable bit. |
|
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. |
|
| Bit 12 | WREN: Write enable bit. |
|
This bit indicates whether write operations are enabled/disabled in the bank by the FMC: |
|
| Bit 11 | WAITCFG: Wait timing configuration. |
|
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bit 9 | WAITPOL: Wait signal polarity bit. |
|
Defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: |
|
| Bit 8 | BURSTEN: Burst enable bit. |
|
This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | FACCEN: Flash access enable |
|
Enables NOR Flash memory access operations. |
|
| Bits 5:4 | MWID[1:0]: Memory data bus width. |
|
Defines the external memory device width, valid for all type of memories. |
|
| Bits 3:2 | MTYP[1:0]: Memory type. |
|
Defines the type of external memory attached to the corresponding memory bank: |
|
| Bit 1 | MUXEN: Address/data multiplexing enable bit. |
|
When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: |
|
| Bit 0 | MBKEN: Memory bank enable bit. |
|
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
SRAM/NOR-Flash chip-select timing register for bank x (FMC_BTRx)
Address offset: 0x04 + 8 * (x – 1), (x = 1 to 4) Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | ACCMOD[1:0] | DATLAT[3:0] | CLKDIV[3:0] | BUSTURN[3:0] |
DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:28 | ACCMOD[1:0]: Access mode |
|
Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. |
|
| Bits 27:24 | DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory |
|
For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: |
|
| Bits 23:20 | CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal) |
|
Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: Refer to Section 13.5.5: Synchronous transactions for FMC_CLK divider ratio formula) |
|
| Bits 19:16 | BUSTURN[3:0]: Bus turnaround phase duration |
|
These bits are written by software to add a delay at the end of a write-to-read (and read-to-
0000: BUSTURN phase duration = 0 HCLK clock cycle added |
|
| Bits 15:8 | DATAST[7:0]: Data-phase duration |
|
These bits are written by software to define the duration of the data phase (refer to Figure 35 In synchronous accesses, this value is don’t care. |
|
| Bits 7:4 | ADDHLD[3:0]: Address-hold phase duration |
|
These bits are written by software to define the duration of the address hold phase (refer to Figure 35 to Figure 47), used in mode D or multiplexed accesses: In synchronous accesses, this value is not used, the address hold phase is always 1 |
|
| Bits 3:0 | ADDSET[3:0]: Address setup phase duration |
|
These bits are written by software to define the duration of the address setup phase (refer to Figure 35 to Figure 47), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:
In synchronous accesses, this value is don’t care.
In Muxed mode or Mode D, the minimum value for ADDSET is 1.
|
Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency
phase soon and starts sampling NWAIT from memory, then starts to read or write when the
memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)
Address offset: 0x104 + 8 * (x – 1), x = 1...4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | ACCMOD[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSTURN[3:0] |
DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
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| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
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| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:28 | ACCMOD[1:0]: Access mode. |
|
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. |
|
| Bits 27:20 | Reserved, must be kept at reset value. |
| Bits 19:16 | BUSTURN[3:0]: Bus turnaround phase duration |
|
The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different expect for muxed or mode D.
0000: BUSTURN phase duration = 0 HCLK clock cycle added |
|
| Bits 15:8 | DATAST[7:0]: Data-phase duration. |
|
These bits are written by software to define the duration of the data phase (refer to Figure 35 to Figure 47), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: |
|
| Bits 7:4 | ADDHLD[3:0]: Address-hold phase duration. |
|
These bits are written by software to define the duration of the address hold phase (refer to Figure 44 to Figure 47), used in asynchronous multiplexed accesses: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always |
|
| Bits 3:0 | ADDSET[3:0]: Address setup phase duration. |
|
These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 35 to Figure 47), used in asynchronous accesses: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash |
The FMC generates the appropriate signal timings to drive the following types of device:
The NAND bank is configured through dedicated registers (Section 13.6.7). The programmable memory parameters include access timings (shown in Table 85) and ECC configuration.
| Parameter | Function | Access mode | Unit | Min. | Max. |
|---|---|---|---|---|---|
| Memory setup time |
Number of clock cycles (HCLK) required to set up the address before the command assertion |
Read/Write | AHB clock cycle (HCLK) | 1 | 255 |
| Memory wait | Minimum duration (in HCLK clock cycles) of the command assertion | Read/Write | AHB clock cycle (HCLK) | 2 | 255 |
| Memory hold | Number of clock cycles (HCLK) during which the address must be held (as well as the data if a write access is performed) after the command de-assertion | Read/Write | AHB clock cycle (HCLK) | 1 | 254 |
| Memory databus high-Z | Number of clock cycles (HCLK) during which the data bus is kept in high-Z state after a write access has started |
Write | AHB clock cycle (HCLK) | 1 | 255 |
The following tables list the signals that are typically used to interface NAND Flash memory.
Note: The prefix “N” identifies the signals which are active low.
8-bit NAND Flash memory
| FMC signal name | I/O | Function |
|---|---|---|
| A[17] | O | NAND Flash address latch enable (ALE) signal |
| A[16] | O | NAND Flash command latch enable (CLE) signal |
| D[7:0] | I/O | 8-bit multiplexed, bidirectional address/data bus |
| NCE | O | Chip select |
| NOE(= NRE) | O | Output enable (memory signal name: read enable, NRE) |
| NWE | O | Write enable |
| NWAIT/INT | I | NAND Flash ready/busy input signal to the FMC |
Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.
16-bit NAND Flash memory
| FMC signal name | I/O | Function |
|---|---|---|
| A[17] | O | NAND Flash address latch enable (ALE) signal |
| A[16] | O | NAND Flash command latch enable (CLE) signal |
| D[15:0] | I/O | 16-bit multiplexed, bidirectional address/data bus |
| NCE | O | Chip select |
| NOE(= NRE) | O | Output enable (memory signal name: read enable, NRE) |
| NWE | O | Write enable |
| NWAIT/INT | I | NAND Flash ready/busy input signal to the FMC |
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.
Table 88 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash controller are shown in gray.
| (omitted) |
The NAND Flash memory bank is managed through a set of registers:
Each timing configuration register contains three parameters used to define number of HCLK cycles for the three phases of any NAND Flash access, plus one parameter that defines the timing for starting driving the data bus when a write access is performed. Figure 53 shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar.
| (omitted) |
The command latch enable (CLE) and address latch enable (ALE) signals of the NAND Flash memory device are driven by address signals from the FMC controller. This means that to send a command or an address to the NAND Flash memory, the CPU has to perform a write to a specific address in its memory space.
A typical page read operation from the NAND Flash device requires the following steps:
to implement the prewait functionality needed by some NAND Flash memories (see details in Section 13.6.5: NAND Flash prewait functionality).
Some NAND Flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see Figure 54).
| (omitted) |
When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the tWB timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the tWB timing, and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND Flash read and write accesses, except when writing the last address byte to the NAND Flash device, where the CPU must write to the attribute memory space.
The FMC NAND Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the ECC by software.
These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a consequence, no hardware ECC computation is available for memories connected to Bank 4.
The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the NAND Flash memory. It is based on the Hamming coding algorithm and consists in calculating the row and column parity.
The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and NWE) each time the NAND Flash memory bank is active.
The ECC operates as follows:
Once the desired number of bytes has been read/written from/to the NAND Flash memory by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value. Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR registers.
To perform an ECC computation:
NAND Flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ECCPS[2:0] | TAR3 |
TAR[2:0] | TCLR[3:0] | Res. | Res. | ECCEN | PWID[1:0] | PTYP | PBKEN | PWAITEN | Res. |
||||||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bits 31:20 | Reserved, must be kept at reset value. |
| Bits 19:17 | ECCPS[2:0]: ECC page size. |
|
Defines the page size for the extended ECC: |
|
| Bits 16:13 | TAR[3:0]: ALE to RE delay. |
|
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). SET is MEMSET or ATTSET according to the addressed space. |
|
| Bits 12:9 | TCLR[3:0]: CLE to RE delay. |
|
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
SET is MEMSET or ATTSET according to the addressed space.
|
|
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | ECCEN: ECC computation logic enable bit |
|
0: ECC logic is disabled and reset (default after reset), |
|
| Bits 5:4 | PWID[1:0]: Data bus width. |
|
Defines the external memory device width. |
|
| Bit 3 | PTYP: Memory type. |
|
Defines the type of device attached to the corresponding memory bank: |
|
| Bit 2 | PBKEN: NAND Flash memory bank enable bit. |
|
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus |
|
| Bit 1 | PWAITEN: Wait feature enable bit. |
|
Enables the Wait feature for the NAND Flash memory bank: |
|
| Bit 0 | Reserved, must be kept at reset value. |
FIFO status and interrupt register (FMC_SR)
Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FEMPT | IFEN | ILEN | IREN | IFS | ILS | IRS |
| r | rw | rw | rw | rw | rw | rw |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | FEMPT: FIFO empty. |
|
Read-only bit that provides the status of the FIFO |
|
| Bit 5 | IFEN: Interrupt falling edge detection enable bit |
|
0: Interrupt falling edge detection request disabled |
|
| Bit 4 | ILEN: Interrupt high-level detection enable bit |
|
0: Interrupt high-level detection request disabled |
|
| Bit 3 | IREN: Interrupt rising edge detection enable bit |
|
0: Interrupt rising edge detection request disabled |
|
| Bit 2 | IFS: Interrupt falling edge status |
|
The flag is set by hardware and reset by software.
If this bit is written by software to 1 it will be set.
|
|
| Bit 1 | ILS: Interrupt high-level status |
|
The flag is set by hardware and reset by software. |
|
| Bit 0 | IRS: Interrupt rising edge status |
|
The flag is set by hardware and reset by software. If this bit is written by software to 1 it will be set. |
Common memory space timing register 2..4 (FMC_PMEM)
Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MEMHIZ[7:0] | MEMHOLD[7:0] |
MEMWAIT[7:0] | MEMSET[7:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | MEMHIZ[7:0]: Common memory x data bus Hi-Z time |
|
Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: |
|
| Bits 23:16 | MEMHOLD[7:0]: Common memory hold time |
|
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: |
|
| Bits 15:8 | MEMWAIT[7:0]: Common memory wait time |
|
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: |
|
| Bits 7:0 | MEMSET[7:0]: Common memory x setup time |
|
Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: |
Attribute memory space timing registers (FMC_PATT)
Address offset: 0x8C
Reset value: 0xFCFC FCFC
The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 13.6.5: NAND Flash prewait functionality).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ATTHIZ[7:0] | ATTHOLD[7:0] |
ATTWAIT[7:0] | ATTSET[7:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | ATTHIZ[7:0]: Attribute memory data bus Hi-Z time |
|
Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: |
|
| Bits 23:16 | ATTHOLD[7:0]: Attribute memory hold time |
|
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: |
|
| Bits 15:8 | ATTWAIT[7:0]: Attribute memory wait time |
|
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: |
|
| Bits 7:0 | ATTSET[7:0]: Attribute memory setup time |
|
Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: |
ECC result registers (FMC_ECCR)
Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 13.6.6: Computation of
the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ECC[31:16] |
ECC[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | ECC[31:0]: ECC result |
|
This field contains the value computed by the ECC computation logic. Table 89 describes the contents of these bit fields. |
| ECCPS[2:0] | Page size in bytes | ECC bits |
|---|---|---|
| 000 | 256 | ECC[21:0] |
| 001 | 512 | ECC[23:0] |
| 010 | 1024 | ECC[25:0] |
| 011 | 2048 | ECC[27:0] |
| 100 | 4096 | ECC[29:0] |
| 101 | 8192 | ECC[31:0] |
The main features of the SDRAM controller are the following:
At startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the external SDRAM devices must configured by the user application. The SDRAM controller I/O pins which are not used by the application, can be used for other purposes.
| SDRAM signal | I/O type | Description | Alternate function |
|---|---|---|---|
| SDCLK | O | SDRAM clock | - |
| SDCKE[1:0] | O | SDCKE0: SDRAM Bank 1 Clock Enable SDCKE1: SDRAM Bank 2 Clock Enable | - |
| SDNE[1:0] | O | SDNE0: SDRAM Bank 1 Chip Enable SDNE1: SDRAM Bank 2 Chip Enable | - |
| A[12:0] | O | Address | FMC_A[12:0] |
| D[31:0] | I/O | Bidirectional data bus | FMC_D[31:0] |
| BA[1:0] | O | Bank Address | FMC_A[15:14] |
| NRAS | O | Row Address Strobe | - |
| NCAS | O | Column Address Strobe | - |
| SDNWE | O | Write Enable | - |
| NBL[3:0] | O | Output Byte Mask for write accesses (memory signal name: DQM[3:0] | FMC_NBL[3:0] |
All SDRAM controller outputs (signals, address and data) change on the falling edge of the memory clock (FMC_SDCLK).
SDRAM initialization
The initialization sequence is managed by software. If the two banks are used, the initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:
Configure the MRD field according to the SDRAM device, set the MODE bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register to issue a "Load Mode Register" command in order to program the SDRAM device.
In particular:
If the Mode Register is not the same for both SDRAM banks, this step has to be repeated twice, once for each bank, and the Target Bank bits set accordingly.
Program the refresh rate in the FMC_SDRTR register
The refresh rate corresponds to the delay between refresh cycles. Its value must be adapted to SDRAM devices.
At this stage the SDRAM device is ready to accept commands. If a system reset occurs during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device. Therefor the SDRAM device must be first reinitialized after reset before issuing any new access by the NOR Flash/PSRAM/SRAM or NAND Flash controller.
Note: If two SDRAM devices are connected to the FMC, all the accesses performed at the same
time to both devices by the Command Mode register (Load Mode Register command) are
issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS
timings) in the FMC_SDTR1 register.
SDRAM controller write cycle
The SDRAM controller accepts single and burst write requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row for each bank to be able to perform consecutive write accesses to different banks (Multibank ping-pong access).
Before performing any write access, the SDRAM bank write protection must be disabled by clearing the WP bit in the FMC_SDCRx register.
| (omitted) |
The SDRAM controller always checks the next access.
SDRAM controller read cycle
The SDRAM controller accepts single and burst read requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row in each bank to be able to perform consecutive read accesses in different banks (Multibank ping-pong access).
| (omitted) |
The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance during the CAS latency period and the RPIPE delay following the below formula. The RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read access.
Number for anticipated data = CAS latency + 1 + (RPIPE delay)/2
Examples:
The read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the column address, 2 bits to select the internal bank and the active row, and 1 bit to select the SDRAM device
When the end of the row is reached in advance during an AHB burst read, the data read in advance (not committed) are not stored in the read FIFO. For single read access, data are correctly stored in the FIFO.
Each time a read request occurs, the SDRAM controller checks:
| (omitted) |
During a write access or a Precharge command, the read FIFO is flushed and ready to be filled with new data.
After the first read request, if the current access was not performed to a row boundary, the SDRAM controller anticipates the next read access during the CAS latency period and the RPIPE delay (if configured). This is done by incrementing the memory address. The following condition must be met:
The address management depends on the next AHB request:
Next AHB request is sequential (AHB Burst)
In this case, the SDRAM controller increments the address.
If the RURST is reset, the read FIFO is not used.
Row and bank boundary management
When a read or write access crosses a row boundary, if the next read or write access is sequential and the current access was performed to a row boundary, the SDRAM controller executes the following operations:
At a row boundary, the automatic activation of the next row is supported for all columns and data bus width configurations.
If necessary, the SDRAM controller inserts additional clock cycles between the following commands:
These parameters are defined into the FMC_SDTRx register.
Refer to Figure 55 and Figure 56 for read and burst write access crossing a row boundary.
| (omitted) |
| (omitted) |
If the next access is sequential and the current access crosses a bank boundary, the SDRAM controller activates the first row in the next bank and initiates a new read/write command. Two cases are possible:
SDRAM controller refresh cycle
The Auto-refresh command is used to refresh the SDRAM device content. The SDRAM controller periodically issues auto-refresh commands. An internal counter is loaded with the COUNT value in the register FMC_SDRTR. This value defines the number of memory clock cycles between the refresh cycles (refresh rate). When this counter reaches zero, an internal pulse is generated.
If a memory access is ongoing, the auto-refresh request is delayed. However, if the memory access and the auto-refresh requests are generated simultaneously, the auto-refresh request takes precedence.
If the memory access occurs during an auto-refresh operation, the request is buffered and processed when the auto-refresh is complete.
If a new auto-refresh request occurs while the previous one was not served, the RE (Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been enabled (REIE = ‘1’).
If SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates a PALL (Precharge ALL) command before the auto-refresh.
If the Auto-refresh command is generated by the FMC_SDCMR Command Mode register (Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.
Two low-power modes are available:
Self-refresh mode
The auto-refresh cycles are performed by the SDRAM device itself to retain data without external clocking.
Power-down mode
The auto-refresh cycles are performed by the SDRAM controller.
Self-refresh mode
This mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register.
The SDRAM clock stops running after a TRAS delay and the internal refresh timer stops counting only if one of the following conditions is met:
Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL command.
If the Write data FIFO is not empty, all data are sent to the memory before activating the Self-refresh mode and the BUSY status flag remains set.
In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which remains low.
The SDRAM device must remain in Self-refresh mode for a minimum period of time of TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To guarantee this minimum period, the BUSY status flag remains high after the Self-refresh activation during a TRAS delay.
As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of commands to exit from Self-refresh mode. After the memory access, the selected device remains in Normal mode.
To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.
| (omitted) |
Power-down mode
This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register.
| (omitted) |
If the Write data FIFO is not empty, all data are sent to the memory before activating the Power-down mode.
As soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down mode. After the memory access, the selected SDRAM device remains in Normal mode.
During Power-down mode, all SDRAM device input and output buffers are deactivated except for the SDCKE which remains low.
The SDRAM device cannot remain in Power-down mode longer than the refresh period and cannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries out the refresh operation by executing the operations below:
To exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.
SDRAM Control registers 1,2 (FMC_SDCR1,2)
Address offset: 0x140+ 4* (x – 1), x = 1,2
Reset value: 0x0000 02D0
This register contains the control parameters for each SDRAM memory bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | RPIPE[1:0] | RBURST | SDCLK | WP | CAS | NB | MWID | NR | NC |
||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bits 14:13 | RPIPE[1:0]: Read pipe |
|
These bits define the delay, in HCLK clock cycles, for reading data after CAS latency.
The corresponding bits in the FMC_SDCR2 register is read only.
|
|
| Bit 12 | RBURST: Burst read |
|
This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO.
The corresponding bit in the FMC_SDCR2 register is don’t care.
|
|
| Bits 11:10 | SDCLK[1:0]: SDRAM clock configuration |
|
These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized.
The corresponding bits in the FMC_SDCR2 register are don’t care.
|
|
| Bit 9 | WP: Write protection |
|
This bit enables write mode access to the SDRAM bank. |
|
| Bits 8:7 | CAS[1:0]: CAS Latency |
|
This bits sets the SDRAM CAS latency in number of memory clock cycles |
|
| Bit 6 | NB: Number of internal banks |
|
This bit sets the number of internal banks. |
|
| Bits 5:4 | MWID[1:0]: Memory data bus width. |
|
These bits define the memory device width. |
|
| Bits 3:2 | NR[1:0]: Number of row address bits |
|
These bits define the number of bits of a row address. |
|
| Bits 1:0 | NC[1:0]: Number of column address bits |
|
These bits define the number of bits of a column address. Before modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user
SDRAM Timing registers 1,2 (FMC_SDTR1,2)
Address offset: 0x148 + 4 * (x – 1), x = 1,2 Reset value: 0x0FFF FFFF This register contains the timing parameters of each SDRAM bank |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | TRCD | TRP | TWR |
TRC | TRAS | TXSR | TMRD |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:24 | TRCD[3:0]: Row to column delay |
|
These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. |
|
| Bits 23:20 | TRP[3:0]: Row precharge delay |
|
These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device.
The corresponding bits in the FMC_SDTR2 register are don’t care.
|
|
| Bits 19:16 | TWR[3:0]: Recovery delay |
|
These bits define the delay between a Write and a Precharge command in number of memory clock cycles.
TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed |
|
| Bits 15:12 | TRC[3:0]: Row cycle delay |
|
These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM The corresponding bits in the FMC_SDTR2 register are don’t care. |
|
| Bits 11:8 | TRAS[3:0]: Self refresh time |
|
These bits define the minimum Self-refresh period in number of memory clock cycles. |
|
| Bits 7:4 | TXSR[3:0]: Exit Self-refresh delay |
|
These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed |
|
| Bits 3:0 | TMRD[3:0]: Load Mode Register to Active |
|
These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles.
If two SDRAM devices are connected, all the accesses performed simultaneously to both The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM
SDRAM Command Mode register (FMC_SDCMR)
Address offset: 0x150 Reset value: 0x0000 0000 This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks. |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MRD |
MRD | NRFS | CTB1 | CTB2 | MODE |
||||||||||||||||
| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bits 21:9 | MRD[12:0]: Mode Register definition |
|
This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. |
|
| Bits 8:5 | NRFS[3:0]: Number of Auto-refresh |
|
These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. |
|
| Bit 4 | CTB1: Command Target Bank 1 |
|
This bit indicates whether the command will be issued to SDRAM Bank 1 or not. |
|
| Bit 3 | CTB2: Command Target Bank 2 |
|
This bit indicates whether the command will be issued to SDRAM Bank 2 or not. |
|
| Bits 2:0 | MODE[2:0]: Command mode |
|
These bits define the command issued to the SDRAM device. When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be If two SDRAM banks are used, the Auto-refresh and PALL command must be issued If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the
SDRAM Refresh Timer register (FMC_SDRTR)
Address offset:0x154 Reset value: 0x0000 0000 This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value. Refresh rate= ( COUNT+ 1 ) × SDRAM clock frequency COUNT= ( SDRAM refresh period⁄ Number of rows ) – 20
Example
Refresh rate= 64 ms⁄ ( 8196rows ) = 7.81μs where 64 ms is the SDRAM refresh period. 7.81μs× 60MHz = 468.6 The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of ‘0000111000000’ (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles. |
As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is ’0’, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.
Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.
If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.
This register is common to SDRAM bank 1 and bank 2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | REIE | COUNT | CRE |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w |
|||||||||||||||||
| Bit 31 | 15 Reserved, must be kept at reset value. |
| Bit 14 | REIE: RES Interrupt Enable |
|
0: Interrupt is disabled |
|
| Bits 13:1 | COUNT[12:0]: Refresh Timer Count |
|
This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). |
|
| Bit 0 | CRE: Clear Refresh error flag |
|
This bit is used to clear the Refresh Error Flag (RE) in the Status Register. The programmed COUNT value must not be equal to the sum of the following timings:
SDRAM Status register (FMC_SDSR)
Address offset: 0x158 Reset value: 0x0000 0000 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | MODES2 | MODES1 | RE |
||
| r | r | r | r | r | r |
||||||||||||||||||||||||||
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 5 | BUSY: Busy status |
|
This bit defines the status of the SDRAM controller after a Command Mode request |
|
| Bits 4:3 | MODES2[1:0]: Status Mode for Bank 2 |
|
This bit defines the Status Mode of SDRAM Bank 2. |
|
| Bits 2:1 | MODES1[1:0]: Status Mode for Bank 1 |
|
This bit defines the Status Mode of SDRAM Bank 1. |
|
| Bit 0 | RE: Refresh error flag |
|
0: No refresh error has been detected |
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
FMC_BCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WFDIS | CCLKEN | CBURSTRW | CPSIZE [2:0] |
ASYNCWAIT | EXTMOD | WAITEN | WREN | WAITCFG | Res. | WAITPOL | BURSTEN | Res. | FACCEN | MWID [1:0] |
MTYP [1:0] |
MUXEN | MBKEN | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
|||||||||||||
| 0x08 |
FMC_BCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CBURSTRW | CPSIZE [2:0] |
ASYNCWAIT | EXTMOD | WAITEN | WREN | WAITCFG | Res. | WAITPOL | BURSTEN | Res. | FACCEN | MWID [1:0] |
MTYP [1:0] |
MUXEN | MBKEN | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
|||||||||||||||
| 0x10 |
FMC_BCR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CBURSTRW | CPSIZE [2:0] |
ASYNCWAIT | EXTMOD | WAITEN | WREN | WAITCFG | Res. | WAITPOL | BURSTEN | Res. | FACCEN | MWID [1:0] |
MTYP [1:0] |
MUXEN | MBKEN | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
|||||||||||||||
| 0x18 |
FMC_BCR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CBURSTRW | CPSIZE [2:0] |
ASYNCWAIT | EXTMOD | WAITEN | WREN | WAITCFG | Res. | WAITPOL | BURSTEN | Res. | FACCEN | MWID [1:0] |
MTYP [1:0] |
MUXEN | MBKEN | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
|||||||||||||||
| 0x04 |
FMC_BTR1
|
Res. | Res. | ACCMOD[1:0] | DATLAT[3:0] | CLKDIV[3:0] | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||
| 0x0C |
FMC_BTR2
|
Res. | Res. | ACCMOD[1:0] | DATLAT[3:0] | CLKDIV[3:0] | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||
| 0x14 |
FMC_BTR3
|
Res. | Res. | ACCMOD[1:0] | DATLAT[3:0] | CLKDIV[3:0] | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||
| 0x1C |
FMC_BTR4
|
Res. | Res. | ACCMOD[1:0] | DATLAT[3:0] | CLKDIV[3:0] | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||
| 0x104 |
FMC_BWTR1
|
Res. | Res. | ACCMOD[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||
| 0x10C |
FMC_BWTR2
|
Res. | Res. | ACCMOD[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||||||||||
| 0x114 |
FMC_BWTR3
|
Res. | Res. | ACCMOD[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||
| 0x11C |
FMC_BWTR4
|
Res. | Res. | ACCMOD[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSTURN[3:0] | DATAST[7:0] | ADDHLD[3:0] | ADDSET[3:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||
| 0x80 |
FMC_PCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ECCPS [2:0] |
TAR[3:0] | TCLR[3:0] |
Res. | Res. | ECCEN | PWID [1:0] |
PTYP | PBKEN | PWAITEN | Res. | |||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
||||||||||||||||
| 0x84 |
FMC_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FEMPT | IFEN | ILEN | IREN | IFS | ILS | IRS |
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x88 | FMC_PMEM | MEMHIZx[7:0] | MEMHOLDx[7:0] | MEMWAITx[7:0] | MEMSETx[7:0] |
||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
|
| 0x8C | FMC_PATT | ATTHIZ[7:0] | ATTHOLD[7:0] | ATTWAIT[7:0] | ATTSET[7:0] |
||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
|
| 0x94 | FMC_ECCR | ECCx[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x140 |
FMC_SDCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RPIPE[ 1:0] |
RBURST | SDCLK [1:0] |
WP | CAS [1:0] |
NB | MWID [1:0] |
NR[1:0] | NC |
||||||
| Reset value | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x144 |
FMC_SDCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RBURST | SDCLK [1:0] |
WP | CAS [1:0] |
NB | MWID [1:0] |
NR[1:0] | NC |
|||||
| Reset value | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x148 |
FMC_SDTR1
|
Res. | Res. | Res. | Res. | TRCD[3:0] | TRP[3:0] | TWR[3:0] | TRC[3:0] | TRAS[3:0] | TXSR[3:0] | TMRD[3:0] |
|||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||
| 0x14C |
FMC_SDTR2
|
Res. | Res. | Res. | Res. | TRCD[3:0] | TRP[3:0] | TWR[3:0] | TRC[3:0] | TRAS[3:0] | TXSR[3:0] | TMRD[3:0] |
|||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||
| 0x150 |
FMC_SDCMR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MRD[12:0] | NRFS[3:0] |
CTB1 | CTB2 | MODE[2:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x154 |
FMC_SDRTR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | REIE | COUNT[12:0] |
CRE | ||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x158 |
FMC_SDSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | MODES2[1:0] | MODES1[1:0] | Res. | ||
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes:
Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI Flash memories are accessed simultaneously.
| (omitted) |
| (omitted) |
Table 92 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode.
| Signal name | Signal type | Description |
|---|---|---|
| CLK | Digital output | Clock to FLASH 1 and FLASH 2 |
| BK1_IO0/SO | Digital input/output | Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 1 |
| BK1_IO1/SI | Digital input/output | Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 1 |
| BK1_IO2 | Digital input/output | Bidirectional IO in quad mode, for FLASH 1 |
| BK1_IO3 | Digital input/output | Bidirectional IO in quad mode, for FLASH 1 |
| BK2_IO0/SO | Digital input/output | Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 2 |
| BK2_IO1/SI | Digital input/output | Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 2 |
| BK2_IO2 | Digital input/output | Bidirectional IO in quad mode, for FLASH 2 |
| BK2_IO3 | Digital input/output | Bidirectional IO in quad mode, for FLASH 2 |
| BK1_nCS | Digital output |
Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI is always used in dual-flash mode. |
| BK2_nCS | Digital output |
Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI is always used in dual-flash mode. |
The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
nCS falls before the start of each command and rises again after each command finishes.
| (omitted) |
Instruction phase
During this phase, an 8-bit instruction, configured in INSTRUCTION field of QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation to be performed.
Though most Flash memories can receive instructions only one bit at a time from the IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register.
When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present.
Address phase
In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in memory-mapped mode the address is given directly via the AHB (from the Cortex® or from a DMA).
The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10] register.
When ADMODE = 00, the address phase is skipped, and the command sequence proceeds directly to the next phase, if any.
Alternate-bytes phase
In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register.
When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when dual-mode is used and only two cycles are used for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and 2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set to 0x8A (1000_1010).
Dummy-cycles phase
In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received, in order to allow the Flash memory the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles.
When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present.
The operating mode of the dummy-cycles phase is determined by DMODE.
In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory.
Data phase
During the data phase, any number of bytes can be sent to, or received from the Flash memory.
In indirect and automatic-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register.
In indirect write mode the data to be sent to the Flash memory must be written to the QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register.
In memory-mapped mode, the data which is read is sent back directly over the AHB to the Cortex or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register.
When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.
Single SPI mode
Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received from the Flash memory arrives via SI (whose I/O shared with IO1).
The different phases can each be configured separately to use this single bit mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.
In each phase which is configured in single mode:
This is the case even for the dummy phase if DMODE = 01.
Dual SPI mode
In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use dual SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.
In each phase which is configured in dual mode:
In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.
Quad SPI mode
In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals.
The different phases can each be configured separately to use quad SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.
In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at high-impedance (input) during the data phase for read operations, and outputs in all other cases.
In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while QUADSPI is active.
SDR mode
By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode.
In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK.
When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK.
DDR mode
When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data rate (DDR) mode.
In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of CLK.
The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s falling edge.
When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also send the data using both rising and falling CLK edges. When DDRM = 1, firmware must clear SSHIFT bit (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge).
| (omitted) |
Dual-flash mode
When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity.
Each of the Flash memories use the same CLK and optionally the same nCS signals, but each have separate IO0, IO1, IO2, and IO3 signals.
Dual-flash mode can be used in conjunction with single-bit, dual-bit, and quad-bit modes, as well as with either SDR or DDR mode.
The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component.
If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored in FLASH 1 and bytes at odd addresses are all stored in FLASH 2.
When reading the Flash memories status registers in dual-flash mode, twice as many bytes should be read compared to doing the same read in single-flash mode. This means that if each Flash memory gives 8 valid bits after the instruction for fetching the status register, then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI will receive one byte from each Flash memory. If each Flash memory gives a status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status bits of both Flash memories in dual-flash mode. The least-significant byte of the result (in the data register) is the least-significant byte of FLASH 1 status register, while the next byte is the least-significant byte of FLASH 2 status register. Then, the third byte of the data register is FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the Flash memories have 16-bit status registers).
An even number of bytes must always be accessed in dual-flash mode. For this reason, bit 0 of the data length field (QUADSPI_DLR[0]) is stuck at 1 when DRM = 1.
In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1 during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each Flash memory always receives the same instruction and the same address. Then, during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of FLASH 2.
When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals.
When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR).
When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR.
The number of bytes to be read/written is specified in the data length register (QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE (QUADSPI_CCR[25:24]) should be set to 00.
If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash memory), then in this special case the transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.
When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF
is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR.
Triggering the start of a command
Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately after:
Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start. If alternate bytes are required, they must be programmed before.
As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set.
FIFO and data management
In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI. FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in the FIFO.
In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set).
Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register.
FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF (FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting. In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold.
If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true (after enough data has been transferred by the CPU or DMA).
In indirect read mode, when the FIFO becomes full, the QUADSPI temporarily stops reading bytes from the Flash memory to avoid an overrun. Note that the reading of the Flash memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 28). Thus, when FTHRES ≥ 29, the application must take care to read enough bytes to assure that the QUADSPI starts retrieving data from the Flash memory again. Otherwise, the FTF flag stays at '0' as long as 28 < FLEVEL < FTHRES.
In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.
The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses.
The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] (QUADSPI_PSMAR), then there is a match for bit n.
If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits.
If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match on any of the unmasked bits.
An interrupt is called when SMF is set if SMIE = 1.
If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0).
The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read.
When configured in memory-mapped mode, the external SPI device is seen as an internal memory.
It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral.
No more than 256MB can addressed even if the Flash memory capacity is larger.
If an access is made to an address outside of the range defined by FSIZE but still within the 256MB range, then a bus error is given. The effect of this error depends on the bus master that attempted the access:
Byte, halfword, and word access types are all supported.
Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next microcontroller access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access will be completed faster since the value is already prefetched.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled.
The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI Flash memory.
The FSIZE[4:0] field defines the size of external memory using the following formula:
Number of bytes in Flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB.
If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.
When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default. If the Flash memory requires more time between commands, the chip select high time (CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high.
The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands (when nCS = 1).
By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal.
In case of external signal delays, it may be beneficial to sample the data later. Using the SSHIFT bit (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of a CLK cycle.
Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit is set.
The QUADSPI configuration is done in two phases:
Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect mode, status-polling mode, or memory-mapped mode.
QUADSPI IP configuration
The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data.
DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode.
The DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their respective enable bit can be also set during this phase.
FIFO level for either DMA request generation or interrupt generation is programmed in the FTHRES bits.
If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register.
Dual-flash mode can be activated by setting DFM to 1.
QUADSPI Flash memory configuration
The parameters related to the targeted external Flash memory are configured through the QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits, the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or Mode 3) in the MODE bit.
The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).
Indirect mode procedure
When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory.
When the QUADSPI is used in indirect mode, the frames are constructed in the following way:
When writing the control register (QUADSPI_CR) the user specifies the following settings:
When writing the communication configuration register (QUADSPI_CCR) the user specifies the following parameters:
If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01).
When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR.
In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR.
Status flag polling mode
The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to
The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it will be ignored and only 4 bytes will be read.
The periodicity is specified in the QUADSPI_PISR register.
Once the status data has been retrieved, it can internally be processed i order to:
The received value can be masked with the value stored in the QUADSPI_PSMKR and ORed or ANDed with the value stored in the QUADSPI_PSMAR.
In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set.
In any case, the latest retrieved value is available in the QUADSPI_DR.
Memory-mapped mode
In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. Only read operations are allowed to the external Flash memory in this mode.
Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR register.
The programmed instruction and frame is sent when a master is accessing the memory mapped space.
The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to QUADSPI_DR in this mode returns zero.
The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode.
Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit (QUADSPI_CCR[28]).
SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR.
SIOO has no effect when IMODE = 00 (no instruction).
An error can be generated in the following case:
Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR.
In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty.
In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort.
After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort.
Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO is flushed.
Note: Some Flash memories might misbehave if a write operation to a status registers is aborted.
By default, nCS is high, deselecting the external Flash memory. nCS falls before an operation begins and rises as soon as it finishes.
When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 66.
| (omitted) |
When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 67.
| (omitted) |
When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 68. Because DDR operations must finish with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK cycle afterwards.
| (omitted) |
When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure 69.
| (omitted) |
When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2 may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions.
An interrupt can be produced on the following events:
Separate interrupt enable bits are available for flexibility.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Timeout | TOF | TOIE |
| Status match | SMF | SMIE |
| FIFO threshold | FTF | FTIE |
| Transfer complete | TCF | TCIE |
| Transfer error | TEF | TEIE |
Address offset: 0x0000
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRESCALER[7:0] | PMM | APMS | Res. | TOIE | SMIE | FTIE | TCIE | TEIE |
Res. | Res. | Res. | FTHRES[4:0] | FSEL | DFM | Res. | SSHIFT | TCEN | DMAEN | ABORT | EN |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
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| Bits 31:24 | PRESCALER[7:0]: Clock prescaler |
|
This field defines the scaler factor for generating CLK based on the AHB clock (value+1). |
|
| Bit 23 | PMM: Polling match mode |
|
This bit indicates which method should be used for determining a “match” during automatic polling mode. |
|
| Bit 22 | APMS: Automatic poll mode stop |
|
This bit determines if automatic polling is stopped after a match. |
|
| Bit 21 | Reserved, must be kept at reset value. |
| Bit 20 | TOIE: TimeOut interrupt enable |
|
This bit enables the TimeOut interrupt. |
|
| Bit 19 | SMIE: Status match interrupt enable |
|
This bit enables the status match interrupt. |
|
| Bit 18 | FTIE: FIFO threshold interrupt enable |
|
This bit enables the FIFO threshold interrupt. |
|
| Bit 17 | TCIE: Transfer complete interrupt enable |
|
This bit enables the transfer complete interrupt. |
|
| Bit 16 | TEIE: Transfer error interrupt enable |
|
This bit enables the transfer error interrupt. |
|
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:8 | FTHRES[4:0] FIFO threshold level |
|
Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. |
|
| Bit 7 | FSEL: Flash memory selection |
|
This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). |
|
| Bit 6 | DFM: Dual-flash mode |
|
This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | SSHIFT: Sample shift |
|
By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. |
|
| Bit 3 | TCEN: Timeout counter enable |
|
This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). |
|
| Bit 2 | DMAEN: DMA enable |
|
In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set. |
|
| Bit 1 | ABORT: Abort request |
|
This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. |
|
| Bit 0 | EN: Enable |
|
Enable the QUADSPI. |
Address offset: 0x0004
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSIZE[4:0] |
Res. | Res. | Res. | Res. | Res. | CSHT[2:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CK MODE |
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| rw | rw | rw | rw | rw |
rw | rw | rw | rw |
|||||||||||||||||||||||
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bits 20:16 | FSIZE[4:0]: Flash memory size |
|
This field defines the size of external memory using the following formula: |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:8 | CSHT[2:0]: Chip select high time |
|
CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | CKMODE: Mode 0 / mode 3 |
|
This bit indicates the level that CLK takes between commands (when nCS = 1). |
Address offset: 0x0008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | FLEVEL[5:0] | Res. | Res. | BUSY | TOF | SMF | FTF | TCF | TEF |
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| r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:8 | FLEVEL[5:0]: FIFO level |
|
This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero. |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bit 5 | BUSY: Busy |
|
This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. |
|
| Bit 4 | TOF: Timeout flag |
|
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. |
|
| Bit 3 | SMF: Status match flag |
|
This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF. |
|
| Bit 2 | FTF: FIFO threshold flag |
|
In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. |
|
| Bit 1 | TCF: Transfer complete flag |
|
This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. |
|
| Bit 0 | TEF: Transfer error flag |
|
This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. |
Address offset: 0x000C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CTOF | CSMF | Res. | CTCF | CTEF |
| w | w | w | w |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | CTOF: Clear timeout flag |
|
Writing 1 clears the TOF flag in the QUADSPI_SR register |
|
| Bit 3 | CSMF: Clear status match flag |
|
Writing 1 clears the SMF flag in the QUADSPI_SR register |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | CTCF: Clear transfer complete flag |
|
Writing 1 clears the TCF flag in the QUADSPI_SR register |
|
| Bit 0 | CTEF: Clear transfer error flag |
|
Writing 1 clears the TEF flag in the QUADSPI_SR register |
Address offset: 0x0010
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DL[31:16] |
DL[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DL[31:0]: Data length |
|
Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. |
Address offset: 0x0014
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DDRM | DHHC | Res. | SIOO | FMODE[1:0] | DMODE[1:0] | Res. | DCYC[4:0] | ABSIZE[1:0] |
ABMODE[1:0] | ADSIZE[1:0] | ADMODE[1:0] | IMODE[1:0] | INSTRUCTION[7:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bit 31 | DDRM: Double data rate mode |
|
This bit sets the DDR mode for the address, alternate byte and data phase: |
|
| Bit 30 | DHHC: DDR hold |
|
Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: |
|
| Bit 29 | Reserved, must be kept at reset value. |
| Bit 28 | SIOO: Send instruction only once mode |
|
See Section 14.3.12: Sending the instruction only once on page 421. This bit has no effect when IMODE = 00. |
|
| Bits 27:26 | FMODE[1:0]: Functional mode |
|
This field defines the QUADSPI functional mode of operation. |
|
| Bits 25:24 | DMODE[1:0]: Data mode |
|
This field defines the data phase’s mode of operation: |
|
| Bit 23 | Reserved, must be kept at reset value. |
| Bits 22:18 | DCYC[4:0]: Number of dummy cycles |
|
This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). |
|
| Bits 17:16 | ABSIZE[1:0]: Alternate bytes size |
|
This bit defines alternate bytes size: |
|
| Bits 15:14 | ABMODE[1:0]: Alternate bytes mode |
|
This field defines the alternate-bytes phase mode of operation: |
|
| Bits 13:12 | ADSIZE[1:0]: Address size |
|
This bit defines address size: |
|
| Bits 11:10 | ADMODE[1:0]: Address mode |
|
This field defines the address phase mode of operation: |
|
| Bits 9:8 | IMODE[1:0]: Instruction mode |
|
This field defines the instruction phase mode of operation: |
|
| Bits 7:0 | INSTRUCTION[7:0]: Instruction |
|
Instruction to be send to the external SPI device. |
Address offset: 0x0018
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDRESS[31:16] |
ADDRESS[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | ADDRESS[31:0]: Address |
|
Address to be send to the external Flash memory |
Address offset: 0x001C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALTERNATE[31:16] |
ALTERNATE[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | ALTERNATE[31:0]: Alternate Bytes |
|
Optional data to be send to the external SPI device right after the address. |
Address offset: 0x0020
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA[31:16] |
DATA[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATA[31:0]: Data |
|
Data to be sent/received to/from the external SPI device. |
Address offset: 0x0024
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MASK[31:16] |
MASK[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MASK[31:0]: Status mask |
|
Mask to be applied to the status bytes received in polling mode. |
Address offset: 0x0028
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MATCH[31:16] |
MATCH[15:0] |
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| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MATCH[31:0]: Status match |
|
Value to be compared with the masked status register to get a match. |
Address offset: 0x002C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
INTERVAL[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | INTERVAL[15:0]: Polling interval |
|
Number of CLK cycles between to read during automatic polling phases. |
Address offset: 0x0030
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
TIMEOUT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | TIMEOUT[15:0]: Timeout period |
|
After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. |
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 |
QUADSPI_CR | PRESCALER[7:0] |
PMM | APMS | Res. | TOIE | SMIE | FTIE | TCIE | TEIE | Res. | Res. | Res. | FTHRES [4:0] |
FSEL | DFM | Res. | SSHIFT | TCEN | DMAEN | ABORT | EN | |||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x0004 |
QUADSPI_DCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSIZE[4:0] |
Res. | Res. | Res. | Res. | Res. | CSHT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKMODE | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x0008 |
QUADSPI_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLEVEL[6:0] |
Res. | Res. | BUS | TOF | SMF | FTF | TCF | TEF | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x000C |
QUADSPI_FCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CTOF | CSMF | Res. | CTCF | CTEF |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x0010 |
QUADSPI_DLR | DL[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0014 |
QUADSPI_CCR
|
DDRM | DHHC | Res. | SIOO | FMODE[1:0] | DMODE[1:0] | Res. | DCYC[4:0] |
ABSIZE[1:0] | ABMODE[1:0] | ADSIZE[1:0] | ADMODE[1:0] | IMODE[1:0] | INSTRUCTION[7:0] |
||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||
| 0x0018 |
QUADSPI_AR | ADDRESS[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x001C |
QUADSPI_ABR | ALTERNATE[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0020 |
QUADSPI_DR | DATA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0024 |
QUADSPI_ PSMKR |
MASK[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0028 |
QUADSPI_ PSMAR |
MATCH[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x002C |
QUADSPI_PIR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INTERVAL[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0030 |
QUADSPI_ LPTR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TIMEOUT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||
Refer to Section 2.2.2 for the register boundary addresses.
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the VBAT channel. The A/D conversion of the channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored into a left-or right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes beyond the user-defined, higher or lower thresholds.
Figure 70 shows the block diagram of the ADC.
Note: VREF–, if available (depending on package), must be tied to VSSA.
Figure 70 shows a single ADC block diagram and Table 95 gives the ADC pin description.
| (omitted) |
| Name | Signal type | Remarks |
|---|---|---|
| VREF+ |
Input, analog reference positive |
The higher/positive reference voltage for the ADC, 1.8 V ≤ VREF+ ≤ VDDA |
| VDDA | Input, analog supply |
Analog power supply equal to VDD and 2.4 V ≤VDDA ≤VDD (3.6 V) for full speed 1.8 V ≤VDDA ≤VDD (3.6 V) for reduced speed |
| VREF– |
Input, analog reference negative |
The lower/negative reference voltage for the ADC, VREF– = VSSA |
| VSSA |
Input, analog supply ground | Ground for analog power supply equal to VSS |
| ADCx_IN[15:0] | Analog input signals | 16 analog input channels |
The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from the Power-down mode.
The conversion starts when either the SWSTART or the JSWSTART bit is set.
The user can stop conversion and put the ADC in power down mode by clearing the ADON bit. In this mode the ADC consumes almost no power (only a few µA).
ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described
in Figure 71, Figure 72 and Figure 73.
| (omitted) |
| (omitted) |
| (omitted) |
The ADC features two clock schemes:
Clock for the analog circuitry: ADCCLK
This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the maximum value of ADCCLK.
Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be enabled/disabled individually for each ADC through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).
There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, ADC_IN2, ADC_IN2, ADC_IN15.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Temperature sensor, VREFINT and VBAT internal channels
The temperature sensor is internally connected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed.
The internal reference voltage VREFINT is connected to ADC1_IN17.
The VBAT channel is connected to ADC1_IN18 channel. It can also be converted as an injected or regular channel.
In Single conversion mode the ADC does one conversion. This mode is started with the CONT bit at 0 by either:
Once the conversion of the selected channel is complete:
Then the ADC stops.
In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one. This mode is started with the CONT bit at 1 either by external trigger or by setting the SWSTRT bit in the ADC_CR2 register (for regular channels only).
After each conversion:
Note: Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection section)
.
As shown in Figure 74, the ADC needs a stabilization time of tSTAB before it starts converting accurately. After the start of the ADC conversion and after 15 clock cycles, the EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
| (omitted) |
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds before alignment.
Table 96 shows how the ADC_CR1 register should be configured to enable the analog watchdog on one or more channels.
| (omitted) |
| Channels guarded by the analog watchdog |
ADC_CR1 register control bits (x = don’t care) |
||
|---|---|---|---|
| AWDSGL bit | AWDEN bit | JAWDEN bit |
|
| None | x | 0 | 0 |
| All injected channels | 0 | 0 | 1 |
| All regular channels | 0 | 1 | 0 |
| All regular and injected channels | 0 | 1 | 1 |
| Single(1) injected channel | 1 | 0 | 1 |
| Single(1) regular channel | 1 | 1 | 0 |
| Single (1) regular or injected channel | 1 | 1 | 1 |
This mode is used to scan a group of analog channels.
The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR register (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion, the next channel in the group is converted automatically. If the CONT bit is set, regular channel conversion does not stop at the last selected channel in the group but continues again from the first selected channel.
If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data converted from the regular group of channels (stored in the ADC_DR register) to SRAM after each regular channel conversion.
The EOC bit is set in the ADC_SR register:
The data converted from an injected channel are always stored into the ADC_JDRx registers.
Triggered injection
To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.
Note: When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 30 ADC clock
cycles (that is two conversions with a sampling time of 3 clock periods), the minimum
interval between triggers must be 31 ADC clock cycles.
Auto-injection
If the JAUTO bit is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously.
| (omitted) |
Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.
Example:
Note: When a regular group is converted in discontinuous mode, no rollover occurs.
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the
1st subgroup.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and JEOC event generated
4th trigger: channel 1
Note: When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Discontinuous mode must not be set for regular and injected groups at the same time.
Discontinuous mode must be enabled only for the conversion of one group.
The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 77 and Figure 78.
The converted data value from the injected group of channels is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.
| (omitted) |
| (omitted) |
Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in Figure 79.
| (omitted) |
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion with the selected polarity. Table 97 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.
| Source | EXTEN[1:0] / JEXTEN[1:0] |
|---|---|
| Trigger detection disabled | 00 |
| Detection on the rising edge | 01 |
| Detection on the falling edge | 10 |
| Detection on both the rising and falling edges | 11 |
Note: The polarity of the external trigger can be changed on the fly.
The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible events can trigger conversion for the regular and injected groups.
Table 98 gives the possible external trigger for regular conversion.
| Source | Type | EXTSEL[3:0] |
|---|---|---|
| TIM1_CH1 |
Internal signal from on-chip timers |
0000 |
| TIM1_CH2 | 0001 |
|
| TIM1_CH3 | 0010 |
|
| TIM2_CH2 | 0011 |
|
| TIM5_TRGO | 0100 |
|
| TIM4_CH4 | 0101 |
|
| TIM3_CH4 | 0110 |
|
| TIM8_TRGO | 0111 |
|
| TIM8_TRGO(2) | 1000 |
|
| TIM1_TRGO | 1001 |
|
| TIM1_TRGO(2) | 1010 |
|
| TIM2_TRGO | 1011 |
|
| TIM4_TRGO | 1100 |
|
| TIM6_TRGO | 1101 |
|
| EXTI line11 | External pin | 1111 |
Table 99 gives the possible external trigger for injected conversion.
| Source | Connection type | JEXTSEL[3:0] |
|---|---|---|
| TIM1_TRGO | Internal signal from on-chip timers |
0000 |
| TIM1_CH4 | 0001 |
|
| TIM2_TRGO | 0010 |
|
| TIM2_CH1 | 0011 |
|
| TIM3_CH4 | 0100 |
|
| TIM4_TRGO | 0101 |
|
| TIM8_CH4 | Internal signal from on-chip timers |
0111 |
| TIM1_TRGO(2) | 1000 |
|
| TIM8_TRGO | 1001 |
|
| TIM8_TRGO(2) | 1010 |
|
| TIM3_CH3 | 1011 |
|
| TIM5_TRGO | 1100 |
|
| TIM3_CH1 | 1101 |
|
| TIM6_TRGO | 1110 |
Software source trigger events can be generated by setting SWSTART (for regular conversion) or JSWSTART (for injected conversion) in ADC_CR2.
A regular group conversion can be interrupted by an injected trigger.
Note: The trigger selection can be changed on the fly. However, when the selection changes,
there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.
This is to avoid spurious detection during transitions.
It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are used to select the number of bits available in the data register. The minimum conversion time for each resolution is then as follows:
Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each conversion of a regular channel, a DMA request is generated. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.
Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and DMA requests are no longer accepted. In this case, if a DMA request is made, the regular conversion in progress is aborted and further regular triggers are ignored. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to re-initialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location. Only then can the conversion be resumed and the data transfer, enabled again. Injected channel conversions are not impacted by overrun errors.
When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have been transferred, which means that all the data transferred to the RAM can be considered as valid.
At the end of the last DMA transfer (number of transfers configured in the DMA controller’s DMA_SxNTR register):
To recover the ADC from OVR state when the DMA is used, follow the steps below:
If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status bit to be set at the end of each conversion, and not only at the end of the sequence. When EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is complete, EOC is set and the ADC_DR register can be read. The overrun management is the same as when the DMA is used.
To recover the ADC from OVR state when the EOCS is set, follow the steps below:
It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this configuration, overrun detection is disabled.
In devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs) ADC modes can be used (see Figure 80).
In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the MULTI[4:0] bits in the ADC_CCR register.
Note: In multi ADC mode, when configuring conversion trigger by an external event, the
application must set trigger by the master only and disable trigger by slaves to prevent
spurious triggers that would start unwanted slave conversions.
The four possible modes below are implemented:
It is also possible to use the previous modes combined in the following ways:
Note: In multi ADC mode, the converted data can be read on the multi-mode data register
(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).
| (omitted) |
DMA requests in Multi ADC mode:
In Multi ADC mode the DMA may be configured to transfer converted data in three different modes. In all cases, the DMA streams to use are those connected to the ADC:
DMA mode 1: On each DMA request (one data item is available), a half-word representing an ADC-converted data item is transferred.
In Dual ADC mode, ADC1 data are transferred on the first request, ADC2 data are transferred on the second request and so on.
In Triple ADC mode, ADC1 data are transferred on the first request, ADC2 data are transferred on the second request and ADC3 data are transferred on the third request; the sequence is repeated. So the DMA first transfers ADC1 data followed by ADC2 data followed by ADC3 data and so on.
DMA mode 1 is used in regular simultaneous triple mode.
Example:
Regular simultaneous triple mode: 3 consecutive DMA requests are generated (one for each converted data item)
1st request: ADC_CDR[31:0] = ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]
4th request: ADC_CDR[31:0] = ADC1_DR[15:0]
DMA mode 2: On each DMA request (two data items are available) two half-words representing two ADC-converted data items are transferred as a word.
In Dual ADC mode, both ADC2 and ADC1 data are transferred on the first request (ADC2 data take the upper half-word and ADC1 data take the lower half-word) and so on.
In Triple ADC mode, three DMA requests are generated. On the first request, both ADC2 and ADC1 data are transferred (ADC2 data take the upper half-word and ADC1 data take the lower half-word). On the second request, both ADC1 and ADC3 data are transferred (ADC1 data take the upper half-word and ADC3 data take the lower half-word).On the third request, both ADC3 and ADC2 data are transferred (ADC3 data take the upper half-word and ADC2 data take the lower half-word) and so on.
DMA mode 2 is used in interleaved mode and in regular simultaneous mode (for Dual ADC mode only).
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are available:
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
Interleaved triple mode: a DMA request is generated each time 2 data items are available
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]
4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
DMA mode 3: This mode is similar to the DMA mode 2. The only differences are that the on each DMA request (two data items are available) two bytes representing two ADC converted data items are transferred as a half-word. The data transfer order is similar to that of the DMA mode 2.
DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
Interleaved triple mode: a DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = ADC1_DR[7:0] | ADC3_DR[15:0]
3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]
4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
Overrun detection: If an overrun is detected on one of the concerned ADCs (ADC1 and ADC2 in dual and triple modes, ADC3 in triple mode only), the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid. It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data.
This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of ADC1 (selected by the JEXTSEL[3:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.
Note: Do not convert the same channel on the two/three ADCs (no overlapping sampling times for
the two/three ADCs when converting the same channel).
In simultaneous mode, one must convert sequences with the same length or ensure that the
interval between triggers is longer than the longer of the 2 sequences (Dual ADC mode) /3
sequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart
while the ADC with the longest sequence is completing the previous conversions.
Regular conversions can be performed on one or all ADCs. In that case, they are
independent of each other and are interrupted when an injected event occurs. They are
resumed at the end of the injected conversion group.
Dual ADC mode
At the end of conversion event on ADC1 or ADC2:
| (omitted) |
Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
| (omitted) |
This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.
Note: Do not convert the same channel on the two/three ADCs (no overlapping sampling times for
the two/three ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the long conversion time of the 2 sequences
(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest
sequence may restart while the ADC with the longest sequence is completing the previous
conversions.
Injected conversions must be disabled.
Dual ADC mode
At the end of conversion event on ADC1 or ADC2:
| (omitted) |
Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
| (omitted) |
This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of ADC1.
Dual ADC mode
After an external trigger occurs:
The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on both ADCs, then 17 clock cycles will separate conversions on ADC1 and ADC2).
If the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs are continuously converted.
Note: If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
After an EOC interrupt is generated by ADC2 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA[1:0] bits in ADC_CCR are equal to 0b10). This request first transfers the ADC2 converted data stored in the upper half-word of the ADC_CDR 32-bit register into SRAM, then the ADC1 converted data stored in the register’s lower half-word into SRAM.
| (omitted) |
Triple ADC mode
After an external trigger occurs:
The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three ADCs, then 17 clock cycles will separate the conversions on ADC1, ADC2 and ADC3).
If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs are continuously converted.
Note: If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
In this mode a DMA request is generated each time 2 data items are available, (if the DMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the
first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM, then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM. The sequence is the following:
| (omitted) |
This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of ADC1.
Note: Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.
Dual ADC mode
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.
If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group.
| (omitted) |
If the injected discontinuous mode is enabled for both ADC1 and ADC2:
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.
If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts.
| (omitted) |
Triple ADC mode
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group have been converted.
If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group.
| (omitted) |
It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.
Note: In combined regular/injected simultaneous mode, one must convert sequences with the
same length or ensure that the interval between triggers is longer than the long conversion
time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the
ADC with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 90 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion.
The injected alternate conversion is immediately started after the injected event. If regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion.
Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the long
conversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode).
Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest
sequence is completing the previous conversions.
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
| (omitted) |
If a trigger occurs during an injected conversion that has interrupted a regular conversion, it is ignored. Figure 91 shows the behavior in this case (2nd trigger is ignored).
| (omitted) |
The temperature sensor can be used to measure the ambient temperature (TA) of the device.
Figure 92 shows the block diagram of the temperature sensor.
When not in use, the sensor can be put in power down mode.
Note: The TSVREFE bit must be set to enable the conversion of both internal channels: the
ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).
Main features
| (omitted) |
Reading the temperature
To use the sensor:
Temperature (in °C) = {(VSENSE – V25) / Avg_Slope} + 25
Where:
Refer to the datasheet electrical characteristics section for the actual values of V25 and Avg_Slope.
Note: The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.
The temperature sensor output voltage changes linearly with temperature. The offset of this linear function depends on each chip due to process variation (up to 45 °C from one chip to another).
The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. If accurate temperature reading is required, an external temperature sensor should be used.
The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider.
When the VBATE is set, the bridge is automatically enabled to connect:
Note: The VBAT and temperature sensor are connected to the same ADC internal channel
(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected
at a time. When both conversion are enabled simultaneously, only the VBAT conversion is
performed.
An interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. Separate interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with them:
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| End of conversion of a regular group | EOC | EOCIE |
| End of conversion of an injected group | JEOC | JEOCIE |
| Analog watchdog status bit is set | AWD | AWDIE |
| Overrun | OVR | OVRIE |
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OVR | STRT | JSTRT | JEOC | EOC | AWD |
| rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 |
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bit 5 | OVR: Overrun |
|
This bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It is cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1. |
|
| Bit 4 | STRT: Regular channel start flag |
|
This bit is set by hardware when regular channel conversion starts. It is cleared by software. |
|
| Bit 3 | JSTRT: Injected channel start flag |
|
This bit is set by hardware when injected group conversion starts. It is cleared by software. |
|
| Bit 2 | JEOC: Injected channel end of conversion |
|
This bit is set by hardware at the end of the conversion of all injected channels in the group. It is cleared by software. |
|
| Bit 1 | EOC: Regular channel end of conversion |
|
This bit is set by hardware at the end of the conversion of a regular group of channels. It is cleared by software or by reading the ADC_DR register. |
|
| Bit 0 | AWD: Analog watchdog flag |
|
This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | OVRIE | RES | AWDEN | JAWDEN | Res. | Res. | Res. | Res. | Res. | Res. |
DISCNUM[2:0] | JDISCEN | DISCEN | JAUTO | AWDSGL | SCAN | JEOCIE | AWDIE | EOCIE | AWDCH[4:0] |
|||||||
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | OVRIE: Overrun interrupt enable |
|
This bit is set and cleared by software to enable/disable the Overrun interrupt. 0: Overrun interrupt disabled |
|
| Bits 25:24 | RES[1:0]: Resolution |
|
These bits are written by software to select the resolution of the conversion. |
|
| Bit 23 | AWDEN: Analog watchdog enable on regular channels |
|
This bit is set and cleared by software. |
|
| Bit 22 | JAWDEN: Analog watchdog enable on injected channels |
|
This bit is set and cleared by software. |
|
| Bits 21:16 | Reserved, must be kept at reset value. |
| Bits 15:13 | DISCNUM[2:0]: Discontinuous mode channel count |
|
These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. |
|
| Bit 12 | JDISCEN: Discontinuous mode on injected channels |
|
This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. |
|
| Bit 11 | DISCEN: Discontinuous mode on regular channels |
|
This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. |
|
| Bit 10 | JAUTO: Automatic injected group conversion |
|
This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. |
|
| Bit 9 | AWDSGL: Enable the watchdog on a single channel in scan mode |
|
This bit is set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. |
|
| Bit 8 | SCAN: Scan mode |
|
This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
An EOC interrupt is generated if the EOCIE bit is set:
A JEOC interrupt is generated only on the end of conversion of the last channel if the |
|
| Bit 7 | JEOCIE: Interrupt enable for injected channels |
|
This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. |
|
| Bit 6 | AWDIE: Analog watchdog interrupt enable |
|
This bit is set and cleared by software to enable/disable the analog watchdog interrupt. |
|
| Bit 5 | EOCIE: Interrupt enable for EOC |
|
This bit is set and cleared by software to enable/disable the end of conversion interrupt. |
|
| Bits 4:0 | AWDCH[4:0]: Analog watchdog channel select bits |
|
These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. 00000: ADC analog input Channel0 00001: ADC analog input Channel1 |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | SWSTART | EXTEN | EXTSEL[3:0] | Res. | JSWSTART | JEXTEN | JEXTSEL[3:0] |
Res. | Res. | Res. | Res. | ALIGN | EOCS | DDS | DMA | Res. | Res. | Res. | Res. | Res. | Res. | CONT | ADON |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw |
||||||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | SWSTART: Start conversion of regular channels |
|
This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
This bit can be set only when ADON = 1 otherwise no conversion is launched.
|
|
| Bits 29:28 | EXTEN: External trigger enable for regular channels |
|
These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. |
|
| Bits 27:24 | EXTSEL[3:0]: External event select for regular group |
|
These bits select the external event used to trigger the start of conversion of a regular group: |
|
| Bit 23 | Reserved, must be kept at reset value. |
| Bit 22 | JSWSTART: Start conversion of injected channels |
|
This bit is set by software and cleared by hardware as soon as the conversion starts. This bit can be set only when ADON = 1 otherwise no conversion is launched. |
|
| Bits 21:20 | JEXTEN: External trigger enable for injected channels |
|
These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. |
|
| Bits 19:16 | JEXTSEL[3:0]: External event select for injected group |
|
These bits select the external event used to trigger the start of conversion of an injected group. 0000: Timer 1 TRGO 0001: Timer 1 CH4 0010: Timer 2 TRGO 0011: Timer 2 CH1 0100: Timer 3 CH4 0101: Timer4 TRGO 0110: Reserved 0111: Timer 8 CH4 1000: Timer 1 TRGO(2) 1001: Timer 8 TRGO 1010: Timer 8 TRGO(2) 1011: Timer 3 CH3 1100: Timer 5 TRGO 1101: Timer 3 CH1 1110: Timer 6 TRGO 1111: Reserved |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | ALIGN: Data alignment |
|
This bit is set and cleared by software. Refer to Figure 77 and Figure 78. |
|
| Bit 10 | EOCS: End of conversion selection |
|
This bit is set and cleared by software. |
|
| Bit 9 | DDS: DMA disable selection (for single ADC mode) |
|
This bit is set and cleared by software. |
|
| Bit 8 | DMA: Direct memory access mode (for single ADC mode) |
|
This bit is set and cleared by software. Refer to the DMA controller chapter for more details. |
|
| Bits 7:2 | Reserved, must be kept at reset value. |
| Bit 1 | CONT: Continuous conversion |
|
This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. |
|
| Bit 0 | ADON: A/D Converter ON / OFF |
|
This bit is set and cleared by software. |
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | SMP18[2:0] | SMP17[2:0] | SMP16[2:0] | SMP15[2:1] |
SMP15_0 | SMP14[2:0] | SMP13[2:0] | SMP12[2:0] | SMP11[2:0] | SMP10[2:0] |
|||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bit 31 | 27 Reserved, must be kept at reset value. |
| Bits 26:0 | SMPx[2:0]: Channel x sampling time selection |
|
These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. 000: 3 cycles 001: 15 cycles |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | SMP9[2:0] | SMP8[2:0] | SMP7[2:0] | SMP6[2:0] | SMP5[2:1] |
SMP5_0 | SMP4[2:0] | SMP3[2:0] | SMP2[2:0] | SMP1[2:0] | SMP0[2:0] |
|||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:0 | SMPx[2:0]: Channel x sampling time selection |
|
These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 3 cycles 001: 15 cycles |
Address offset: 0x14-0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | JOFFSETx[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | JOFFSETx[11:0]: Data offset for injected channel x |
|
These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers. |
Address offset: 0x24
Reset value: 0x0000 0FFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | HT[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | HT[11:0]: Analog watchdog higher threshold |
|
These bits are written by software to define the higher threshold for the analog watchdog. |
Note: The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
Address offset: 0x28
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | LT[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | LT[11:0]: Analog watchdog lower threshold |
|
These bits are written by software to define the lower threshold for the analog watchdog. |
Note: The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
Address offset: 0x2C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | L[3:0] | SQ16[4:1] |
SQ16_0 | SQ15[4:0] | SQ14[4:0] | SQ13[4:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:20 | L[3:0]: Regular channel sequence length |
|
These bits are written by software to define the total number of conversions in the regular channel conversion sequence. |
|
| Bits 19:15 | SQ16[4:0]: 16th conversion in regular sequence |
|
These bits are written by software with the channel number (0..18) assigned as the 16th in the conversion sequence. |
|
| Bits 14:10 | SQ15[4:0]: 15th conversion in regular sequence |
| Bits 9:5 | SQ14[4:0]: 14th conversion in regular sequence |
| Bits 4:0 | SQ13[4:0]: 13th conversion in regular sequence |
Address offset: 0x30
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | SQ12[4:0] | SQ11[4:0] | SQ10[4:1] |
SQ10_0 | SQ9[4:0] | SQ8[4:0] | SQ7[4:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:26 | SQ12[4:0]: 12th conversion in regular sequence |
|
These bits are written by software with the channel number (0..18) assigned as the 12th in the sequence to be converted. |
|
| Bits 24:20 | SQ11[4:0]: 11th conversion in regular sequence |
| Bits 19:15 | SQ10[4:0]: 10th conversion in regular sequence |
| Bits 14:10 | SQ9[4:0]: 9th conversion in regular sequence |
| Bits 9:5 | SQ8[4:0]: 8th conversion in regular sequence |
| Bits 4:0 | SQ7[4:0]: 7th conversion in regular sequence |
Address offset: 0x34
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | SQ6[4:0] | SQ5[4:0] | SQ4[4:1] |
SQ4_0 | SQ3[4:0] | SQ2[4:0] | SQ1[4:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:25 | SQ6[4:0]: 6th conversion in regular sequence |
|
These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted. |
|
| Bits 24:20 | SQ5[4:0]: 5th conversion in regular sequence |
| Bits 19:15 | SQ4[4:0]: 4th conversion in regular sequence |
| Bits 14:10 | SQ3[4:0]: 3rd conversion in regular sequence |
| Bits 9:5 | SQ2[4:0]: 2nd conversion in regular sequence |
| Bits 4:0 | SQ1[4:0]: 1st conversion in regular sequence |
Address offset: 0x38
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JL[1:0] | JSQ4[4:1] |
JSQ4[0] | JSQ3[4:0] | JSQ2[4:0] | JSQ1[4:0] |
||||||||||||||||
| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bits 21:20 | JL[1:0]: Injected sequence length |
|
These bits are written by software to define the total number of conversions in the injected channel conversion sequence. |
|
| Bits 19:15 | JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below) |
|
These bits are written by software with the channel number (0..18) assigned as the 4th in the sequence to be converted. |
|
| Bits 14:10 | JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below) |
| Bits 9:5 | JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below) |
| Bits 4:0 | JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below) |
Note: When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels
in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the
following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in
starting from JSQ3[4:0], and then JSQ4[4:0].
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0]
channel.
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
JDATA[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | JDATA[15:0]: Injected data |
|
These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 77 and Figure 78. |
Address offset: 0x4C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DATA[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | DATA[15:0]: Regular data |
|
These bits are read-only. They contain the conversion result from the regular channels. The data are left- or right-aligned as shown in Figure 77 and Figure 78. |
Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing it to 0 in the corresponding ADC_SR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OVR3 | STRT3 | JSTRT3 | JEOC 3 | EOC3 | AWD3 |
Res. | Res. |
OVR2 | STRT2 | JSTRT 2 |
JEOC2 | EOC2 | AWD2 |
Res. | Res. |
OVR1 | STRT1 | JSTRT1 | JEOC 1 | EOC1 | AWD1 |
| ADC3 |
ADC2 | ADC1 |
|||||||||||||||||||||||||||||
| r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | OVR3: Overrun flag of ADC3 |
|
This bit is a copy of the OVR bit in the ADC3_SR register. |
|
| Bit 20 | STRT3: Regular channel Start flag of ADC3 |
|
This bit is a copy of the STRT bit in the ADC3_SR register. |
|
| Bit 19 | JSTRT3: Injected channel Start flag of ADC3 |
|
This bit is a copy of the JSTRT bit in the ADC3_SR register. |
|
| Bit 18 | JEOC3: Injected channel end of conversion of ADC3 |
|
This bit is a copy of the JEOC bit in the ADC3_SR register. |
|
| Bit 17 | EOC3: End of conversion of ADC3 |
|
This bit is a copy of the EOC bit in the ADC3_SR register. |
|
| Bit 16 | AWD3: Analog watchdog flag of ADC3 |
|
This bit is a copy of the AWD bit in the ADC3_SR register. |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bit 13 | OVR2: Overrun flag of ADC2 |
|
This bit is a copy of the OVR bit in the ADC2_SR register. |
|
| Bit 12 | STRT2: Regular channel Start flag of ADC2 |
|
This bit is a copy of the STRT bit in the ADC2_SR register. |
|
| Bit 11 | JSTRT2: Injected channel Start flag of ADC2 |
|
This bit is a copy of the JSTRT bit in the ADC2_SR register. |
|
| Bit 10 | JEOC2: Injected channel end of conversion of ADC2 |
|
This bit is a copy of the JEOC bit in the ADC2_SR register. |
|
| Bit 9 | EOC2: End of conversion of ADC2 |
|
This bit is a copy of the EOC bit in the ADC2_SR register. |
|
| Bit 8 | AWD2: Analog watchdog flag of ADC2 |
|
This bit is a copy of the AWD bit in the ADC2_SR register. |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bit 5 | OVR1: Overrun flag of ADC1 |
|
This bit is a copy of the OVR bit in the ADC1_SR register. |
|
| Bit 4 | STRT1: Regular channel Start flag of ADC1 |
|
This bit is a copy of the STRT bit in the ADC1_SR register. |
|
| Bit 3 | JSTRT1: Injected channel Start flag of ADC1 |
|
This bit is a copy of the JSTRT bit in the ADC1_SR register. |
|
| Bit 2 | JEOC1: Injected channel end of conversion of ADC1 |
|
This bit is a copy of the JEOC bit in the ADC1_SR register. |
|
| Bit 1 | EOC1: End of conversion of ADC1 |
|
This bit is a copy of the EOC bit in the ADC1_SR register. |
|
| Bit 0 | AWD1: Analog watchdog flag of ADC1 |
|
This bit is a copy of the AWD bit in the ADC1_SR register. |
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSVREFE | VBATE | Res. | Res. | Res. | Res. | ADCPRE |
DMA[1:0] | DDS | Res. | DELAY[3:0] | Res. | Res. | Res. | MULTI[4:0] |
|||||||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bit 23 | TSVREFE: Temperature sensor and VREFINT enable |
|
This bit is set and cleared by software to enable/disable the temperature sensor and the VREFINT channel. VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT |
|
| Bit 22 | VBATE: VBAT enable |
|
This bit is set and cleared by software to enable/disable the VBAT channel. |
|
| Bits 21:18 | Reserved, must be kept at reset value. |
| Bits 17:16 | ADCPRE: ADC prescaler |
|
Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 |
|
| Bits 15:14 | DMA: Direct memory access mode for multi ADC mode |
|
This bit-field is set and cleared by software. Refer to the DMA controller section for more details. |
|
| Bit 13 | DDS: DMA disable selection (for multi-ADC mode) |
|
This bit is set and cleared by software. |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bits 11:8 | DELAY: Delay between 2 sampling phases |
|
Set and cleared by software. These bits are used in dual or triple interleaved modes. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:0 | MULTI[4:0]: Multi ADC mode selection |
|
These bits are written by software to select the operating mode.
|
Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA2[15:0] |
DATA1[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | DATA2[15:0]: 2nd data item of a pair of regular conversions |
|
|
| Bits 15:0 | DATA1[15:0]: 1st data item of a pair of regular conversions |
|
The following table summarizes the ADC registers.
| Offset | Register |
|---|---|
| 0x000 - 0x04C | ADC1 |
| 0x050 - 0x0FC | Reserved |
| 0x100 - 0x14C | ADC2 |
| 0x118 - 0x1FC | Reserved |
| 0x200 - 0x24C | ADC3 |
| 0x250 - 0x2FC | Reserved |
| 0x300 - 0x308 | Common registers |
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
ADC_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OVR | STRT | JSTRT | JEOC | EOC | AWD |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x04 |
ADC_CR1
|
Res. | Res. | Res. | Res. | Res. | OVRIE | RES[1:0] | AWDEN | JAWDEN | Res. | Res. | Res. | Res. | Res. | Res. | DISC NUM [2:0] |
JDISCEN | DISCEN | JAUTO | AWD SGL | SCAN | JEOCIE | AWDIE | EOCIE | AWDCH[4:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||
| 0x08 |
ADC_CR2
|
Res. | SWSTART | EXTEN[1:0] | EXTSEL [3:0] |
Res. | JSWSTART | JEXTEN[1:0] | JEXTSEL [3:0] |
Res. | Res. | Res. | Res. | ALIGN | EOCS | DDS | DMA | Res. | Res. | Res. | Res. | Res. | Res. | CONT | ADON | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x0C | ADC_SMPR1 | Sample time bits SMPx_x |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 | ADC_SMPR2 | Sample time bits SMPx_x |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x14 |
ADC_JOFR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JOFFSET1[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x18 |
ADC_JOFR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JOFFSET2[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x1C |
ADC_JOFR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JOFFSET3[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x20 |
ADC_JOFR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JOFFSET4[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x24 |
ADC_HTR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HT[11:0] |
|||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||
| 0x28 |
ADC_LTR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LT[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x2C |
ADC_SQR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | L[3:0] | Regular channel sequence SQx_x bits |
||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x30 |
ADC_SQR2
|
Res. | Res. | Regular channel sequence SQx_x bits |
|||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||
| 0x34 |
ADC_SQR3
|
Res. | Res. | Regular channel sequence SQx_x bits |
|||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||
| 0x38 |
ADC_JSQR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JL[1:0] | Injected channel sequence JSQx_x bits |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x3C |
ADC_JDR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JDATA[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x40 |
ADC_JDR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JDATA[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x44 |
ADC_JDR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JDATA[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x48 |
ADC_JDR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JDATA[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x4C |
ADC_DR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Regular DATA[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
ADC_CSR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OVR | STRT | JSTRT | JEOC | EOC | AWD | Res. | Res. | OVR | STRT | JSTRT | JEOC | EOC | AWD | Res. | Res. | OVR | STRT | JSTRT | JEOC | EOC | AWD |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| - | - | ADC3 | - | ADC2 | - | ADC1 |
|||||||||||||||||||||||||||
| 0x04 |
ADC_CCR
Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSVREFE | VBATE | Res. | Res. | Res. | Res. | ADCPRE[1:0] | DMA[1:0] | DDS | Res. | DELAY [3:0] |
Res. | Res. | Res. | MULTI [4:0] |
|||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x08 |
ADC_CDR Reset value |
Regular DATA2[15:0] | Regular DATA1[15:0] |
||||||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, VREF+ (shared with ADC) is available for better resolution.
Figure 93 shows the block diagram of a DAC channel and Table 104 gives the pin description.
| (omitted) |
| Name | Signal type | Remarks |
|---|---|---|
| VREF+ |
Input, analog reference positive |
The higher/positive reference voltage for the DAC, 1.8 V ≤ VREF+ ≤ VDDA |
| VDDA | Input, analog supply | Analog power supply |
| VSSA | Input, analog supply ground | Ground for analog power supply |
| DAC_OUTx | Analog output signal | DAC channelx analog output |
Note: Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP.
Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register.
| (omitted) |
Depending on the selected configuration mode, the data have to be written into the specified register as described below:
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.
| (omitted) |
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-mapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.
| (omitted) |
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time tSETTLING that depends on the power supply voltage and the analog output load.
| (omitted) |
Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following equation:
DACoutput = V× D-----O-----R-
--
REF
4096 16.3.6 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 105.
| Source | Type | TSEL[2:0] |
|---|---|---|
| Timer 6 TRGO event |
Internal signal from on-chip timers |
000 |
| Timer 8 TRGO event | 001 |
|
| Timer 7 TRGO event | 010 |
|
| Timer 5 TRGO event | 011 |
|
| Timer 2 TRGO event | 100 |
|
| Timer 4 TRGO event | 101 |
|
| EXTI line9 | External pin | 110 |
| SWTRIG | Software control bit | 111 |
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.
Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred into the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data.
The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled.
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm.
| (omitted) |
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
| (omitted) |
Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.
| (omitted) |
| (omitted) |
Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.
All modes are described in the paragraphs below.
To configure the DAC in this conversion mode, the following sequence is required:
When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later).
To configure the DAC in this conversion mode, the following sequence is required:
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively.
To configure the DAC in this conversion mode, the following sequence is required:
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB1 clock cycles).
To configure the DAC in this conversion mode, the following sequence is required:
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
Refer to Section 1 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | DMAU DRIE2 |
DMA EN2 | MAMP2[3:0] | WAVE2[1:0] | TSEL2[2:0] | TEN2 | BOFF2 | EN2 |
Res. | Res. | DMAU DRIE1 |
DMA EN1 | MAMP1[3:0] | WAVE1[1:0] | TSEL1[2:0] | TEN1 | BOFF1 | EN1 |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bit 29 | DMAUDRIE2: DAC channel2 DMA underrun interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 28 | DMAEN2: DAC channel2 DMA enable |
|
This bit is set and cleared by software. |
|
| Bits 27:24 | MAMP2[3:0]: DAC channel2 mask/amplitude selector |
|
These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. |
|
| Bits 23:22 | WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable |
|
These bits are set/reset by software. Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) |
|
| Bits 21:19 | TSEL2[2:0]: DAC channel2 trigger selection |
|
These bits select the external event used to trigger DAC channel2
Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
|
|
| Bit 18 | TEN2: DAC channel2 trigger enable |
|
This bit is set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR2 register When software trigger is selected, the transfer from the DAC_DHRx register to the |
|
| Bit 17 | BOFF2: DAC channel2 output buffer disable |
|
This bit is set and cleared by software to enable/disable DAC channel2 output buffer. |
|
| Bit 16 | EN2: DAC channel2 enable |
|
This bit is set and cleared by software to enable/disable DAC channel2. |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bit 13 | DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable |
|
This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled |
|
| Bit 12 | DMAEN1: DAC channel1 DMA enable |
|
This bit is set and cleared by software. |
|
| Bits 11:8 | MAMP1[3:0]: DAC channel1 mask/amplitude selector |
|
These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. |
|
| Bits 7:6 | WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable |
|
These bits are set and cleared by software.
Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
|
|
| Bits 5:3 | TSEL1[2:0]: DAC channel1 trigger selection |
|
These bits select the external event used to trigger DAC channel1.
Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
|
|
| Bit 2 | TEN1: DAC channel1 trigger enable |
|
This bit is set and cleared by software to enable/disable DAC channel1 trigger. When software trigger is selected, the transfer from the DAC_DHRx register to the |
|
| Bit 1 | BOFF1: DAC channel1 output buffer disable |
|
This bit is set and cleared by software to enable/disable DAC channel1 output buffer. |
|
| Bit 0 | EN1: DAC channel1 enable |
|
This bit is set and cleared by software to enable/disable DAC channel1. |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWTRIG2 | SWTRIG1 |
| w | w |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | SWTRIG2: DAC channel2 software trigger |
|
This bit is set and cleared by software to enable/disable the software trigger. This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 |
|
| Bit 0 | SWTRIG1: DAC channel1 software trigger |
|
This bit is set and cleared by software to enable/disable the software trigger. This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | DACC1DHR[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel1. |
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DACC1DHR[11:0] | Res. | Res. | Res. | Res. |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:4 | DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel1. |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC1DHR[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data |
|
These bits are written by software which specifies 8-bit data for DAC channel1. |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | DACC2DHR[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel2. |
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DACC2DHR[11:0] | Res. | Res. | Res. | Res. |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:4 | DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data |
|
These bits are written by software which specify 12-bit data for DAC channel2. |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DHR[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data |
|
These bits are written by software which specifies 8-bit data for DAC channel2. |
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | DACC2DHR[11:0] |
Res. | Res. | Res. | Res. | DACC1DHR[11:0] |
||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel2. |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel1. |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DACC2DHR[11:0] | Res. | Res. | Res. | Res. |
DACC1DHR[11:0] | Res. | Res. | Res. | Res. |
||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:20 | DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel2. |
|
| Bits 19:16 | Reserved, must be kept at reset value. |
| Bits 15:4 | DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data |
|
These bits are written by software which specifies 12-bit data for DAC channel1. |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
Address offset: 0x28
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DACC2DHR[7:0] | DACC1DHR[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data |
|
These bits are written by software which specifies 8-bit data for DAC channel2. |
|
| Bits 7:0 | DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data |
|
These bits are written by software which specifies 8-bit data for DAC channel1. |
Address offset: 0x2C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | DACC1DOR[11:0] |
|||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DACC1DOR[11:0]: DAC channel1 data output |
|
These bits are read-only, they contain data output for DAC channel1. |
Address offset: 0x30
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | DACC2DOR[11:0] |
|||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DACC2DOR[11:0]: DAC channel2 data output |
|
These bits are read-only, they contain data output for DAC channel2. |
Address offset: 0x34
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | DMAUDR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | DMAUDR1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| rc_w1 |
rc_w1 |
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bit 29 | DMAUDR2: DAC channel2 DMA underrun flag |
|
This bit is set by hardware and cleared by software (by writing it to 1). |
|
| Bits 28:14 | Reserved, must be kept at reset value. |
| Bit 13 | DMAUDR1: DAC channel1 DMA underrun flag |
|
This bit is set by hardware and cleared by software (by writing it to 1). |
|
| Bits 12:0 | Reserved, must be kept at reset value. |
Table 106 summarizes the DAC registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | DAC_CR |
Res. | Res. | DMAUDRIE2 | DMAEN2 | MAMP2[3:0] |
WAVE2[2:0] | TSEL2[2:0] | TEN2 | BOFF2 | EN2 | Res. | Res. | DMAUDRIE1 | DMAEN1 | MAMP1[3:0] |
WAVE1[2:0] | TSEL1[2:0] | TEN1 | BOFF1 | EN1 | ||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x04 |
DAC_ SWTRIGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SWTRIG2 | SWTRIG1 |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x08 |
DAC_ DHR12R1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC1DHR[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x0C |
DAC_ Reset value |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC1DHR[11:0] |
Res. | Res. | Res. | Res. | |||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x10 |
DAC_ DHR8R1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC1DHR[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x14 |
DAC_ DHR12R2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DHR[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x18 |
DAC_ DHR12L2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DHR[11:0] |
Res. | Res. | Res. | Res. | |||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
|
0x1C 0x20 |
DAC_ Reset value DAC_ |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DHR[7:0] |
|||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| Res. | Res. | Res. | Res. | D | AC | C2D | HR | [11: | 0] |
Res. | Res. | Res. | Res. | D | AC | C1D | HR | [11: | 0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x24 |
DAC_ DHR12LD |
DACC2DHR[11:0] | Reserved | DACC1DHR[11:0] | Reserved |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
|
0x28 0x2C |
DAC_ Reset value DAC_ |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DHR[7:0] | DACC1DHR[7:0] |
||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | D | AC | C1D | OR | [11: | 0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x30 |
DAC_ DOR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DACC2DOR[11:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x34 | DAC_SR |
Res. | Res. | DMAUDR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMAUDR1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | |||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data stream input from microcontroller memory.
An external Σ∆ modulator provides digital data stream of converted analog values from the external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input channel through a serial interface. DFSDM supports several standards to connect various Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with adjustable parameters). DFSDM module supports the connection of up to 8 multiplexed input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM module also supports alternative parallel data inputs from up to 8 internal 16-bit data channels (from microcontrollers memory).
DFSDM is converting an input data stream into a final digital data word which represents an analog input value on a Σ∆ modulator analog input. The conversion is based on a configurable digital process: the digital filtering and decimation of the input serial data stream.
The conversion speed and resolution are adjustable according to configurable parameters for digital processing: filter type, filter order, length of filter, integrator length. The maximum output data resolution is up to 24 bits. There are two conversion modes: single conversion mode and continuous mode. The data can be automatically stored in a system RAM buffer through DMA, thus reducing the software overhead.
A flexible timer triggering system can be used to control the start of conversion of DFSDM. This timing control is capable of triggering simultaneous conversions or inserting a programmable delay between conversions.
DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of the input channel data stream or to final output data. Analog watchdog has its own digital filtering of input data stream to reach the required speed and resolution of watched data.
To detect short-circuit in control applications, there is a short-circuit detector. This block watches each input channel data stream for occurrence of stable data for a defined time duration (several 0’s or 1’s in an input data stream).
An extremes detector block watches final output data and stores maximum and minimum values from the output data values. The extremes values stored can be restarted by software.
Two power modes are supported: normal mode and stop mode.
This section describes the configuration implemented in DFSDMx.
| DFSDM features | DFSDM1 |
|---|---|
| Number of channels | 8 |
| Number of filters | 4 |
| Input from internal ADC | - |
| Supported trigger sources | 32 |
| Pulses skipper | - |
| ID registers support | - |
| (omitted) |
| Name | Signal Type | Remarks |
|---|---|---|
| VDD | Power supply | Digital power supply. |
| VSS | Power supply | Digital ground power supply. |
| CKIN[7:0] | Clock input | Clock signal provided from external Σ∆ modulator. FT input. |
| DATIN[7:0] | Data input | Data signal provided from external Σ∆ modulator. FT input. |
| CKOUT | Clock output | Clock output to provide clock signal into external Σ∆ modulator. |
| EXTRG[1:0] | External trigger signal |
Input trigger from two EXTI signals to start analog conversion (from GPIOs: EXTI11, EXTI15). |
| Name | Signal Type | Remarks |
|---|---|---|
| dfsdm_jtrg[31:0] |
Internal/ external trigger signal |
Input trigger from internal/external trigger sources in order to start analog conversion (from internal sources: synchronous input, from external sources: asynchronous input with synchronization). See Table 110 for details. |
| dfsdm_break[3:0] | break signal output |
Break signals event generation from Analog watchdog or short-circuit detector |
| dfsdm_dma[3:0] | DMA request signal |
DMA request signal from each DFSDM_FLTx (x=0..3): end of injected conversion event. |
| dfsdm_it[3:0] | Interrupt request signal | Interrupt signal for each DFSDM_FLTx (x=0..3) |
| Trigger name | Trigger source |
|---|---|
| dfsdm_jtrg0 | TIM1_TRGO |
| dfsdm_jtrg1 | TIM1_TRGO2 |
| dfsdm_jtrg2 | TIM8_TRGO |
| dfsdm_jtrg3 | TIM8_TRGO2 |
| dfsdm_jtrg4 | TIM3_TRGO |
| dfsdm_jtrg5 | TIM4_TRGO |
| dfsdm_jtrg6 | TIM10_OC1 |
| dfsdm_jtrg7 | TIM6_TRGO |
| dfsdm_jtrg8 | TIM7_TRGO |
| dfsdm_jtrg[23:9] | Reserved |
| dfsdm_jtrg24 | EXTI11 |
| dfsdm_jtrg25 | EXTI15 |
| dfsdm_jtrg26 | LPTIMER1 |
| dfsdm_jtrg[31:27] | Reserved |
| Break name | Break destination |
|---|---|
| dfsdm_break[0] | TIM1 break |
| dfsdm_break[1] | TIM1 break2 |
| dfsdm_break[2] | TIM8 break |
| dfsdm_break[3] | TIM8 break2 |
DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7) and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sincx digital filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and DFSDM_FLTx is put into stop mode. All register settings remain unchanged except DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register. Once the channel is enabled, it receives serial data from the external Σ∆ modulator or parallel internal data sources (CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before stopping the system clock to enter in the STOP mode of the device.
DFSDM clocks
The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers, digital processing blocks (digital filter, integrator) and next additional blocks (analog watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see DFSDMSEL bit description in Section 5.3.25: RCC dedicated clocks configuration register
(RCC_DCKFGR1)). The DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for all DFSDM_FLTx, x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock input(s). It is provided on CKOUT pin. This output clock signal must be in the range specified in given device datasheet and is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 5.3.25: RCC
dedicated clocks configuration register (RCC_DCKFGR1)).
There are 8 multiplexed serial data channels which can be selected for conversion by each filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register.
Channel inputs selection
Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from the following channel pins. This serial input channel redirection is set by CHINSEL bit in DFSDM_CHyCFGR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation) stereo microphone type. PDM stereo microphone has one data and one clock signal. Data signal provides information for both left and right audio channel (rising clock edge samples for left channel and falling clock edge samples for right channel).
Configuration of serial channels for PDM microphone input:
| (omitted) |
Output clock generation
A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1 register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is performed:
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz.
SPI data input format operation
In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in DFSDM_CHyCFGR1 register).
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register:
Note: An internal clock source can only be used when the external Σ∆ modulator uses CKOUT
signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save CKINy pin connection (CKINy pins can be used for other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less than fDFSDMCLK/4.
Manchester coded data input format operation
In Manchester coded format, the data stream is sent in serial format through DATINy pin only. Decoded data and clock signal are recovered from serial stream after Manchester decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in DFSDM_CHyCFGR1 register):
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than fDFSDMCLK/6.
To correctly receive Manchester coded data, the CKOUTDIV divider (in DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate according formula:
((CKOUTDIV+ 1 ) × TSYSCLK ) <TManchester clock < (2× CKOUTDIV ×TSYSCLK )
| (omitted) |
Clock absence detection
Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register. If enabled, then this clock absence detection is performed continuously on a given channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock error (see CKABF[7:0] in DFSDM_FLT0ISR register and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Clock absence status bit CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0 then CKABF[y] is held in set state).
When a clock absence event has occurred, the data conversion (and/or analog watchdog and short-circuit detector) provides incorrect data. The user should manage this event and discard given data while a clock absence is reported.
The clock absence feature is available only when the system clock is used for the CKOUT signal (CKOUTSRC=0 in DFSDM_CH0CFGR1 register).
When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). The software sequence concerning clock absence detection feature should be:
If SPI data format is used, then the clock absence detection is based on the comparison of an external input clock with an output clock generation (CKOUT signal). The external input clock signal into the input channel must be changed at least once per 8 signal periods of CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CH0CFGR1 register).
| (omitted) |
If Manchester data format is used, then the clock absence means that the clock recovery is unable to perform from Manchester coded signal. For a correct clock recovery, it is first necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 107 for Manchester synchronization).
The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register). This condition also defines the minimum data rate to be able to correctly recover the Manchester coded data and clock signals.
The maximum data rate of Manchester coded data must be less than the CKOUT signal.
So to correctly receive Manchester coded data, the CKOUTDIV divider must be set according the formula:
((CKOUTDIV+ 1 ) × TSYSCLK ) <TManchester clock < (2× CKOUTDIV ×
TSYSCLK )
A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock recovery error (see CKABF[7:0] in DFSDM_FLT0ISR register and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in DFSDM_FLT0ICR register), the clock absence flag is refreshed.
| (omitted) |
Manchester/SPI code synchronization
The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:
CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized the hardware immediately set the CKABF[y] flag. Software is then reading back the CKABF[y] flag and if it is set then perform again clearing of this flag by setting CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to synchronize/receive Manchester coded data the CKOUTDIV divider (in DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate according the formula below.
((CKOUTDIV+ 1 ) × TSYSCLK ) <TManchester clock < (2× CKOUTDIV ×TSYSCLK )
SPI coded stream is synchronized after first detection of clock input signal (valid rising/falling edge).
Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register).
| (omitted) |
External serial clock frequency measurement
The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input data clock after a conversion trigger (regular or injected) and finishes by last input data clock before conversion ends (end of conversion flag is set). Each conversion duration (time between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1). The user can then compute the data rate according to the digital filter settings (FORD, FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in DFSDM_FLTxCNVTIMR register).
In case of parallel data input (Section 17.4.6: Parallel data inputs) the measured frequency is the average input data rate during one conversion.
Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sincx
filters (x=1..5):
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
regular conversion with FAST = 1 (except first conversion):
for Sincx
and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where:
Channel offset setting
Each channel has its own offset setting (in register) which is finally subtracted from each conversion result (injected or regular) from a given channel. Offset correction is performed after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0] field in DFSDM_CHyCFGR2 register.
Data right bit shift
To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts which will be applied on each conversion result (injected or regular) from a given channel. The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained, in order to have valid 24-bit signed format of result data.
The following parameters must be configured for the input serial interface:
Each input channel provides a register for 16-bit parallel data input (besides serial data input). Each 16-bit parallel input can be sourced from internal data sources only:
The selection for using serial or parallel data input for a given channel is done by field DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel data source: direct write by CPU/DMA.
Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to the digital filter which is accepting 16-bit parallel data.
If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHyDATINR register is write protected.
Input from memory (direct CPU/DMA write)
The direct data write into DFSDM_CHyDATINR register by CPU or DMA (DATMPX[1:0]=2) can be used as data input in order to process digital data streams from memory or peripherals.
Data can be written by CPU or DMA into DFSDM_CHyDATINR register:
CPU data write:
Input data are written directly by CPU into DFSDM_CHyDATINR register.
DMA data write:
The DMA should be configured in memory-to-memory transfer mode to transfer data from memory buffer into DFSDM_CHyDATINR register. The destination memory
address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input.
This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading.
The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load respectively one or two samples in one write operation. 32-bit input data register (DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1 register:
Standard mode (DATPACK[1:0]=0):
Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and write protected. The digital filter must perform one input sampling (from INDAT0[15:0]) to empty data register after it has been filled by CPU/DMA. This mode is used together with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per write operation.
Interleaved mode (DATPACK[1:0]=1):
DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR register. This mode is used together with 32-bit CPU/DMA access to DFSDM_CHyDATINR register to load two samples per write operation.
Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is automatically copied INDAT0[15:0] of the following (y+1) channel data register DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y = 0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0] and INDAT1[15:0] parts are write protected for this channel. If even channel is set to Dual mode then the following odd channel must be set into Standard mode (DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 108 for DFSDM_CHyDATINR registers data modes and assignments of data samples to channels.
| (omitted) |
The write into DFSDM_CHyDATINR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data samples into DFSDM_CHyDATINR before the single conversion is started (any data present in the DFSDM_CHyDATINR before starting a conversion is discarded).
There are 8 multiplexed channels which can be selected for conversion using the injected channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1 means that channel y is selected.
Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In scan mode, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first, followed immediately by the next higher channel until all the channels selected by JCHG[7:0] have been converted. In single mode (JSCAN=0), only one channel from the selected channels is converted, and the channel selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel selection to the lowest selected channel.
Injected conversions can be launched by software or by a trigger. They are never interrupted by regular conversions.
The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the DFSDM_FLTxCR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of continuous regular conversions is temporarily interrupted when an injected conversion is requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register) causes that the conversion will never end - because no input data is provided (with no clock signal). In this case, it is necessary to enable a given channel (CHEN=1 in DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1 register.
DFSDM contains a Sincx
type digital filter implementation. This Sincx filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sincx
digital filter is configurable in order to reach the required output data rates and required output data resolution. The configurable parameters are:
The filter has the following transfer function (impulse response in H domain):
⎝1–
z–1 ⎠
⎝1–
z ⎠
| (omitted) |
| FOSR | Sinc1 | Sinc2 | FastSinc | Sinc3 | Sinc4 | Sinc5 |
|---|---|---|---|---|---|---|
| x | +/- x | +/- x2 | +/- 2x2 | +/- x3 | +/- x4 | +/- x5 |
| 4 | +/- 4 | +/- 16 | +/- 32 | +/- 64 | +/- 256 | +/- 1024 |
| 8 | +/- 8 | +/- 64 | +/- 128 | +/- 512 | +/- 4096 | - |
| 32 | +/- 32 | +/- 1024 | +/- 2048 | +/- 32768 | +/- 1048576 | +/- 33554432 |
| 64 | +/- 64 | +/- 4096 | +/- 8192 | +/- 262144 | +/- 16777216 | +/- 1073741824 |
| 128 | +/- 128 | +/- 16384 | +/- 32768 | +/- 2097152 | +/- 268435456 |
rflow on full scale |
| 256 | +/- 256 | +/- 65536 | +/- 131072 | +/- 16777216 | Result can overflow on full scale input (> 32-bit signed integer) | |
| 1024 | +/- 1024 | +/- 1048576 | +/- 2097152 | +/- 1073741824 |
||
For more information about Sinc filter type properties and usage, it is recommended to study the theory about digital filters (more resources can be downloaded from internet).
The integrator performs additional decimation and a resolution increase of data coming from the digital filter. The integrator simply performs the sum of data from a digital filter for a given number of data samples from a filter.
The integrator oversampling ratio parameter defines how many data counts will be summed to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0] bits description in DFSDM_FLTxFCR register).
| IOSR | Sinc1 | Sinc2 | FastSinc | Sinc3 | Sinc4 | Sinc5 |
|---|---|---|---|---|---|---|
| x | +/- FOSR. x | +/- FOSR2. x | +/- 2.FOSR2. x | +/- FOSR3. x | +/- FOSR4. x | +/- FOSR5. x |
| 4 | - | - | - | +/- 67 108 864 | - | - |
| 32 | - | - | - | +/- 536 870 912 | - | - |
| 128 | - | - | - | +/- 2 147 483 648 | - | - |
| 256 | - | - | - | +/- 232 | - | - |
The analog watchdog purpose is to trigger an external signal (break or interrupt) when an analog signal reaches or crosses given maximum and minimum threshold values. An interrupt/event/break generation can then be invoked.
Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog filter on each channel) or data output register (current injected or regular conversion result) according to AWFSEL bit setting (in DFSDM_FLTxCR1 register). The input channels to be monitored or not by the analog watchdog x will be selected by AWDCH[7:0] in DFSDM_FLTxCR2 register.
Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in DFSDM_FLTxAWLTR register).
There are 2 options for comparing the threshold registers with the data values
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is taken from channels selected by AWDCH[7:0] field (DFSDM_FLTxCR2 register). Each of the selected channels filter result is compared to one threshold value pair (AWHT[23:0] / AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit threshold compared with the analog watchdog filter output because data coming from the analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data (from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When several channels are selected (field AWDCH[7:0] field of DFSDM_FLTxCR2 register), several comparison requests may be received simultaneously. In this case, the channel request with the lowest number is managed first and then continuing to higher selected channels. For each channel, the result can be recorded in a separate flag (fields
AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog feature at this input clock speed. Therefore user must properly configure the number of watched channels and analog watchdog filter parameters with respect to input sampling clock speed and DFSDM frequency.
Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate given by the analog watchdog filter setting and the channel input clock frequency.
The analog watchdog filter conversion works like a regular Fast Continuous Conversion without the intergator. The number of serial samples needed for one result from analog watchdog filter output (at channel input clock frequency fCKIN):
first conversion:
for Sincx
filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1]
for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1]
next conversions:
for Sincx
and FastSinc filters: number of samples = [FOSR * IOSR]
where:
FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_CHyAWSCDR register)
FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_CHyAWSCDR register)
In case of output data register monitoring (AWFSEL=0), the comparison is done after a right bit shift and an offset correction of final data (see OFFSET[23:0] and DTRBS[4:0] fields in DFSDM_CHyCFGR2 register). A comparison is performed after each injected or regular end of conversion for the channels selected by AWDCH[7:0] field (in DFSDM_FLTxCR2 register).
The status of an analog watchdog event is signalized in DFSDM_FLTxAWSR register where a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched events in DFSDM_FLTxAWSR register are cleared by writing ‘1’ into the corresponding clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDM_FLTxAWCFR register.
The global status of an analog watchdog is signalized by the AWDF flag bit in DFSDM_FLTxISR register (it is used for the fast detection of an interrupt source). AWDF=1 signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one channel). AWDF bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared.
An analog watchdog event can be assigned to break output signal. There are four break outputs to be assigned to a high or low threshold crossing event (dfsdm_break[3:0]). The break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and BKAWL[3:0] fields in DFSDM_FLTxAWHTR and DFSDM_FLTxAWLTR register.
The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or overvoltage). An interrupt/event/break generation can be invoked.
Input data into a short-circuit detector is taken from channel transceiver outputs.
There is an upcounting counter on each input channel which is counting consecutive 0’s or 1’s on serial data receiver outputs. A counter is restarted if there is a change in the data stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit threshold register value (SCDT[7:0] bits in DFSDM_CHyAWSCDR register), then a short-circuit event is invoked. Each input channel has its short-circuit detector. Any channel can be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1 register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits, status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared also by hardware when corresponding channel y is disabled (CHEN[y] = 0).
On each channel, a short-circuit detector event can be assigned to break output signal dfsdm_break[3:0]. There are four break outputs to be assigned to a short-circuit detector event. The break signal assignment to a given channel short-circuit detector event is done by BKSCD[3:0] field in DFSDM_CHyAWSCDR register.
Short circuit detector cannot be used in case of parallel input data channel selection (DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register).
Four break outputs are totally available (shared with the analog watchdog function).
The purpose of an extremes detector is to collect the minimum and maximum values of final output data words (peak to peak values).
If the output data word is higher than the value stored in the extremes detector maximum register (EXMAX[23:0] bits in DFSDM_FLTxEXMAX register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMAXCH[2:0] bits (in DFSDM_FLTxEXMAX register) .
If the output data word is lower than the value stored in the extremes detector minimum register (EXMIN[23:0] bits in DFSDM_FLTxEXMIN register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMINCH[2:0] bits (in DFSDM_FLTxEXMIN register).
The minimum and maximum register values can be refreshed by software (by reading given DFSDM_FLTxEXMAX or DFSDM_FLTxEXMIN register). After refresh, the extremes detector minimum data register DFSDM_FLTxEXMIN is filled with 0x7FFFFF (maximum positive value) and the extremes detector maximum register DFSDM_FLTxEXMAX is filled with 0x800000 (minimum negative value).
The extremes detector performs a comparison after a right bit shift and an offset data correction. For each extremes detector, the input channels to be considered into computing the extremes value are selected in EXCH[7:0] bits (in DFSDM_FLTxCR2 register).
The data unit block is the last block of the whole processing path: External Σ∆ modulators - Serial transceivers - Sinc filter - Integrator - Data unit block.
The output data rate depends on the serial data stream rate, and filter and integrator settings. The maximum output data rate is:
-----------------------------------------------f-C----K----I-N-
-----------------------------------------------
Datarate samples ⁄
s = F⋅ (I
– 1 + F ) + (F+ 1 ) ...FAST = 0, Sincx filter
OSR OSR ORD ORD
Datarate samples ⁄
s = -----------------------------------f
--C----K---I--N
------------------------------------ ...FAST = 0, FastSinc filter
FOSR ⋅ (I
OSR – 1 + 4 ) + (2+ 1 )
or
-----------f
--C---K----I--N
------------
Datarate samples ⁄
s = F⋅ I
...FAST = 1
OSR OSR
Maximum output data rate in case of parallel data input:
-----------------------------------f
--D---A----T---A----I-N----_---R----A---T---E-
-----------------------------------
Datarate samples ⁄
s = F⋅ (I
– 1 + F ) + (F+ 1 ) ...FAST = 0, Sincx filter
OSR OSR ORD ORD
or
Datarate samples ⁄
s = ------------------------f
--D---A----T---A----I-N----_---R---A---T---E
------------------------- ...FAST = 0, FastSinc filter
FOSR ⋅ (I
OSR – 1 + 4 ) + (2+ 1 )
or
f-
-D----A----T---A---I--N----_--R----A---T---E
-
Datarate samples ⁄
s = F⋅ I
...FAST=1 or any filter bypass case (FOSR = 1
) OSR OSR
where: fDATAIN_RATE...input data rate from CPU/DMA
The right bit-shift of final data is performed in this module because the final data width is 24-
bit and data coming from the processing path can be up to 32 bits. This right bit-shift is configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained - to have valid 24-bit signed format of result data.
In the next step, an offset correction of the result is performed. The offset correction value (OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate calibration routine.
Due to the fact that all operations in digital processing are performed on 32-bit signed registers, the following conditions must be fulfilled not to overflow the result:
FOSR FORD . IOSR <= 231 ... for Sincx
filters, x = 1..5)
2 . FOSR 2 . IOSR <= 231 ... for FastSinc filter)
Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate
(fDATAIN_RATE) must be limited to be able to read all output data:
fDATAIN_RATE ≤ fAPB
where fAPB is the bus frequency to which the DFSDM peripheral is connected.
Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be used for a differential or single-ended signal measurement.
A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and ones from a Σ∆ modulator represents values -1 and +1).
Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format).
Injected conversions can be launched using the following methods:
If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is triggered, all of the selected channels in the injected group (JCHG[7:0] bits in DFSDM_FLTxJCHGR register) are converted sequentially, starting with the lowest channel (channel 0, if selected).
If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in DFSDM_FLTxJCHGR register) is converted and the channel selection is then moved to the next selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel selection to the lowest selected injected channel.
Only one injected conversion can be ongoing at a given time. Thus, any request to launch an injected conversion is ignored if another request for an injected conversion has already been issued but not yet completed.
Regular conversions can be launched using the following methods:
Only one regular conversion can be pending or ongoing at a given time. Thus, any request to launch a regular conversion is ignored if another request for a regular conversion has
already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress. This pending regular conversion is then delayed and is performed when all injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit in DFSDM_FLTxRDATAR register.
Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in continuous mode. RCONT=1 means that the channel selected by RCH[2:0] is converted repeatedly after ‘1’ is written to RSWSTART.
The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh data if converting continuously from one channel because data inside the filter is valid from previously sampled continuous data. The speed increase depends on the chosen filter order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
for Sincx filters:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
if FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
t = IOSR / fCKIN (... but CNVCNT=0)
Continuous mode is not available for injected conversions. Injected conversions can be started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is performed, then regular continuous conversion is restarted from the next conversion cycle (like new regular continuous conversion is applied for new channel selection - even if there is no change in DFSDM_FLTxCR1 register).
An injected conversion has a higher precedence than a regular conversion. A regular conversion which is already in progress is immediately interrupted by the request of an injected conversion; this regular conversion is restarted after the injected conversion finishes.
An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’ (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in progress, the regular conversion is immediately stopped and an injected conversion is launched. The regular conversion is then restarted and this delayed restart is signalized in bit RPEND.
Injected conversions have precedence over regular conversions in that a injected conversion can temporarily interrupt a sequence of continuous regular conversions. When the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action. For example, suppose that, while an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1 writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence finishes, the precedence dictates that the regular conversion is performed next and its delayed start is signalized in RPEND bit.
In order to reduce the consumption, the DFSDM filter and integrator are automatically put into idle when not used by conversions (RCIP=0, JCIP=0).
In order to increase the CPU performance, a set of interrupts related to the CPU event occurrence has been implemented:
| Interrupt event | Event flag | Event/Interrupt clearing method |
Interrupt enable control bit |
|---|---|---|---|
| End of injected conversion | JEOCF | reading DFSDM_FLTxJDATAR | JEOCIE |
| End of regular conversion | REOCF | reading DFSDM_FLTxRDATAR | REOCIE |
| Injected data overrun | JOVRF | writing CLRJOVRF = 1 | JOVRIE |
| Regular data overrun | ROVRF | writing CLRROVRF = 1 | ROVRIE |
| Analog watchdog |
AWDF, AWHTF[7:0], AWLTF[7:0] |
writing CLRAWHTF[7:0] = 1 writing CLRAWLTF[7:0] = 1 |
AWDIE, (AWDCH[7:0]) |
| short-circuit detector | SCDF[7:0] | writing CLRSCDF[7:0] = 1 |
SCDIE, (SCDEN) |
| Channel clock absence | CKABF[7:0] | writing CLRCKABF[7:0] = 1 |
CKABIE, (CKABEN) |
To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.
This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DFSDM EN |
CKOUT SRC |
Res. | Res. | Res. | Res. | Res. | Res. | CKOUTDIV[7:0] |
DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHIN SEL |
CHEN | CKAB EN |
SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||
| Bit 31 | DFSDMEN: Global enable for DFSDM interface |
|
0: DFSDM interface disabled –all registers DFSDM_FLTxISR are set to reset state (x = 0..3) –all registers DFSDM_FLTxAWSR are set to reset state (x = 0..3)
DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
|
|
| Bit 30 | CKOUTSRC: Output serial clock source selection |
|
0: Source for output clock is from system clock –SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 5.3.25: RCC This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
|
|
| Bits 29:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | CKOUTDIV[7:0]: Output serial clock divider |
|
0: Output clock generation is disabled (CKOUT signal is set to low state)
CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
|
|
| Bits 15:14 | DATPACK[1:0]: Data packing mode in DFSDM_CHyDATINR register. |
|
0:Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. |
|
| Bits 13:12 | DATMPX[1:0]: Input data multiplexer for channel y |
|
0:Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). |
|
| Bits 11:9 | Reserved, must be kept at reset value. |
| Bit 8 | CHINSEL: Channel inputs selection |
|
0: Channel inputs are taken from pins of the same channel y. |
|
| Bit 7 | CHEN: Channel y enable |
|
0: Channel y disabled |
|
| Bit 6 | CKABEN: Clock absence detector enable on channel y |
|
0: Clock absence detector disabled on channel y |
|
| Bit 5 | SCDEN: Short-circuit detector enable on channel y |
|
0: Input channel y will not be guarded by the short-circuit detector |
|
| Bit 4 | Reserved, must be kept at reset value. |
| Bits 3:2 | SPICKSEL[1:0]: SPI clock select for channel y |
|
0:clock coming from external CKINy input - sampling point according SITP[1:0] |
|
| Bits 1:0 | SITP[1:0]: Serial interface type for channel y |
|
00: SPI with rising edge to strobe data |
This register specifies the parameters used by channel y.
Address offset: 0x04 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFSET[23:8] |
OFFSET[7:0] | DTRBS[4:0] | Res. | Res. | Res. |
||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||
| Bits 31:8 | OFFSET[23:0]: 24-bit calibration offset for channel y |
|
For channel y, OFFSET is applied to the results of each conversion from this channel. |
|
| Bits 7:3 | DTRBS[4:0]: Data right bit-shift for channel y |
|
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). |
|
| Bits 2:0 | Reserved, must be kept at reset value. |
Short-circuit detector and analog watchdog settings for channel y.
Address offset: 0x08 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] |
BKSCD[3:0] | Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:22 | AWFORD[1:0]: Analog watchdog Sinc filter order on channel y |
|
0: FastSinc filter type H( z ) = ⎛1-----–- This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). |
|
| Bit 21 | Reserved, must be kept at reset value. |
| Bits 20:16 | AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y |
|
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is also the decimation ratio of the analog data rate.
If AWFOSR = 0 then the filter has no effect (filter bypass).
|
|
| Bits 15:12 | BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y |
|
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y |
|
| Bits 11:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | SCDT[7:0]: short-circuit detector threshold for channel y |
|
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. |
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
Address offset: 0x0C + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
WDATA[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | WDATA[15:0]: Input channel y watchdog data |
|
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). |
This register contains 16-bit input data to be processed by DFSDM filter module.
Address offset: 0x10 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INDAT1[15:0] |
INDAT0[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | INDAT1[15:0]: Input data for channel y or channel y+1 |
|
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. |
|
| Bits 15:0 | INDAT0[15:0]: Input data for channel y |
|
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. |
Address offset: 0x100 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | AWF SEL |
FAST | Res. | Res. | RCH[2:0] | Res. | Res. | RDMA EN |
Res. | RSYNC | RCON T |
RSW START |
Res. |
Res. | JEXTEN[1:0] | JEXTSEL[4:0] | Res. | Res. | JDMA EN |
JSCAN | JSYNC | Res. | JSW START |
DFEN |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rt_w1 |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rt_w1 | rw |
|||||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | AWFSEL: Analog watchdog fast mode select |
|
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift |
|
| Bit 29 | FAST: Fast conversion mode selection for regular conversions |
|
0: Fast conversion mode disabled |
|
| Bits 28:27 | Reserved, must be kept at reset value. |
| Bits 26:24 | RCH[2:0]: Regular channel selection |
|
0: Channel 0 is selected as the regular channel |
|
| Bits 23:22 | Reserved, must be kept at reset value. |
| Bit 21 | RDMAEN: DMA channel enabled to read data for the regular conversion |
|
0: The DMA channel is not enabled to read regular data |
|
| Bit 20 | Reserved, must be kept at reset value. |
| Bit 19 | RSYNC: Launch regular conversion synchronously with DFSDM_FLT0 |
|
0: Do not launch a regular conversion synchronously with DFSDM_FLT0 |
|
| Bit 18 | RCONT: Continuous mode selection for regular conversions |
|
0: The regular channel is converted just once for each conversion request |
|
| Bit 17 | RSWSTART: Software start of a conversion on the regular channel |
|
0: Writing ‘0’ has no effect |
|
| Bits 16:15 | Reserved, must be kept at reset value. |
| Bits 14:13 | JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions |
|
00: Trigger detection is disabled |
|
| Bits 12:8 | JEXTSEL[4:0]: Trigger signal selection for launching injected conversions |
|
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), DFSDM_FLT0 DFSDM_FLT1 DFSDM_FLT2 DFSDM_FLT3 |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bit 5 | JDMAEN: DMA channel enabled to read data for the injected channel group |
|
0: The DMA channel is not enabled to read injected data |
|
| Bit 4 | JSCAN: Scanning conversion mode for injected conversions |
|
0: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. |
|
| Bit 3 | JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger |
|
0: Do not launch an injected conversion synchronously with DFSDM_FLT0 |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | JSWSTART: Start a conversion of the injected group of channels |
|
0: Writing ‘0’ has no effect. |
|
| Bit 0 | DFEN: DFSDM_FLTx enable |
|
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. –register DFSDM_FLTxISR is set to the reset state –register DFSDM_FLTxAWSR is set to the reset state |
Address offset: 0x104 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDCH[7:0] |
EXCH[7:0] | Res. | CKAB IE |
SCDIE | AWDIE | ROVR IE |
JOVRI E |
REOC IE |
JEOCI E |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | AWDCH[7:0]: Analog watchdog channel selection |
|
These bits select the input channel to be guarded continuously by the analog watchdog. |
|
| Bits 15:8 | EXCH[7:0]: Extremes detector channel selection |
|
These bits select the input channels to be taken by the Extremes detector. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | CKABIE: Clock absence interrupt enable |
|
0: Detection of channel input clock absence interrupt is disabled
CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
|
|
| Bit 5 | SCDIE: Short-circuit detector interrupt enable |
|
0: short-circuit detector interrupt is disabled
SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
|
|
| Bit 4 | AWDIE: Analog watchdog interrupt enable |
|
0: Analog watchdog interrupt is disabled |
|
| Bit 3 | ROVRIE: Regular data overrun interrupt enable |
|
0: Regular data overrun interrupt is disabled |
|
| Bit 2 | JOVRIE: Injected data overrun interrupt enable |
|
0: Injected data overrun interrupt is disabled |
|
| Bit 1 | REOCIE: Regular end of conversion interrupt enable |
|
0: Regular end of conversion interrupt is disabled |
|
| Bit 0 | JEOCIE: Injected end of conversion interrupt enable |
|
0: Injected end of conversion interrupt is disabled |
Address offset: 0x108 + 0x80 * x, x = 0..3
Reset value: 0x00FF 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCDF[7:0] | CKABF[7:0] |
Res. | RCIP | JCIP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDF | ROVRF | JOVRF | REOCF | JEOCF |
||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r |
|||||||||
| Bits 31:24 | SCDF[7:0]: short-circuit detector flag |
|
SDCF[y]=0: No short-circuit detector event occurred on channel y
SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
|
|
| Bits 23:16 | CKABF[7:0]: Clock absence flag |
|
CKABF[y]=0: Clock signal on channel y is present.
CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
|
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | RCIP: Regular conversion in progress status |
|
0: No request to convert the regular channel has been issued |
|
| Bit 13 | JCIP: Injected conversion in progress status |
|
0: No request to convert the injected channel group (neither by software nor by trigger) has been issued |
|
| Bits 12:5 | Reserved, must be kept at reset value. |
| Bit 4 | AWDF: Analog watchdog |
|
0: No Analog watchdog event occurred |
|
| Bit 3 | ROVRF: Regular conversion overrun flag |
|
0: No regular conversion overrun has occurred |
|
| Bit 2 | JOVRF: Injected conversion overrun flag |
|
0: No injected conversion overrun has occurred |
|
| Bit 1 | REOCF: End of regular conversion flag |
|
0: No regular conversion has completed |
|
| Bit 0 | JEOCF: End of injected conversion flag |
|
0: No injected conversion has completed
For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in
All the bits of DFSDM_FLTxISR are automatically reset when DFEN=0.
|
Address offset: 0x10C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLRSCDF[7:0] | CLRCKABF[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLRR OVRF |
CLRJ OVRF |
Res. | Res. |
||||||||||||||
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rc_w1 | rc_w1 | ||||||||||||||
| Bits 31:24 | CLRSCDF[7:0]: Clear the short-circuit detector flag |
|
CLRSCDF[y]=0: Writing ‘0’ has no effect
CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
|
|
| Bits 23:16 | CLRCKABF[7:0]: Clear the clock absence flag |
|
CLRCKABF[y]=0: Writing ‘0’ has no effect
CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
|
|
| Bits 15:4 | Reserved, must be kept at reset value. |
| Bit 3 | CLRROVRF: Clear the regular conversion overrun flag |
|
0: Writing ‘0’ has no effect |
|
| Bit 2 | CLRJOVRF: Clear the injected conversion overrun flag |
|
0: Writing ‘0’ has no effect |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
|
The bits of DFSDM_FLTxICR are always read as ‘0’.
|
Address offset: 0x110 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JCHG[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | JCHG[7:0]: Injected channel group selection |
|
JCHG[y]=0: channel y is not part of the injected group |
Address offset: 0x114 + 0x80 * x, x = 0..3
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FORD[2:0] | Res. | Res. | Res. | FOSR[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IOSR[7:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||
| Bits 31:29 | FORD[2:0]: Sinc filter order |
|
0: FastSinc filter type ⎝1– H( z ) = ⎛⎜1-----–- This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1). |
|
| Bits 28:26 | Reserved, must be kept at reset value. |
| Bits 25:16 | FOSR[9:0]: Sinc filter oversampling ratio (decimation rate) |
|
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This number is also the decimation ratio of the output data rate from filter.
If FOSR = 0, then the filter has no effect (filter bypass).
|
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | IOSR[7:0]: Integrator oversampling ratio (averaging length) |
|
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
If IOSR = 0, then the Integrator has no effect (Integrator bypass).
|
Address offset: 0x118 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| JDATA[23:8] |
JDATA[7:0] | Res. | Res. | Res. | Res. | Res. | JDATACH[2:0] |
||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r |
|||||
| Bits 31:8 | JDATA[23:0]: Injected group conversion data |
|
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. |
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | JDATACH[2:0]: Injected channel most recently converted |
|
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
DMA may be used to read the data from this register. Half-word accesses may be used to Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not |
Address offset: 0x11C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RDATA[23:8] |
RDATA[7:0] | Res. | Res. | Res. | RPEND | Res. | RDATACH[2:0] |
||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | ||||
| Bits 31:8 | RDATA[23:0]: Regular channel conversion data |
|
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bit 4 | RPEND: Regular channel pending data |
|
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bits 2:0 | RDATACH[2:0]: Regular channel most recently converted |
|
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
Half-word accesses may be used to read only the MSBs of conversion data.
Reading this register also clears REOCF in DFSDM_FLTxISR.
|
Address offset: 0x120 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AWHT[23:8] |
AWHT[7:0] | Res. | Res. | Res. | Res. | BKAWH[3:0] |
|||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:8 | AWHT[23:0]: Analog watchdog high threshold |
|
These bits are written by software to define the high threshold for the analog watchdog. In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event |
|
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event |
Address offset: 0x124 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AWLT[23:8] |
AWLT[7:0] | Res. | Res. | Res. | Res. | BKAWL[3:0] |
|||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:8 | AWLT[23:0]: Analog watchdog low threshold |
|
These bits are written by software to define the low threshold for the analog watchdog. In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event |
|
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event |
Address offset: 0x128 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
AWHTF[7:0] | AWLTF[7:0] |
||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | AWHTF[7:0]: Analog watchdog high threshold flag |
|
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register. |
|
| Bits 7:0 | AWLTF[7:0]: Analog watchdog low threshold flag |
|
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.
|
Address offset: 0x12C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CLRAWHTF[7:0] | CLRAWLTF[7:0] |
||||||||||||||
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag |
|
CLRAWHTF[y]=0: Writing ‘0’ has no effect |
|
| Bits 7:0 | CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag |
|
CLRAWLTF[y]=0: Writing ‘0’ has no effect |
Address offset: 0x130 + 0x80 * x, (x = 0 to 3)
Reset value: 0x8000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXMAX[23:8] |
EXMAX[7:0] | Res. | Res. | Res. | Res. | Res. | EXMAXCH[2:0] |
||||||||||||||||||||||||
| rs_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r |
rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | r | r | r |
|||||
| Bits 31:8 | EXMAX[23:0]: Extremes detector maximum value |
|
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register. |
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | EXMAXCH[2:0]: Extremes detector maximum data channel. |
|
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register. |
Address offset: 0x134 + 0x80 * x, (x = 0 to 3)
Reset value: 0x7FFF FF00
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXMIN[23:8] |
EXMIN[7:0] | Res. | Res. | Res. | Res. | Res. | EXMINCH[2:0] |
||||||||||||||||||||||||
| rc_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r |
rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | rs_r | r | r | r |
|||||
| Bits 31:8 | EXMIN[23:0]: Extremes detector minimum value |
|
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. |
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | EXMINCH[2:0]: Extremes detector minimum data channel |
|
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register. |
Address offset: 0x138 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CNVCNT[27:12] |
CNVCNT[11:0] | Res. | Res. | Res. | Res. |
||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | ||||
| Bits 31:4 | CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from CPU/DMA write) |
|
When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
The following table summarizes the DFSDM registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
DFSDM_ CH0CFGR1 |
DFSDMEN | CKOUTSRC | Res. | Res. | Res. | Res. | Res. | Res. | CKOUTDIV[7:0] |
DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPI[C1:K0S]EL | SITP[1:0] | |||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x04 |
DFSDM_ CH0CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x08 |
DFSDM_ CH0AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AW[1F:O0]RD | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x0C |
DFSDM_ CH0WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x10 |
DFSDM_ CH0DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x14 - 0x1C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x20 |
DFSDM_ CH1CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPI[C1:K0S]EL | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||
| 0x24 |
DFSDM_ CH1CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x28 |
DFSDM_ CH1AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x2C |
DFSDM_ CH1WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x30 |
DFSDM_ CH1DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x34 - 0x3C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x40 |
DFSDM_ CH2CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x44 |
DFSDM_ CH2CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x48 |
DFSDM_ CH2AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x4C |
DFSDM_ CH2WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x50 |
DFSDM_ CH2DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x54 - 0x5C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x60 |
DFSDM_ CH3CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x64 |
DFSDM_ CH3CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x68 |
DFSDM_ CH3AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x6C |
DFSDM_ CH3WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x70 |
DFSDM_ CH3DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x74 - 0x7C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x80 |
DFSDM_ CH4CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x84 |
DFSDM_ CH4CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x88 |
DFSDM_ CH4AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x8C |
DFSDM_ CH4WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x90 |
DFSDM_ CH4DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x94 - 0x9C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0xA0 |
DFSDM_ CH5CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xA4 |
DFSDM_ CH5CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0xA8 |
DFSDM_ CH5AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0xAC |
DFSDM_ CH5WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0xB0 |
DFSDM_ CH5DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0xB4 - 0xBC | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0xC0 |
DFSDM_ CH6CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xC4 |
DFSDM_ CH6CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0xC8 |
DFSDM_ CH6AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0xCC |
DFSDM_ CH6WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0xD0 |
DFSDM_ CH6DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0xD4 - 0xDC | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0xE0 |
DFSDM_ CH7CFGR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATPACK[1:0] | DATMPX[1:0] | Res. | Res. | Res. | CHINSEL | CHEN | CKABEN | SCDEN | Res. | SPICKSEL[1:0] | SITP[1:0] | ||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xE4 |
DFSDM_ CH7CFGR2 |
OFFSET[23:0] | DTRBS[4:0] |
Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0xE8 |
DFSDM_ CH7AWSCDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWFORD[1:0] | Res. | AWFOSR[4:0] | BKSCD[3:0] |
Res. | Res. | Res. | Res. | SCDT[7:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0xEC |
DFSDM_ CH7WDATR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDATA[15:0] |
|||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0xF0 |
DFSDM_ CH7DATINR |
INDAT1[15:0] | INDAT0[15:0] |
||||||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0xF4 - 0xFC | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x100 |
DFSDM_ FLT0CR1 |
Res. | AWFSEL | FAST | Res. | Res. | RCH[2:0] |
Res. | Res. | RDMAEN | Res. | RSYNC | RCONT | RSW START | Res. | Res. | JEXTEN[1:0] | JEXTSEL[4:0] |
Res. | Res. | JDMAEN | JSCAN | JSYNC | Res. | JSW START | DFEN | |||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x104 |
DFSDM_ FLT0CR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDCH[7:0] | EXCH[7:0] |
Res. | CKABIE | SCDIE | AWDIE | ROVRIE | JOVRIE | REOCIE | JEOCIE | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x108 |
DFSDM_ FLT0ISR |
SCDF[7:0] | CKABF[7:0] |
Res. | RCIP | JCIP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDF | ROVRF | JOVRF | REOCF | JEOCF | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x10C |
DFSDM_ FLT0ICR |
CLRSCDF[7:0] | CLRCKABF[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLR ROVRF | CLR JOVRF | Res. | Res. | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x110 |
DFSDM_ FLT0JCHGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JCHG[7:0] |
|||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||||||||||||||||
| 0x114 |
DFSDM_ FLT0FCR |
FORD[2:0] | Res. | Res. | Res. | FOSR[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IOSR[7:0] |
||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x118 |
DFSDM_ FLT0JDATAR |
JDATA[23:0] |
Res. | Res. | Res. | Res. | Res. | JDATACH [2:0] | |||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x11C |
DFSDM_ FLT0RDATAR |
RDATA[23:0] |
Res. | Res. | Res. | RPEND | Res. | RDATA CH[2:0] |
|||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x120 |
DFSDM_ FLT0AWHTR |
AWHT[23:0] |
Res. | Res. | Res. | Res. | BKAWH[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x124 |
DFSDM_ FLT0AWLTR |
AWLT[23:0] |
Res. | Res. | Res. | Res. | BKAWL[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x128 |
DFSDM_ FLT0AWSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWHTF[7:0] | AWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x12C |
DFSDM_ FLT0AWCFR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLRAWHTF[7:0] | CLRAWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x130 |
DFSDM_ FLT0EXMAX |
EXMAX[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMAXCH[2:0] | |||||||||||||||||||||||||
| reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x134 |
DFSDM_ FLT0EXMIN |
EXMIN[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMINCH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
||||||
| 0x138 |
DFSDM_ FLT0CNVTIMR |
CNVCNT[27:0] |
Res. | Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x13C - 0x17C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x180 |
DFSDM_ FLT1CR1 |
Res. | AWFSEL | FAST | Res. | Res. | RCH[2:0] |
Res. | Res. | RDMAEN | Res. | RSYNC | RCONT | RSW START | Res. | Res. | JEXTEN[1:0] | JEXTSEL[4:0] |
Res. | Res. | JDMAEN | JSCAN | JSYNC | Res. | JSW START | DFEN | |||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x184 |
DFSDM_ FLT1CR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDCH[7:0] | EXCH[7:0] |
Res. | Res. | Res. | AWDIE | ROVRIE | JOVRIE | REOCIE | JEOCIE | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x188 |
DFSDM_ FLT1ISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RCIP | JCIP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDF | ROVRF | JOVRF | REOCF | JEOCF |
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x18C |
DFSDM_ FLT1ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLR ROVRF | CLR JOVRF | Res. | Res. |
| reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x190 |
DFSDM_ FLT1JCHGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JCHG[7:0] |
|||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||||||||||||||||
| 0x194 |
DFSDM_ FLT1FCR |
FORD[2:0] | Res. | Res. | Res. | FOSR[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IOSR[7:0] |
||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x198 |
DFSDM_ FLT1JDATAR |
JDATA[23:0] |
Res. | Res. | Res. | Res. | Res. | JDATACH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x19C |
DFSDM_ FLT1RDATAR |
RDATA[23:0] |
Res. | Res. | Res. | RPEND | Res. | RDATA CH[2:0] |
|||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x1A0 |
DFSDM_ FLT1AWHTR |
AWHT[23:0] |
Res. | Res. | Res. | Res. | BKAWH[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x1A4 |
DFSDM_ FLT1AWLTR |
AWLT[23:0] |
Res. | Res. | Res. | Res. | BKAWL[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x1A8 |
DFSDM_ FLT1AWSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWHTF[7:0] | AWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1AC |
DFSDM_ FLT1AWCFR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLRAWHTF[7:0] | CLRAWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1B0 |
DFSDM_ FLT1EXMAX |
EXMAX[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMAXCH[2:0] | |||||||||||||||||||||||||
| reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x1B4 |
DFSDM_ FLT1EXMIN |
EXMIN[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMINCH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
||||||
| 0x1B8 |
DFSDM_ FLT1CNVTIMR |
CNVCNT[27:0] |
Res. | Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x1BC - 0x1FC | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x200 |
DFSDM_ FLT2CR1 |
Res. | AWFSEL | FAST | Res. | Res. | RCH[2:0] |
Res. | Res. | RDMAEN | Res. | RSYNC | RCONT | RSW START | Res. | Res. | JEXTEN[1:0] | JEXTSEL[4:0] |
Res. | Res. | JDMAEN | JSCAN | JSYNC | Res. | JSW START | DFEN | |||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x204 |
DFSDM_ FLT2CR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDCH[7:0] | EXCH[7:0] |
Res. | Res. | Res. | AWDIE | ROVRIE | JOVRIE | REOCIE | JEOCIE | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x208 |
DFSDM_ FLT2ISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RCIP | JCIP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDF | ROVRF | JOVRF | REOCF | JEOCF |
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x20C |
DFSDM_ FLT2ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLR ROVRF | CLR JOVRF | Res. | Res. |
| reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x210 |
DFSDM_ FLT2JCHGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JCHG[7:0] |
|||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||||||||||||||||
| 0x214 |
DFSDM_ FLT2FCR |
FORD[2:0] | Res. | Res. | Res. | FOSR[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IOSR[7:0] |
||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x218 |
DFSDM_ FLT2JDATAR |
JDATA[23:0] |
Res. | Res. | Res. | Res. | Res. | JDATACH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x21C |
DFSDM_ FLT2RDATAR |
RDATA[23:0] |
Res. | Res. | Res. | RPEND | Res. | RDATA CH[2:0] |
|||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x220 |
DFSDM_ FLT2AWHTR |
AWHT[23:0] |
Res. | Res. | Res. | Res. | BKAWH[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x224 |
DFSDM_ FLT2AWLTR |
AWLT[23:0] |
Res. | Res. | Res. | Res. | BKAWL[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x228 |
DFSDM_ FLT2AWSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWHTF[7:0] | AWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x22C |
DFSDM_ FLT2AWCFR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLRAWHTF[7:0] | CLRAWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x230 |
DFSDM_ FLT2EXMAX |
EXMAX[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMAXCH[2:0] | |||||||||||||||||||||||||
| reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x234 |
DFSDM_ FLT2EXMIN |
EXMIN[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMINCH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
||||||
| 0x238 |
DFSDM_ FLT2CNVTIMR |
CNVCNT[27:0] |
Res. | Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x23C - 0x27C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x280 |
DFSDM_ FLT3CR1 |
Res. | AWFSEL | FAST | Res. | Res. | RCH[2:0] |
Res. | Res. | RDMAEN | Res. | RSYNC | RCONT | RSW START | Res. | Res. | JEXTEN[1:0] | JEXTSEL[4:0] |
Res. | Res. | JDMAEN | JSCAN | JSYNC | Res. | JSW START | DFEN | |||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x284 |
DFSDM_ FLT3CR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDCH[7:0] | EXCH[7:0] |
Res. | Res. | Res. | AWDIE | ROVRIE | JOVRIE | REOCIE | JEOCIE | ||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x288 |
DFSDM_ FLT3ISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RCIP | JCIP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWDF | ROVRF | JOVRF | REOCF | JEOCF |
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x28C |
DFSDM_ FLT3ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLR ROVRF | CLR JOVRF | Res. | Res. |
| reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x290 |
DFSDM_ FLT3JCHGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | JCHG[7:0] |
|||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||||||||||||||||
| 0x294 |
DFSDM_ FLT3FCR |
FORD[2:0] | Res. | Res. | Res. | FOSR[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IOSR[7:0] |
||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x298 |
DFSDM_ FLT3JDATAR |
JDATA[23:0] |
Res. | Res. | Res. | Res. | Res. | JDATACH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x29C |
DFSDM_ FLT3RDATAR |
RDATA[23:0] |
Res. | Res. | Res. | RPEND | Res. | RDATA CH[2:0] |
|||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x2A0 |
DFSDM_ FLT3AWHTR |
AWHT[23:0] |
Res. | Res. | Res. | Res. | BKAWH[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x2A4 |
DFSDM_ FLT3AWLTR |
AWLT[23:0] |
Res. | Res. | Res. | Res. | BKAWL[3:0] |
||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x2A8 |
DFSDM_ FLT3AWSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | AWHTF[7:0] | AWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2AC |
DFSDM_ FLT3AWCFR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLRAWHTF[7:0] | CLRAWLTF[7:0] |
||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2B0 |
DFSDM_ FLT3EXMAX |
EXMAX[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMAXCH[2:0] | |||||||||||||||||||||||||
| reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x2B4 |
DFSDM_ FLT3EXMIN |
EXMIN[23:0] |
Res. | Res. | Res. | Res. | Res. | EXMINCH[2:0] | |||||||||||||||||||||||||
| reset value | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
||||||
| 0x2B8 |
DFSDM_ FLT3CNVTIMR |
CNVCNT[27:0] |
Res. | Res. | Res. | Res. | |||||||||||||||||||||||||||
| reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x2BC - 0x3FC | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black & white cameras, X24 and X5 cameras, and it is assumed that all preprocessing like resizing is performed in the camera module.
The digital camera interface uses two clock domains, DCMI_PIXCLK and HCLK. The signals generated with DCMI_PIXCLK are sampled on the rising edge of HCLK once they are stable. An enable signal is generated in the HCLK domain, to indicate that data coming from the camera are stable and can be sampled. The maximum DCMI_PIXCLK period must be higher than 2.5 HCLK periods.
The digital camera interface is a synchronous parallel interface that can receive high-speed (up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock line (DCMI_PIXCLK). The pixel clock has a programmable polarity, so that data can be captured on either the rising or the falling edge of the pixel clock.
The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a general-purpose DMA channel. The image buffer is managed by the DMA, not by the camera interface.
The data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer modes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG bit (bit 3 of DCMI_CR register) must be set.
The data flow is synchronized either by hardware using the optional DCMI_HSYNC (horizontal synchronization) and DCMI_VSYNC (vertical synchronization) signals or by synchronization codes embedded in the data flow.
Figure 110 shows the DCMI block diagram.
| (omitted) |
| (omitted) |
The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register.
The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.
The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused input pins must be connected to ground.
Table 116 shows the DCMI pins.
| Signal name | Signal type | Signal description |
|
|---|---|---|---|
|
8 bits 10 bits 12 bits 14 bits |
DCMI_D[0..7] DCMI_D[0..9] DCMI_D[0..11] DCMI_D[0..13] |
Digital inputs | DCMI data |
| DCMI_PIXCLK | Digital input | Pixel clock |
|
| DCMI_HSYNC | Digital input | Horizontal synchronization / Data valid |
|
| DCMI_VSYNC | Digital input | Vertical synchronization |
|
The data are synchronous with DCMI_PIXCLK and change on the rising/falling edge of the pixel clock depending on the polarity.
The DCMI_HSYNC signal indicates the start/end of a line.
The DCMI_VSYNC signal indicates the start/end of a frame
| (omitted) |
8-bit data
When EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSBs at its input (DCMI_D[0:7]) and stores them as 8-bit data. The DCMI_D[13:8] inputs are ignored. In this case, to capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4th
captured data byte is placed in the MSB position in the 32-bit word. Table 117 gives an example of the positioning of captured data bytes in two 32-bit words.
| Byte address | 31:24 | 23:16 | 15:8 | 7:0 |
|---|---|---|---|---|
| 0 | Dn+3[7:0] | Dn+2[7:0] | Dn+1[7:0] | Dn[7:0] |
| 4 | Dn+7[7:0] | Dn+6[7:0] | Dn+5[7:0] | Dn+4[7:0] |
10-bit data
When EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit data at its input DCMI_D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero. So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 118.
| Byte address | 31:26 | 25:16 | 15:10 | 9:0 |
|---|---|---|---|---|
| 0 | 0 | Dn+1[9:0] | 0 | Dn[9:0] |
| 4 | 0 | Dn+3[9:0] | 0 | Dn+2[9:0] |
12-bit data
When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the 12-bit data at its input DCMI_D[0..11] and stores them as the 12 least significant bits of a 16-
bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 119.
| Byte address | 31:28 | 27:16 | 15:12 | 11:0 |
|---|---|---|---|---|
| 0 | 0 | Dn+1[11:0] | 0 | Dn[11:0] |
| 4 | 0 | Dn+3[11:0] | 0 | Dn+2[11:0] |
14-bit data
When EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the 14-bit data at its input DCMI_D[0..13] and stores them as the 14 least significant bits of a 16-
bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 120.
| Byte address | 31:30 | 29:16 | 15:14 | 13:0 |
|---|---|---|---|---|
| 0 | 0 | Dn+1[13:0] | 0 | Dn[13:0] |
| 4 | 0 | Dn+3[13:0] | 0 | Dn+2[13:0] |
The digital camera interface supports embedded or hardware (DCMI_HSYNC and DCMI_VSYNC) synchronization. When embedded synchronization is used, it is up to the digital camera module to make sure that the 0x00 and 0xFF values are used ONLY for synchronization (not in data). Embedded synchronization codes are supported only for the 8-bit parallel data interface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to “00”).
For compressed data, the DCMI supports only the hardware synchronization mode. In this case, DCMI_VSYNC is used as a start/end of the image, and DCMI_HSYNC is used as a Data Valid signal. Figure 113 shows the corresponding timing diagram.
| (omitted) |
Hardware synchronization mode
In hardware synchronization mode, the two synchronization signals (DCMI_HSYNC/DCMI_VSYNC) are used.
Depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronization periods. The DCMI_HSYNC/DCMI_VSYNC signals act like blanking signals since all the data received during DCMI_HSYNC/DCMI_VSYNC active periods are ignored.
In order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized with the DCMI_VSYNC signal. When the hardware synchronization mode is selected, and
capture is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the deactivation of the DCMI_VSYNC signal (next start of frame).
Transfer can then be continuous, with successive frames transferred by DMA to successive buffers or the same/circular buffer. To allow the DMA management of successive frames, a VSIF (Vertical synchronization interrupt flag) is activated at the end of each frame.
Embedded data synchronization mode
In this synchronization mode, the data flow is synchronized using 32-bit codes embedded in the data flow. These codes use the 0x00/0xFF values that are not used in data anymore. There are 4 types of codes, all with a 0xFF0000XY format. The embedded synchronization codes are supported only in 8-bit parallel data width capture (in the DCMI_CR register, the EDM[1:0] bits should be programmed to “00”). For other data widths, this mode generates unpredictable results and must not be used.
Note: Camera modules can have 8 such codes (in interleaved mode). For this reason, the
interleaved mode is not supported by the camera interface (otherwise, every other
half-frame would be discarded).
Mode 2
Four embedded codes signal the following events
The XY values in the 0xFF0000XY format of the four codes are programmable (see Section 18.7.7: DCMI embedded synchronization code register (DCMI_ESCR)).
A 0xFF value programmed as a “frame end” means that all the unused codes are interpreted as valid frame end codes.
In this mode, once the camera interface has been enabled, the frame capture starts after the first occurrence of the frame end (FE) code followed by a frame start (FS) code.
Mode 1
An alternative coding is the camera mode 1. This mode is ITU656 compatible.
The codes signal another set of events:
This mode can be supported by programming the following codes:
An embedded unmask code is also implemented for frame/line start and frame/line end codes. Using it, it is possible to compare only the selected unmasked bits with the programmed code. You can therefore select a bit to compare in the embedded code and
detect a frame/line start or frame/line end. This means that there can be different codes for the frame/line start and frame/line end with the unmasked bit position remaining the same.
Example
FS = 0xA5
Unmask code for FS = 0x10
In this case the frame start code is embedded in the bit 4 of the frame start code.
This interface supports two types of capture: snapshot (single frame) and continuous grab.
Snapshot mode (single frame)
In this mode, a single frame is captured (CM = ‘1’ in the DCMI_CR register). After the CAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame before sampling the data. The camera interface is automatically disabled (CAPTURE bit cleared in DCMI_CR) after receiving the first complete frame. An interrupt is generated (IT_FRAME) if it is enabled.
In case of an overrun, the frame is lost and the CAPTURE bit is cleared.
| (omitted) |
Continuous grab mode
In this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, the grabbing process starts on the next DCMI_VSYNC or embedded frame start depending on the mode. The process continues until the CAPTURE bit is cleared in DCMI_CR. Once the CAPTURE bit has been cleared, the grabbing process continues until the end of the current frame.
| (omitted) |
In continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate.
Note: In the hardware synchronization mode (ESS = ‘0’ in DCMI_CR), the IT_VSYNC interrupt is
generated (if enabled) even when CAPTURE = ‘0’ in DCMI_CR so, to reduce the frame
capture rate even further, the IT_VSYNC interrupt can be used to count the number of
frames between 2 captures in conjunction with the Snapshot mode. This is not allowed by
embedded data synchronization mode.
With the crop feature, the camera interface can select a rectangular window from the received image. The start (upper left corner) coordinates and size (horizontal dimension in number of pixel clocks and vertical dimension in number of lines) are specified using two 32-
bit registers (DCMI_CWSTRT and DCMI_CWSIZE). The size of the window is specified in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension).
| (omitted) |
These registers specify the coordinates of the starting point of the capture window as a line number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from 0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT value can only be a multiple of 4 (two least significant bits are forced to 0) to allow the correct transfer of data through the DMA.
If the DCMI_VSYNC signal goes active before the number of lines is specified in the DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated when enabled.
| (omitted) |
To allow JPEG image reception, it is necessary to set the JPEG bit in the DCMI_CR register. JPEG images are not stored as lines and frames, so the DCMI_VSYNC signal is used to start the capture while DCMI_HSYNC serves as a data enable signal. The number of bytes in a line may not be a multiple of 4, you should therefore be careful when handling this case since a DMA request is generated each time a complete 32-bit word has been constructed from the captured data. When an end of frame is detected and the 32-bit word to be transferred has not been completely received, the remaining data are padded with ‘0s’ and a DMA request is generated.
The crop feature and embedded synchronization codes cannot be used in the JPEG format.
Input mode
A four-word FIFO is implemented to manage data rate transfers on the AHB. The DCMI features a simple FIFO controller with a read pointer incremented each time the camera interface reads from the AHB, and a write pointer incremented each time the camera interface writes to the FIFO. There is no overrun protection to prevent the data from being overwritten if the AHB interface does not sustain the data transfer rate.
In case of overrun or errors in the synchronization signals, the FIFO is reset and the DCMI interface waits for a new start of frame.
Three types of data are supported:
Compressed data: JPEG
For B&W, YCbCr or RGB data, the maximum input size is 2048 × 2048 pixels. No limit in JPEG compressed mode.
For monochrome, RGB & YCbCr, the frame buffer is stored in raster mode. 32-bit words are used. Only the little endian format is supported.
| (omitted) |
Characteristics:
Table 121 shows how the data are stored.
| Byte address | 31:24 | 23:16 | 15:8 | 7:0 |
|---|---|---|---|---|
| 0 | n + 3 | n + 2 | n + 1 | n |
| 4 | n + 7 | n + 6 | n + 5 | n + 4 |
Characteristics:
The RGB planar format is compatible with standard OS frame buffer display formats.
Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.
The 24 BPP (palletized format) and grayscale formats are not supported. Pixels are stored in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a pixel row. Pixel components are R (red), G (green) and B (blue). All components have the same spatial resolution (4:4:4 format). A frame is stored in a single part, with the components interleaved on a pixel basis.
Table 122 shows how the data are stored.
| Byte address | 31:27 | 26:21 | 20:16 | 15:11 | 10:5 | 4:0 |
|---|---|---|---|---|---|---|
| 0 | Red n + 1 | Green n + 1 | Blue n + 1 | Red n | Green n | Blue n |
| 4 | Red n + 4 | Green n + 3 | Blue n + 3 | Red n + 2 | Green n + 2 | Blue n + 2 |
Characteristics:
Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue and red). Each component is encoded in 8 bits. Luma and chroma are stored together (interleaved) as shown in Table 123.
| Byte address | 31:24 | 23:16 | 15:8 | 7:0 |
|---|---|---|---|---|
| 0 | Y n + 1 | Cr n | Y n | Cb n |
| 4 | Y n + 3 | Cr n + 2 | Y n + 2 | Cb n + 2 |
Characteristics:
Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue and red). In this mode, the chroma information is dropped. Only Luma component of each
pixel , encoded in 8 bits, is stored as shown in Table 124.
The result is a monochrome image having the same resolution as the original YCbCr data.
| Byte address | 31:24 | 23:16 | 15:8 | 7:0 |
|---|---|---|---|---|
| 0 | Y n + 3 | Y n + 2 | Y n + 1 | Y n |
| 4 | Y n + 7 | Y n + 6 | Y n + 5 | Y n + 4 |
This is a modification of the previous reception modes, being applicable to monochrome, RGB or Y extraction modes.
This mode allows to only store a half resolution image. It is selected through OELS and LSM control bits.
Five interrupts are generated. All interrupts are maskable by software. The global interrupt (IT_DCMI) is the OR of all the individual interrupts. Table 125 gives the list of all interrupts.
| Interrupt name | Interrupt event |
|---|---|
| IT_LINE | Indicates the end of line |
| IT_FRAME | Indicates the end of frame capture |
| IT_OVR | indicates the overrun of data reception |
| IT_VSYNC | Indicates the synchronization frame |
| IT_ERR | Indicates the detection of an error in the embedded synchronization frame detection |
| IT_DCMI | Logic OR of the previous interrupts |
All DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OELS | LSM | OEBS | BSM[1:0] |
Res. | ENABLE | Res. | Res. | EDM[1:0] | FCRC[1:0] | VSPOL | HSPOL | PCKPOL | ESS | JPEG | CROP | CM | CAPTURE |
|||
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | OELS: Odd/Even Line Select (Line Select Start) |
|
This bit works in conjunction with LSM field (LSM = 1) |
|
| Bit 19 | LSM: Line Select mode |
|
0: Interface captures all received lines |
|
| Bit 18 | OEBS: Odd/Even Byte Select (Byte Select Start) |
|
This bit works in conjunction with BSM field (BSM <> 00) |
|
| Bits 17:16 | BSM[1:0]: Byte Select mode |
|
00: Interface captures all received data This mode only work for EDM[1:0]=00. For all other EDM values, this bit |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | ENABLE: DCMI enable |
|
0: DCMI disabled The DCMI configuration registers should be programmed correctly before |
|
| Bits 13:12 | Reserved, must be kept at reset value. |
| Bits 11:10 | EDM[1:0]: Extended data mode |
|
00: Interface captures 8-bit data on every pixel clock |
|
| Bits 9:8 | FCRC[1:0]: Frame capture rate control |
|
These bits define the frequency of frame capture. They are meaningful only in Continuous grab mode. They are ignored in snapshot mode. |
|
| Bit 7 | VSPOL: Vertical synchronization polarity |
|
This bit indicates the level on the DCMI_VSYNC pin when the data are not valid on the parallel interface. |
|
| Bit 6 | HSPOL: Horizontal synchronization polarity |
|
This bit indicates the level on the DCMI_HSYNC pin when the data are not valid on the parallel interface. |
|
| Bit 5 | PCKPOL: Pixel clock polarity |
|
This bit configures the capture edge of the pixel clock |
|
| Bit 4 | ESS: Embedded synchronization select |
|
0: Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals. Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS This bit is disabled in JPEG mode. |
|
| Bit 3 | JPEG: JPEG format |
|
0: Uncompressed video format |
|
| Bit 2 | CROP: Crop feature |
|
0: The full image is captured. In this case the total number of bytes in an image frame should be a multiple of 4 |
|
| Bit 1 | CM: Capture mode |
|
0: Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA. |
|
| Bit 0 | CAPTURE: Capture enable |
|
0: Capture disabled. The DMA controller and all DCMI configuration registers should be |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FNE | VSYNC | HSYNC |
| r | r | r |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | FNE: FIFO not empty |
|
This bit gives the status of the FIFO 1: FIFO contains valid data 0: FIFO empty |
|
| Bit 1 | VSYNC: |
|
This bit gives the state of the DCMI_VSYNC pin with the correct programmed polarity. |
|
| Bit 0 | HSYNC: |
|
This bit gives the state of the DCMI_HSYNC pin with the correct programmed polarity. |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE _RIS |
VSYNC _RIS |
ERR _RIS |
OVR _RIS |
FRAME _RIS |
| r | r | r | r | r |
DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value.
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | LINE_RIS: Line raw interrupt status |
|
This bit gets set when the DCMI_HSYNC signal changes from the inactive state to the active state. It goes high even if the line is not valid. |
|
| Bit 3 | VSYNC_RIS: DCMI_VSYNC raw interrupt status |
|
This bit is set when the DCMI_VSYNC signal changes from the inactive state to the active state. |
|
| Bit 2 | ERR_RIS: Synchronization error raw interrupt status |
|
0: No synchronization error detected
This bit is available only in embedded synchronization mode.
|
|
| Bit 1 | OVR_RIS:Overrun raw interrupt status |
|
0: No data buffer overrun occurred |
|
| Bit 0 | FRAME_RIS: Capture complete raw interrupt status |
|
0: No new capture 1: A frame has been captured. |
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE _IE |
VSYNC _IE |
ERR _IE |
OVR _IE |
FRAME _IE |
| rw | rw | rw | rw | rw |
The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write.
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | LINE_IE: Line interrupt enable |
|
0: No interrupt generation when the line is received |
|
| Bit 3 | VSYNC_IE: DCMI_VSYNC interrupt enable |
|
0: No interrupt generation |
|
| Bit 2 | ERR_IE: Synchronization error interrupt enable |
|
0: No interrupt generation
This bit is available only in embedded synchronization mode.
|
|
| Bit 1 | OVR_IE: Overrun interrupt enable |
|
0: No interrupt generation |
|
| Bit 0 | FRAME_IE: Capture complete interrupt enable |
|
0: No interrupt generation |
This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE _MIS |
VSYNC _MIS |
ERR _MIS |
OVR _MIS |
FRAME _MIS |
| r | r | r | r | r |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | LINE_MIS: Line masked interrupt status |
|
This bit gives the status of the masked line interrupt |
|
| Bit 3 | VSYNC_MIS: VSYNC masked interrupt status |
|
This bit gives the status of the masked VSYNC interrupt |
|
| Bit 2 | ERR_MIS: Synchronization error masked interrupt status |
|
This bit gives the status of the masked synchronization error interrupt
This bit is available only in embedded synchronization mode.
|
|
| Bit 1 | OVR_MIS: Overrun masked interrupt status |
|
This bit gives the status of the masked overflow interrupt |
|
| Bit 0 | FRAME_MIS: Capture complete masked interrupt status |
|
This bit gives the status of the masked capture complete interrupt |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE _ISC |
VSYNC _ISC |
ERR _ISC |
OVR _ISC |
FRAME _ISC |
| w | w | w | w | w |
The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | LINE_ISC: line interrupt status clear |
|
Writing a ‘1’ into this bit clears LINE_RIS in the DCMI_RIS register |
|
| Bit 3 | VSYNC_ISC: Vertical Synchronization interrupt status clear |
|
Writing a ‘1’ into this bit clears the VSYNC_RIS bit in DCMI_RIS |
|
| Bit 2 | ERR_ISC: Synchronization error interrupt status clear |
|
Writing a ‘1’ into this bit clears the ERR_RIS bit in DCMI_RIS
This bit is available only in embedded synchronization mode.
|
|
| Bit 1 | OVR_ISC: Overrun interrupt status clear |
|
Writing a ‘1’ into this bit clears the OVR_RIS bit in DCMI_RIS |
|
| Bit 0 | FRAME_ISC: Capture complete interrupt status clear |
|
Writing a ‘1’ into this bit clears the FRAME_RIS bit in DCMI_RIS |
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FEC[7:0]] | LEC[7:0] |
LSC[7:0] | FSC[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | FEC[7:0]: Frame end delimiter code |
|
This byte specifies the code of the frame end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FEC. |
|
| Bits 23:16 | LEC[7:0]: Line end delimiter code |
|
This byte specifies the code of the line end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, LEC. |
|
| Bits 15:8 | LSC[7:0]: Line start delimiter code |
|
This byte specifies the code of the line start delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, LSC. |
|
| Bits 7:0 | FSC[7:0]: Frame start delimiter code |
|
This byte specifies the code of the frame start delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FSC. |
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FEU[7:0] | LEU[7:0] |
LSU[7:0] | FSU[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | FEU[7:0]: Frame end delimiter unmask |
|
This byte specifies the mask to be applied to the code of the frame end delimiter. |
|
| Bits 23:16 | LEU[7:0]: Line end delimiter unmask |
|
This byte specifies the mask to be applied to the code of the line end delimiter. |
|
| Bits 15:8 | LSU[7:0]: Line start delimiter unmask |
|
This byte specifies the mask to be applied to the code of the line start delimiter. |
|
| Bits 7:0 | FSU[7:0]: Frame start delimiter unmask |
|
This byte specifies the mask to be applied to the code of the frame start delimiter. |
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | VST[12:0] |
Res. | Res. | HOFFCNT[13:0] |
|||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bits 28:16 | VST[12:0]: Vertical start line count |
|
The image capture starts with this line number. Previous line data are ignored. |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | HOFFCNT[13:0]: Horizontal offset count |
|
This value gives the number of pixel clocks to count before starting a capture. |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | VLINE[13:0] |
Res. | Res. | CAPCNT[13:0] |
||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:16 | VLINE[13:0]: Vertical line count |
|
This value gives the number of lines to be captured from the starting point. |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | CAPCNT[13:0]: Capture count |
|
This value gives the number of pixel clocks to be captured from the starting point on the same line. It value should corresponds to word-aligned data for different widths of parallel interfaces. |
Address offset: 0x28
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Byte3[7:0] | Byte2[7:0] |
Byte1[7:0] | Byte0[7:0] |
||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:24 | Byte3[7:0]: Data byte 3 |
| Bits 23:16 | Byte2[7:0]: Data byte 2 |
| Bits 15:8 | Byte1[7:0]: Data byte 1 |
| Bits 7:0 | Byte0[7:0]: Data byte 0 |
The digital camera Interface packages all the received data in 32-bit format before requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA transfers and avoid DMA overrun conditions.
Table 126 summarizes the DCMI registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | DCMI_CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OELS | LSM | OEBS | BSM |
Res. | ENABLE | Res. | Res. | EDM | FCRC |
VSPOL | HSPOL | PCKPOL | ESS | JPEG | CROP | CM | CAPTURE | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x04 | DCMI_SR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FNE | VSYNC | HSYNC |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x08 | DCMI_RIS |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE_RIS | VSYNC_RIS | ERR_RIS | OVR_RIS | FRAME_RIS |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0C | DCMI_IER |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE_IE | VSYNC_IE | ERR_IE | OVR_IE | FRAME_IE |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x10 | DCMI_MIS |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE_MIS | VSYNC_MIS | ERR_MIS | OVR_MIS | FRAME_MIS |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x14 | DCMI_ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LINE_ISC | VSYNC_ISC | ERR_ISC | OVR_ISC | FRAME_ISC |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x18 | DCMI_ESCR | FEC | LEC | LSC | FSC |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1C | DCMI_ESUR | FEU | LEU | LSU | FSU |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x20 | DCMI_CWSTRT |
Res. | Res. | Res. | VST[12:0 |
Res. | Res. | HOFFCNT[13:0] |
|||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x24 | DCMI_CWSIZE |
Res. | Res. | VLINE13:0] |
Res. | Res. | CAPCNT[13:0] |
||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x28 | DCMI_DR | Byte3 | Byte2 | Byte1 | Byte0 |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
This section applies to the whole STM32F76xxx and STM32F77xxx devices, unless otherwise specified.
The LCD-TFT (liquid crystal display - thin film transistor) display controller provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD and TFT panels.
The block diagram of the LTDC is shown in Figure 119: LTDC block diagram.
| (omitted) |
Layer FIFO: One FIFO 64x32-bit per layer.
PFC: pixel format converter, performing the pixel format conversion from the selected input pixel format of a layer to words.
AHB interface: for data transfer from memories to the FIFO.
Blending, dithering unit and timings generator: Refer to Section 19.4.1 and Section 19.4.2.
Table 127 summarizes the LTDC signal interface.
| LCD-TFT signals | I/O | Description |
|---|---|---|
| LCD_CLK | O | Clock output |
| LCD_HSYNC | O | Horizontal synchronization |
| LCD_VSYNC | O | Vertical synchronization |
| LCD_DE | O | Not data enable |
| LCD_R[7:0] | O | Data: 8-bit red data |
| LCD_G[7:0] | O | Data: 8-bit green data |
| LCD_B[7:0] | O | Data: 8-bit blue data |
The LTDC-TFT controller pins must be configured by the user application. The unused pins can be used for other purposes.
For LTDC outputs up to 24-bit (RGB888), if less than 8 bpp are used to output for example RGB565 or RGB666 to interface on 16- or 18-bit displays, the RGB display data lines must be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in the case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display R[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller LCD_R[7:3], LCD_G[7:2] and LCD_B[7:3].
The LCD-TFT controller peripheral uses 3 clock domains:
AHB clock domain (HCLK)
This domain contains the LCD-TFT AHB master interface for data transfer from the memories to the Layer FIFO and the frame buffer configuration register
APB2 clock domain (PCLK2):
This domain contains the global configuration registers and the interrupt register.
Pixel clock domain (LCD_CLK)
This domain contains the pixel data generation, the layer configuration register as well as the LCD-TFT interface signal generator. The LCD_CLK output should be configured following the panel requirements. The LCD_CLK is generated from a specific PLL output (refer to the reset and clock control section).
Table 128 summarizes the clock domain for each register.
| LTDC register | Clock domain |
|---|---|
| LTDC_LxCR |
HCLK |
| LTDC_LxCFBAR |
|
| LTDC_LxCFBLR |
|
| LTDC_LxCFBLNR |
|
| LTDC_SRCR |
PCLK2 |
| LTDC_IER |
|
| LTDC_ISR |
|
| LTDC_ICR | |
| LTDC_SSCR |
Pixel clock (LCD_CLK) |
| LTDC_BPCR |
|
| LTDC_AWCR |
|
| LTDC_TWCR |
|
| LTDC_GCR |
|
| LTDC_BCCR |
|
| LTDC_LIPCR |
|
| LTDC_CPSR |
|
| LTDC_CDSR |
|
| LTDC_LxWHPCR |
|
| LTDC_LxWVPCR |
|
| LTDC_LxCKCR |
|
| LTDC_LxPFCR |
|
| LTDC_LxCACR |
|
| LTDC_LxDCCR |
|
| LTDC_LxBFCR |
|
| LTDC_LxCLUTWR |
Care must be taken while accessing the LTDC registers, the APB2 bus is stalled during:
For registers on PCLK2 clock domain, APB2 bus is stalled for 6 PCKL2 periods during the register write accesses, and for 7 PCKL2 periods during Read accesses.
The LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR register. It resets the three clock domains.
The LCD-TFT controller provides flexible configurable parameters. It can be enabled or disabled through the LTDC_GCR register.
Synchronous timings
Figure 120 presents the configurable timing parameters generated by the synchronous timings generator block presented in the block diagram Figure 119. It generates the
horizontal and vertical synchronization timings panel signals, the pixel clock and the data enable signals.
| (omitted) |
Note: The HBP and HFP are respectively the horizontal back porch and front porch period.
The VBP and the VFP are respectively the vertical back porch and front porch period.
The LCD-TFT programmable synchronous timings are:
Note: When the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first
horizontal synchronization pixel in the vertical synchronization area and following the back
porch, active data display area and the front porch.
When the LTDC is disabled, the timing generator block is reset to X = total width - 1, Y = total height - 1 and held the last pixel before the vertical synchronization phase and the FIFO are flushed. Therefore only blanking data is output continuously.
Example of synchronous timings configuration
TFT-LCD timings (must be extracted from panel datasheet):
The programmed values in the LTDC timings registers are:
Programmable polarity
The horizontal and vertical synchronization, data enable and pixel clock output signals polarity can be programmed to active high or active low through the LTDC_GCR register.
Background color
A constant background color (RGB888) can programmed through the LTDC_BCCR register. It is used for blending with the bottom layer.
Dithering
The dithering pseudo-random technique using an LFSR is used to add a small random value (threshold) to each pixel color channel (R, G or B) value, thus rounding up the MSB in some cases when displaying a 24-bit data on 18-bit display. Thus the Dithering technique is used to round data which is different from one frame to the other.
The dithering pseudo-random technique is the same as comparing LSBs against a threshold value and adding a 1 to the MSB part only, if the LSB part is >= the threshold. The LSBs are typically dropped once dithering was applied.
The width of the added pseudo-random value is 2 bits for each color channel: 2 bits for red, 2 bits for green and 2 bits for blue.
Once the LCD-TFT controller is enabled, the LFSR starts running with the first active pixel and it is kept running even during blanking periods and when dithering is switched off. If the LTDC is disabled, the LFSR is reset.
The dithering can be switched On and Off on the fly through the LTDC_GCR register.
Reload shadow registers
Some configuration registers are shadowed. The shadow registers values can be reloaded immediately to the active registers when writing to these registers or at the beginning of the vertical blanking period following the configuration in the LTDC_SRCR register. If the immediate reload configuration is selected, the reload should be only activated when all new registers have been written.
The shadow registers should not be modified again before the reload has been done. Reading from the shadow registers returns the actual active value. The new written value can only be read after the reload has taken place.
A register reload interrupt can be generated if enabled in the LTDC_IER register.
The shadowed registers are all the layer1 and layer2 registers except the LTDC_LxCLUTWR register.
Interrupt generation event
Refer to Section 19.5: LTDC interrupts for interrupt configuration.
Up to two layers can be enabled, disabled and configured separately. The layer display order is fixed and it is bottom up. If two layers are enabled, the layer2 is the top displayed window.
Windowing
Every layer can be positioned and resized and it must be inside the active display area.
The window position and size are configured through the top-left and bottom-right X/Y positions and the internal timing generator that includes the synchronous, back porch size and the active data area. Refer to LTDC_LxWHPCR and LTDC_WVPCR registers.
The programmable layer position and size defines the first/last visible pixel of a line and the first/last visible line in the window. It allows to display either the full image frame or only a part of the image frame. Refer to Figure 121.
| (omitted) |
Pixel input format
The programmable pixel format is used for the data stored in the frame buffer of a layer.
Up to 8 input pixel formats can be configured for every layer through the LTDC_LxPFCR register
The pixel data is read from the frame buffer and then transformed to the internal 8888 (ARGB) format as follows: components having a width of less than 8 bits get expanded to 8 bits by bit replication. The selected bit range is concatenated multiple times until it is longer than 8 bits. Of the resulting vector, the 8 MSB bits are chosen. Example: 5 bits of an RGB565 red channel become (bit positions): 43210432 (the 3 LSBs are filled with the 3 MSBs of the 5 bits)
Table 129 describes the pixel data mapping depending on the selected format.
|
ARGB8888
|
|||
|
@+3 Ax[7:0] |
@+2 Rx[7:0] |
@+1 Gx[7:0] |
@ Bx[7:0] |
|
@+7 Ax+1[7:0] |
@+6 Rx+1[7:0] |
@+5 Gx+1[7:0] |
@+4 Bx+1[7:0] |
|
RGB888
|
|||
|
@+3 Bx+1[7:0] |
@+2 Rx[7:0] |
@+1 Gx[7:0] |
@ Bx[7:0] |
|
@+7 Gx+2[7:0] |
@+6 Bx+2[7:0] |
@+5 Rx+1[7:0] |
@+4 Gx+1[7:0] |
|
RGB565
|
|||
|
@+3 Rx+1[4:0] Gx+1[5:3] |
@+2 Gx+1[2:0] Bx+1[4:0] |
@+1 Rx[4:0] Gx[5:3] |
@ Gx[2:0] Bx[4:0] |
|
@+7 Rx+3[4:0] Gx+3[5:3] |
@+6 Gx+3[2:0] Bx+3[4:0] |
@+5 Rx+2[4:0] Gx+2[5:3] |
@+4 Gx+2[2:0] Bx+2[4:0] |
| ARGB1555 | |||
|
@+3 Ax+1[0]Rx+1[4:0] Gx+1[4:3] |
@+2 Gx+1[2:0] Bx+1[4:0] |
@+1 Ax[0] Rx[4:0] Gx[4:3] |
@ Gx[2:0] Bx[4:0] |
|
@+7 Ax+3[0]Rx+3[4:0] Gx+3[4:3] |
@+6 Gx+3[2:0] Bx+3[4:0] |
@+5 Ax+2[0]Rx+2[4:0]Gx+2[4: |
@+4 Gx+2[2:0] Bx+2[4:0] |
|
ARGB4444
|
|||
|
@+3 Ax+1[3:0]Rx+1[3:0] |
@+2 Gx+1[3:0] Bx+1[3:0] |
@+1 Ax[3:0] Rx[3:0] |
@ Gx[3:0] Bx[3:0] |
|
@+7 Ax+3[3:0]Rx+3[3:0] |
@+6 Gx+3[3:0] Bx+3[3:0] |
@+5 Ax+2[3:0]Rx+2[3:0] |
@+4 Gx+2[3:0] Bx+2[3:0] |
|
L8
|
|||
|
@+3 Lx+3[7:0] |
@+2 Lx+2[7:0] |
@+1 Lx+1[7:0] |
@ Lx[7:0] |
|
@+7 Lx+7[7:0] |
@+6 Lx+6[7:0] |
@+5 Lx+5[7:0] |
@+4 Lx+4[7:0] |
|
AL44
|
|||
|
@+3 Ax+3[3:0] Lx+3[3:0] |
@+2 Ax+2[3:0] Lx+2[3:0] |
@+1 Ax+1[3:0] Lx+1[3:0] |
@ Ax[3:0] Lx[3:0] |
|
@+7 Ax+7[3:0] Lx+7[3:0] |
@+6 Ax+6[3:0] Lx+6[3:0] |
@+5 Ax+5[3:0] Lx+5[3:0] |
@+4 Ax+4[3:0] Lx+4[3:0] |
|
AL88
|
|||
|
@+3 Ax+1[7:0] |
@+2 Lx+1[7:0] |
@+1 Ax[7:0] |
@ Lx[7:0] |
|
@+7 Ax+3[7:0] |
@+6 Lx+3[7:0] |
@+5 Ax+2[7:0] |
@+4 Lx+2[7:0] |
Color look-up table (CLUT)
The CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and it is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel format.
First, the CLUT has to be loaded with the R, G and B values that replace the original R, G, B values of that pixel (indexed color). Each color (RGB value) has its own address which is the position within the CLUT.
The R, G and B values and their own respective address are programmed through the LTDC_LxCLUTWR register.
Color frame buffer address
Every layer has a start address for the color frame buffer configured through the LTDC_LxCFBAR register.
When a layer is enabled, the data is fetched from the color frame buffer.
Color frame buffer length
Every layer has a total line length setting for the color frame buffer in bytes and a number of lines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR register respectively.
The line length and the number of lines settings are used to stop the prefetching of data to the layer FIFO at the end of the frame buffer.
Color frame buffer pitch
Every layer has a configurable pitch for the color frame buffer, which is the distance between the start of one line and the beginning of the next line in bytes. It is configured through the LTDC_LxCFBLR register.
Layer blending
The blending is always active and the two layers can be blended following the blending factors configured through the LTDC_LxBFCR register.
The blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is blended with the Background color, then the layer2 is blended with the result of blended color of layer1 and the background. Refer to Figure 122.
| (omitted) |
Default color
Every layer can have a default color in the format ARGB which is used outside the defined layer window or when a layer is disabled.
The default color is configured through the LTDC_LxDCCR register.
The blending is always performed between the two layers even when a layer is disabled. To avoid displaying the default color when a layer is disabled, keep the blending factors of this layer in the LTDC_LxBFCR register to their reset value.
Color keying
A color key (RGB) can be configured to be representative for a transparent pixel.
If the color keying is enabled, the current pixels (after format conversion and before CLUT respectively blending) are compared to the color key. If they match for the programmed RGB value, all channels (ARGB) of that pixel are set to 0.
The color key value can be configured and used at run-time to replace the pixel RGB value.
The color keying is enabled through the LTDC_LxCKCR register.
The color keying is configured through the LTDC_LxCKCR register. The programmed value depends on the pixel format as it is compared to current pixel after pixel format conversion to ARGB888.
Example: if the a mid-yellow color (50% red + 50% green) is used as the transparent color key:
The LTDC provides four maskable interrupts logically ORed to two interrupt vectors.
The interrupt sources can be enabled or disabled separately through the LTDC_IER register. Setting the appropriate mask bit to 1 enables the corresponding interrupt.
The two interrupts are generated on the following events:
Those interrupts events are connected to the NVIC controller as described in Figure 123.
| (omitted) |
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Line | LIF | LIE |
| Register reload | RRIF | RRIEN |
| FIFO underrun | FUDERRIF | FUDERRIE |
| Transfer error | TERRIF | TERRIE |
Note: All layer’s registers are shadowed. Once a register is written, it must not be modified again
before the reload has been done. Thus, a new write to the same register overrides the
previous configuration if not yet reloaded.
This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure 120 and Section 19.4:
LTDC programmable parameters for an example of configuration.
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | HSW[11:0] |
Res. | Res. | Res. | Res. | Res. | VSH[10:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | HSW[11:0]: horizontal synchronization width (in units of pixel clock period) |
|
These bits define the number of Horizontal Synchronization pixel minus 1. |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | VSH[10:0]: vertical synchronization height (in units of horizontal scan line) |
|
These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. |
This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNC width + HBP - 1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNC height + VBP - 1). Refer to Figure 120 and Section 19.4: LTDC programmable parameters for an example of configuration.
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | AHBP[11:0] |
Res. | Res. | Res. | Res. | Res. | AVBP[10:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | AHBP[11:0]: accumulated horizontal back porch (in units of pixel clock period) |
|
These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1. |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | AVBP[10:0]: accumulated Vertical back porch (in units of horizontal scan line) |
|
These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1. |
This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width + HBP + active width - 1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNC height + BVBP + active height - 1). Refer to Figure 120 and Section 19.4: LTDC
programmable parameters for an example of configuration.
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | AAW[11:0] |
Res. | Res. | Res. | Res. | Res. | AAH[10:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | AAW[11:0]: accumulated active width (in units of pixel clock period) |
|
These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1. |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | AAH[10:0]: accumulated active height (in units of horizontal scan line) |
|
These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel. Refer to device datasheet for maximum active height supported following maximum pixel clock. |
This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNC width + HBP + active width + HFP - 1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNC height + BVBP + active height + VFP - 1). Refer to Figure 120 and Section 19.4: LTDC programmable parameters for an example of configuration.
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | TOTALW[11:0] |
Res. | Res. | Res. | Res. | Res. | TOTALH[10:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | TOTALW[11:0]: total width (in units of pixel clock period) |
|
These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | TOTALH[10:0]: total height (in units of horizontal scan line) |
|
These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. |
This register defines the global configuration of the LCD-TFT controller.
Address offset: 0x18
Reset value: 0x0000 2220
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HSPOL | VSPOL | DEPOL | PCPOL | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DEN |
Res. | DRW[2:0] | Res. | DGW[2:0] | Res. | DBW[2:0] | Res. | Res. | Res. | LTDCEN |
||||||
| rw | rw | rw | rw | rw |
r | r | r | r | r | r | r | r | r | rw | |||||||||||||||||
| Bit 31 | HSPOL: horizontal synchronization polarity |
|
This bit is set and cleared by software. |
|
| Bit 30 | VSPOL: vertical synchronization polarity |
|
This bit is set and cleared by software. |
|
| Bit 29 | DEPOL: not data enable polarity |
|
This bit is set and cleared by software. |
|
| Bit 28 | PCPOL: pixel clock polarity |
|
This bit is set and cleared by software. |
|
| Bits 27:17 | Reserved, must be kept at reset value. |
| Bit 16 | DEN: dither enable |
|
This bit is set and cleared by software. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:12 | DRW[2:0]: dither red width |
|
These bits return the Dither Red Bits. |
|
| Bit 11 | Reserved, must be kept at reset value. |
| Bits 10:8 | DGW[2:0]: dither green width |
|
These bits return the dither green bits. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bits 6:4 | DBW[2:0]: dither blue width |
|
These bits return the dither blue bits. |
|
| Bits 3:1 | Reserved, must be kept at reset value. |
| Bit 0 | LTDCEN: LCD-TFT controller enable |
|
This bit is set and cleared by software. |
This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBR | IMR |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | VBR: vertical blanking reload |
|
This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). |
|
| Bit 0 | IMR: immediate reload |
|
This bit is set by software and cleared only by hardware after reload. |
Note: The shadow registers read back the active values. Until the reload has been done, the 'old'
value is read.
This register defines the background color (RGB888).
Address offset: 0x2C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BCRED[7:0] |
BCGREEN[7:0] | BCBLUE[7:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | BCRED[7:0]: background color red value |
|
These bits configure the background red value. |
|
| Bits 15:8 | BCGREEN[7:0]: background color green value |
|
These bits configure the background green value. |
|
| Bits 7:0 | BCBLUE[7:0]: background color blue value |
|
These bits configure the background blue value. |
This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
Address offset: 0x34
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIE | TERRIE | FUIE | LIE |
| rw | rw | rw | rw |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | RRIE: register reload interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 2 | TERRIE: transfer error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 1 | FUIE: FIFO underrun interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | LIE: line interrupt enable |
|
This bit is set and cleared by software. |
This register returns the interrupt status flag.
Address offset: 0x38
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIF | TERRIF | FUIF | LIF |
| r | r | r | r |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | RRIF: register reload interrupt flag |
|
0: no register reload interrupt generated |
|
| Bit 2 | TERRIF: transfer error interrupt flag |
|
0: no transfer error interrupt generated |
|
| Bit 1 | FUIF: FIFO underrun interrupt flag |
|
0: no FIFO underrun interrupt generated. |
|
| Bit 0 | LIF: line interrupt flag |
|
0: no line interrupt generated |
Address offset: 0x3C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRRIF | CTERRIF | CFUIF | CLIF |
| w | w | w | w |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | CRRIF: clears register reload interrupt flag |
|
0: no effect |
|
| Bit 2 | CTERRIF: clears the transfer error interrupt flag |
|
0: no effect |
|
| Bit 1 | CFUIF: clears the FIFO underrun interrupt flag |
|
0: no effect |
|
| Bit 0 | CLIF: clears the line interrupt flag |
|
0: no effect |
This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure 120.
Address offset: 0x40
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | LIPOS[10:0] |
||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||
| Bits 31:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | LIPOS[10:0]: line interrupt position |
|
These bits configure the line interrupt position. |
Address offset: 0x44
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CXPOS[15:0] |
CYPOS[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | CXPOS[15:0]: current X position |
|
These bits return the current X position. |
|
| Bits 15:0 | CYPOS[15:0]: current Y position |
|
These bits return the current Y position. |
This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals.
Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.
Address offset: 0x48
Reset value: 0x0000 000F
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSYNCS | VSYNCS | HDES | VDES |
| r | r | r | r |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | HSYNCS: horizontal synchronization display status |
|
0: active low |
|
| Bit 2 | VSYNCS: vertical synchronization display status |
|
0: active low |
|
| Bit 1 | HDES: horizontal data enable display status |
|
0: active low 1: active high |
|
| Bit 0 | VDES: vertical data enable display status |
|
0: active low 1: active high |
Note: The returned status does not depend on the configured polarity in the LTDC_GCR register,
instead it returns the current active display phase.
Address offset: 0x84 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLUTEN | Res. | Res. | COLKEN | LEN |
| rw | rw | rw |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | CLUTEN: color look-up table enable |
|
This bit is set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | COLKEN: color keying enable |
|
This bit is set and cleared by software. |
|
| Bit 0 | LEN: layer enable |
|
This bit is set and cleared by software. |
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window.
The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register.
The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register.
Address offset: 0x88 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | WHSPPOS[11:0] |
Res. | Res. | Res. | Res. | WHSTPOS[11:0] |
||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | WHSPPOS[11:0]: window horizontal stop position |
|
These bits configure the last visible pixel of a line of the layer window. |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | WHSTPOS[11:0]: window horizontal start position |
|
These bits configure the first visible pixel of a line of the layer window. |
Example:
The LTDC_BPCR register is configured to 0x000E0005 (AHBP[11:0] is 0xE) and the LTDC_AWCR register is configured to 0x028E01E5 (AAW[11:0] is 0x28E). To configure the horizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the active data area:
This register defines the vertical position (first and last line) of the layer1 or 2 window.
The first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the register LTDC_BPCR register.
The last visible line of a frame is the programmed value of AAH[10:0] bits in the LTDC_AWCR register.
Address offset: 0x8C + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | WVSPPOS[10:0] |
Res. | Res. | Res. | Res. | Res. | WVSTPOS[10:0] |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bits 26:16 | WVSPPOS[10:0]: window vertical stop position |
|
These bits configure the last visible line of the layer window. WVSPPOS[10:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register). |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | WVSTPOS[10:0]: window vertical start position |
|
These bits configure the first visible line of the layer window. |
Example:
The LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the LTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5).
To configure the vertical position of a window size of 630x460, with vertical start offset of 8 lines in the active data area:
This register defines the color key value (RGB), that is used by the color keying.
Address offset: 0x90 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKRED[7:0] |
CKGREEN[7:0] | CKBLUE[7:0] |
|||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | CKRED[7:0]: color key red value |
| Bits 15:8 | CKGREEN[7:0]: color key green value |
| Bits 7:0 | CKBLUE[7:0]: color key blue value |
This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
Address offset: 0x94 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PF[2:0] |
||
| rw | rw | rw | |||||||||||||||||||||||||||||
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | PF[2:0]: pixel format |
|
These bits configure the pixel format |
This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
Address offset: 0x98 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 00FF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CONSTA[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | CONSTA[7:0]: constant alpha |
|
These bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware. |
This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
Address offset: 0x9C + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DCALPHA[7:0] | DCRED[7:0] |
DCGREEN[7:0] | DCBLUE[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | DCALPHA[7:0]: default color alpha |
|
These bits configure the default alpha value. |
|
| Bits 23:16 | DCRED[7:0]: default color red |
|
These bits configure the default red value. |
|
| Bits 15:8 | DCGREEN[7:0]: default color green |
|
These bits configure the default green value. |
|
| Bits 7:0 | DCBLUE[7:0]: default color blue |
|
These bits configure the default blue value. |
This register defines the blending factors F1 and F2.
The general blending formula is: BC = BF1 x C + BF2 x Cs
Address offset: 0xA0 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0607
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | BF1[2:0] | Res. | Res. | Res. | Res. | Res. | BF2[2:0] |
||||
| rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||||
| Bits 31:11 | Reserved, must be kept at reset value. |
| Bits 10:8 | BF1[2:0]: blending factor 1 |
|
These bits select the blending factor F1. |
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | BF2[2:0]: blending factor 2 |
|
These bits select the blending factor F2 |
Note: The constant alpha value, is the programmed value in the LxCACR register divided by 255
by hardware.
Example: Only layer1 is enabled, BF1 configured to constant alpha. BF2 configured to
1 - constant alpha. The constant alpha programmed in the LxCACR register is 240 (0xF0).
Thus, the constant alpha value is 240/255 = 0.94. C: current layer color is 128.
Cs: background color is 48. Layer1 is blended with the background color.
BC = constant alpha x C + (1 - Constant Alpha) x Cs = 0.94 x 128 + (1- 0.94) x 48 = 123.
This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
Address offset: 0xAC + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CFBADD[31:16] |
CFBADD[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | CFBADD[31:0]: color frame buffer start address |
|
These bits define the color frame buffer start address. |
This register defines the color frame buffer line length and pitch.
Address offset: 0xB0 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CFBP[12:0] |
Res. | Res. | Res. | CFBLL[12:0] |
||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bits 28:16 | CFBP[12:0]: color frame buffer pitch in bytes |
|
These bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes. |
|
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | CFBLL[12:0]: color frame buffer line length |
|
These bits define the length of one line of pixels in bytes + 3. |
Example:
This register defines the number of lines in the color frame buffer.
Address offset: 0xB4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | CFBLNBR[10:0] |
||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||
| Bits 31:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | CFBLNBR[10:0]: frame buffer line number |
|
These bits define the number of lines in the frame buffer that corresponds to the active high width. |
Note: The number of lines and line length settings define how much data is fetched per frame for
every layer. If it is configured to less bytes than required, a FIFO underrun interrupt will be
generated if enabled.
The start address and pitch settings on the other hand define the correct start of every line in
memory.
This register defines the CLUT address and the RGB value.
Address offset: 0xC4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLUTADD[7:0] | RED[7:0] |
GREEN[7:0] | BLUE[7:0] |
||||||||||||||||||||||||||||
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:24 | CLUTADD[7:0]: CLUT address |
|
These bits configure the CLUT address (color position within the CLUT) of each RGB value. |
|
| Bits 23:16 | RED[7:0]: red value |
|
These bits configure the red value. |
|
| Bits 15:8 | GREEN[7:0]: green value |
|
These bits configure the green value. |
|
| Bits 7:0 | BLUE[7:0]: blue value |
|
These bits configure the blue value. |
Note: The CLUT write register should only be configured during blanking period or if the layer is
disabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.
The CLUT is only meaningful for L8, AL44 and AL88 pixel format.
The following table summarizes the LTDC registers. Refer to the register boundary addresses table for the LTDC register base address.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0008 |
LTDC_SSCR |
Res. | Res. | Res. | Res. | HSW[11:0] |
Res. | Res. | Res. | Res. | Res. | VSH[10:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x000C |
LTDC_BPCR |
Res. | Res. | Res. | Res. | AHBP[11:0] |
Res. | Res. | Res. | Res. | Res. | AVBP[10:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0010 |
LTDC_AWCR |
Res. | Res. | Res. | Res. | AAW[11:0] |
Res. | Res. | Res. | Res. | Res. | AAH[10:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0014 |
LTDC_TWCR |
Res. | Res. | Res. | Res. | TOTALW[11:0] |
Res. | Res. | Res. | Res. | Res. | TOTALH[10:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0018 |
LTDC_GCR |
HSPOL | VSPOL | DEPOL | PCPOL | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DEN | Res. | DRW[2:0] |
Res. | DGW[2:0] |
Res. | DBW[2:0] |
Res. | Res. | Res. | LTDCEN | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
||||||||||||||||||
| 0x0024 |
LTDC_SRCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBR | IMR |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x002C |
LTDC_BCCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BCRED[7:0] | BCGREEN[7:0] | BCBLUE[7:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0034 |
LTDC_IER |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIE | TERRIE | FUIE | LIE |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x0038 |
LTDC_ISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIF | TERRIF | FUIF | LIF |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x003C |
LTDC_ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRRIF | CTERRIF | CFUIF | CLIF |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x0040 |
LTDC_LIPCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LIPOS10:0] |
||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x0044 |
LTDC_CPSR | CXPOS[15:0] | CYPOS[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x0048 |
LTDC_CDSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSYNCS | VSYNCS | HDES | VDES |
| Reset value | 1 | 1 | 1 | 1 |
|||||||||||||||||||||||||||||
| 0x0084 |
LTDC_L1CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLUTEN | Res. | Res. | COLKEN | LEN |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x0088 |
LTDC_L1WHPCR |
Res. | Res. | Res. | Res. | WHSPPOS[11:0] |
Res. | Res. | Res. | Res. | WHSTPOS[11:0] |
||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x008C |
LTDC_L1WVPCR |
Res. | Res. | Res. | Res. | Res. | WVSPPOS[10:0] |
Res. | Res. | Res. | Res. | Res. | WVSTPOS[10:0] |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x0090 |
LTDC_L1CKCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKRED[7:0] | CKGREEN[7:0] | CKBLUE[7:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0094 |
LTDC_L1PFCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PF[2:0] |
||
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x0098 |
LTDC_L1CACR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CONSTA[7:0] |
|||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||||||
| 0x009C | LTDC_L1DCCR | DCALPHA[7:0] | DCRED[7:0] | DCGREEN[7:0] | DCBLUE[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00A0 |
LTDC_L1BFCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BF1[2:0] |
Res. | Res. | Res. | Res. | Res. | BF2[2:0] |
||||
| Reset value | 1 | 1 | 0 | 1 | 1 | 1 |
|||||||||||||||||||||||||||
| 0x00AC | LTDC_L1CFBAR | CFBADD[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x00B0 |
LTDC_L1CFBLR |
Res. | Res. | Res. | CFBP[12:0] |
Res. | Res. | Res. | CFBLL[12:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x00B4 |
LTDC_L1CFBLNR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CFBLNBR[10:0] |
||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x00C4 | LTDC_L1CLUTWR | CLUTADD[7:0] | RED[7:0] | GREEN[7:0] | BLUE[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0104 |
LTDC_L2CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLUTEN | Res. | Res. | COLKEN | LEN |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x0108 |
LTDC_L2WHPCR |
Res. | Res. | Res. | Res. | WHSPPOS[11:0] |
Res. | Res. | Res. | Res. | WHSTPOS[11:0] |
||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x010C |
LTDC_L2WVPCR |
Res. | Res. | Res. | Res. | Res. | WVSPPOS[10:0] |
Res. | Res. | Res. | Res. | Res. | WVSTPOS[10:0] |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x0110 |
LTDC_L2CKCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKRED[7:0] | CKGREEN[7:0] | CKBLUE[7:0] |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0114 |
LTDC_L2PFCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PF[2:0] |
||
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x0118 |
LTDC_L2CACR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CONSTA[7:0] |
|||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||||||
| 0x011C | LTDC_L2DCCR | DCALPHA[7:0] | DCRED[7:0] | DCGREEN[7:0] | DCBLUE[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0120 |
LTDC_L2BFCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BF1[2:0] |
Res. | Res. | Res. | Res. | Res. | BF2[2:0] |
||||
| Reset value | 1 | 1 | 0 | 1 | 1 | 1 |
|||||||||||||||||||||||||||
| 0x012C | LTDC_L2CFBAR | CFBADD[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0130 |
LTDC_L2CFBLR |
Res. | Res. | Res. | CFBP[12:0] |
Res. | Res. | Res. | CFBLL[12:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x0134 |
LTDC_L2CFBLNR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CFBLNBR[10:0] |
||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x0144 | LTDC_L2CLUTWR | CLUTADD[7:0] | RED[7:0] | GREEN[7:0] | BLUE[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2.2 for the register boundary addresses.
Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.
The display serial interface (DSI) is part of a group of communication protocols defined by the MIPI® Alliance. The MIPI® DSI Host controller is a digital core that implements all protocol functions defined in the MIPI® DSI Specification.
It provides an interface between the system and the MIPI® D-PHY, allowing the user to communicate with a DSI-compliant display.
MIPI® Alliance Specification for Display Serial interface (DSI)
v1.1 - 22 November 2011
MIPI® Alliance Specification for Display Bus interface (DBI-2)
v2.00 - 16 November 2005
MIPI® Alliance Specification for Display Command set (DCS)
v1.1 - 22 November 2011
MIPI® Alliance Specification for Display Pixel interface (DPI-2)
v2.00 - 15 September 2005
MIPI® Alliance Specification for Stereoscopic Display Formats (SDF)
v1.0 - 22 November 2011
MIPI® Alliance Specification for D-PHY
v1.1 - 7 November 2011
Video mode interfaces features:
•16-bit RGB, configurations 1, 2, and 3
•18-bit RGB, configurations 1 and 2
•24-bit RGB
•Number of lanes: 2
•Maximum speed per lane: 500 Mbps
•See examples in Section 20.4.2: Supported resolutions and frame rates
Adapted interface features:
•16-bit RGB, configurations 1, 2, and 3
•18-bit RGB, configurations 1 and 2
•24-bit RGB
The MIPI® DSI Host includes dedicated video interfaces internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. More in detail:
The block diagram of the DSI Host is shown in Figure 124.
| (omitted) |
The DSI specification does not define supported standard resolutions or frame rates. Display resolution, blanking periods, synchronization events duration, frame rates, and pixel color depth play a fundamental role in the required bandwidth. In addition, other link related attributes can influence the ability of the link to support a DSI-specific device. These attributes can be: display input buffering capabilities, video transmission mode (burst or non-burst), bus Turn-Around (BTA) time, concurrent command mode traffic in a video mode transmission, or display device specifics. All these variables make it difficult to define a
standard procedure to estimate the minimum lane rate and the minimum number of lanes that support a specific display device.
The basic assumptions for estimates are:
Figure 125 shows the architecture of the DSI Host
| (omitted) |
The different parts have the following functions:
a high-speed transmission. It also performs data splitting between available D-PHY lanes for high-speed transmission.
The LTDC interface captures the data and control signals and conveys them to the FIFO interfaces that transmit them to the DSI link.
Two different streams of data are present at the interface, namely video control signals and pixel data. Depending on the interface color coding, the pixel data is disposed differently throughout the LTDC bus.
Interface pixel color coding is summarized in Table 132.
| Location |
16 bits | 18 bits |
24 bits |
|||
|---|---|---|---|---|---|---|
| Config 1 | Config 2 | Config 3 | Config 1 | Config 2 |
||
| D23 | - | - | - | - | - | R[7] |
| D22 | - | - | - | - | - | R[6] |
| D21 | - | - | R[4] | - | R[5] | R[5] |
| D20 | - | R[4] | R[3] | - | R[4] | R[4] |
| D19 | - | R[3] | R[2] | - | R[3] | R[3] |
| D18 | - | R[2] | R[1] | - | R[2] | R[2] |
| D17 | - | R[1] | R[0] | R[5] | R[1] | R[1] |
| D16 | - | R[0] | - | R[4] | R[0] | R[0] |
| D15 | R[4] | - | - | R[3] | - | G[7] |
| D14 | R[3] | - | - | R[2] | - | G[6] |
| D13 | R[2] | G[5] | G[5] | R[1] | G[5] | G[5] |
| D12 | R[1] | G[4] | G[4] | R[0] | G[4] | G[4] |
| D11 | R[0] | G[3] | G[3] | G[5] | G[3] | G[3] |
| D10 | G[5] | G[2] | G[2] | G[4] | G[2] | G[2] |
| D9 | G[4] | G[1] | G[1] | G[3] | G[1] | G[1] |
| D8 | G[3] | G[0] | G[0] | G[2] | G[0] | G[0] |
| D7 | G[2] | - | - | G[1] | - | B[7] |
| D6 | G[1] | - | - | G[0] | - | B[6] |
| D5 | G[0] | - | B[4] | B[5] | B[5] | B[5] |
| D4 | B[4] | B[4] | B[3] | B[4] | B[4] | B[4] |
| D3 | B[3] | B[3] | B[2] | B[3] | B[3] | B[3] |
| D2 | B[2] | B[2] | B[1] | B[2] | B[2] | B[2] |
| D1 | B[1] | B[1] | B[0] | B[1] | B[1] | B[1] |
| D0 | B[0] | B[0] | - | B[0] | B[0] | B[0] |
The LTDC interface can be configured to increase flexibility and promote correct use of this interface for several systems. The following configuration options are available:
For SHTDN and COLM sampling and transmission, the video streaming from the LTDC must be active. This means that if the LTDC is not actively generating the video signals like VSYNC and HSYNC, these signals are not transmitted through the DSI link. Because of such constraints and for commands to be correctly transmitted, the first VSYNC active pulse should occur for the command sampling and transmission. When shutting down the display, it is necessary for the LTDC to be kept active for one frame after the command being issued. This ensures that the commands are correctly transmitted before actually disabling the video generation at the LTDC interface.
The SHTDN and COLM values can be programmed in the DSI wrapper control register (DSI_WCR).
For all of the data types, one entire pixel is received per each clock cycle. The number of pixels of payload is restricted to a multiple of a value, as shown in Table 133.
| Value | Data types |
|---|---|
| 1 |
16-bit 18-bit loosely packed 24-bit |
| 2 | Loosely packed pixel stream |
| 4 | 18-bit non-loosely packed |
There are different video transmission modes, namely:
Burst mode
In this mode, the entire active pixel line is buffered into a FIFO and transmitted in a single packet with no interruptions. This transmission mode requires that the DPI Pixel FIFO has the capacity to store a full line of active pixel data inside it. This mode is optimally used when the difference between the pixel required bandwidth and DSI link bandwidth is significant, it enables the DSI Host to quickly dispatch the entire active video line in a single burst of data and then return to low-power mode.
Non-burst mode
In this mode, the processor uses the partitioning properties of the DSI Host to divide the video line transmission into several DSI packets. This is done to match the pixel required bandwidth with the DSI link bandwidth. With this mode, the controller configuration does not require a full line of pixel data to be stored inside the LTDC interface pixel FIFO. It requires only the content of one video packet.
Guidelines for selecting the burst or non-burst mode
Selecting the burst and non-burst mode is mainly dependent on the system configuration and the device requirements. Choose the video transmission mode that suits the application scenario. The burst mode is more beneficial because it increases the probability of the link spending more time in the low-power mode, decreasing power consumption. However, the following conditions should be met for availing the maximum benefits from the burst mode of operation:
If the system cannot meet these requirements, it is likely that the pixel data will be lost causing the malfunctioning of the display device while using the burst mode. These errors are related to the capabilities of the system to store the temporary pixel data.
If all the conditions for using the burst mode cannot be met, use the non-burst mode to avoid the errors caused by the burst mode. The non-burst mode provides a better matching of rates for pixel transmission, enabling:
The DSI non-burst mode should be configured in such way that the DSI output pixel ratio matches with the LTDC interface input pixel ratio, reducing the memory requirements on both host and/or device side. This is achieved by dividing a pixel line into several chunks of pixels and optionally interleaving them with null packets.
The following equations show how the DSI Host core transmission parameters should be programmed in non-burst mode to match the DSI link pixel output ratio (left hand side of the "=" sign) and LTDC interface pixel input (right hand side of the "=" sign).
When the null packets are enabled:
lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 12 + NPSIZE) / number_of_lanes
= pixels_per_line * LTDC_Clock_period
When the null packets are disabled:
lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 6) / number_of_lanes
= pixels_per_line * LTDC_Clock_period
It is possible to update the LTDC interface configuration on the fly without impacting the current frame. It is done with the help of shadow registers. This feature is controlled by the DSI Host video shadow control register (DSI_VSCR).
The new configuration is only used when the system requests for it. To update the video configuration during the transmission of a video frame, the configuration of that frame needs to be stored in the auxiliary registers. This way, the new frame configurations can be set through the APB interface without corrupting the current frame.
By default, this feature is disabled. To enable this feature, set the enable (EN) bit of the DSI Host video shadow control register (DSI_VSCR) to 1.
When this feature is enabled, the system supplies the configuration stored in the auxiliary registers.
Figure 126 shows the necessary steps to update the LTDC interface configuration.
| (omitted) |
Immediate update
When the shadow register feature is active, the auxiliary registers requires the LTDC configuration before the video engine starts. This means that, after a reset, update register (UR) bit is immediately granted.
In situations when it is required to immediately update the active registers without the reset (as illustrated in Figure 127), ensure that the enable (EN) and update register (UR) bits of the DSI Host video shadow control register (DSI_VSCR) are set to 0.
| (omitted) |
Updating the configuration during the transmission of a frame using APB
To update the LTDC interface configuration, follow the steps shown in Figure 128:
| (omitted) |
Requesting a configuration update
It is possible to request for the LTDC interface configuration update at any part of the frame. DSI Host waits until the end of the frame to change the configuration. However, avoid sending the update request during the first line of the frame because the data must propagate between clock domains.
The adapted command mode, enables the system to input a stream of pixel from the LTDC that is conveyed by DSI Host using the command mode transmission (using the DCS packets). The adapted command mode also supports pixel input control rate signaling and tearing effect report mechanism.
The adapted command mode allows to send large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands. It helps in delivering a wider data bandwidth for the memory write operations sent in command mode to MIPI® displays and to refresh large areas of pixels in high resolution displays. If additional commands such as display configuration commands, read back commands, and tearing effect initialization are to be transferred, then the APB slave generic interface should be used to complement the adapted command mode functionality.
Adapted command mode of operation supports 16 bpp, 18 bpp, and 24 bpp RGB.
To transmit the image data in adapted command mode:
To transmit the image data, follow these steps:
Figure 129 shows the adapted command mode usage flow.
| (omitted) |
When the command mode (CMDM) bit of the DSI Host mode configuration register (DSI_CFGR) is set to 1, the LTDC interface assume the behavior corresponding to the adapted command mode.
In this mode, the host processor can use the LTDC interface to transmit a continuous stream of pixels to be written in the local frame buffer of the peripheral. It uses a pixel input bus to receive the pixels and controls the flow automatically to limit the stream of continuous pixels. When the first pixel is received, the current value of the command size (CMDSIZE) field of the DSI Host LTDC command configuration register (DSI_LCCR), is shadowed to the internal interface function. The interface increments a counter on every valid pixel that is input through the interface. When this pixel counter reaches command size (CMDSIZE), a command is written into the command FIFO and the packet is ready to be transmitted through the DSI link.
If the last pixel arrives before the counter reaches the value of shadowed command size (CMDSIZE), a WMS command is issued to the command FIFO with word count (WC) set to the amount of bytes that correspond to the value of the counter. If more than CMDSIZE number of pixels are received (shadowed value), a WMS command is sent to the command FIFO with WC set to the number of bytes that correspond to command size (CMDSIZE) and the counter is restarted.
After the first WMS command has been written to the FIFO, the circuit behaves in a similar way, but issues WMC commands instead of WMS commands. The process is repeated until the last pixel of the image is received. The core automatically starts sending a new packet
when the last pixel of the image is received falls or command size (CMDSIZE) limit is reached.
Synchronization with the LTDC
The DSI wrapper performs the synchronization of the transfer process by :
The transfer to refresh the display frame buffer can be trigged
The selection between manual and automatic mode is done through the automatic refresh (AR) bit of the DSI Wapper configuration register (DSI_WCFGR). In automatic refresh mode, the LTDC enable (LTDCEN) bit of the DSI Wapper control register (DSI_WCR) is set automatically by a tearing effect (TEIF) event.
Once the transfer of one frame is done whatever in manual or automatic refresh mode, the DSI wrapper is halting the TFT display controller (LTDC) resetting the LTDC enable (LTDCEN) bit of the DSI Wapper control register (DSI_WCR) and set the end of refresh interrupt flag (ERIF) flag of the DSI wrapper status register (DSI_WSR). If the end of refresh interrupt enable (ERIE) bit of the DSI Wapper configuration register (DSI_WCFGR) is set, an interrupt is generated.
The end of refresh interrupt flag (ERIF) flag of the DSI wrapper status register (DSI_WSR) can be reset setting the clear end of refresh interrupt flag (CERIF) bit of the DSI wrapper clear interrupt flag register (DSI_WCIFR).
The halting of the TFT display controller (LTDC) by the DSI wrapper is done synchronously on a rising edge or a falling edge of VSync according to the VSync polarity (VSPOL) bit of the DSI Wapper configuration register (DSI_WCFGR).
Support of tearing effect
The DSI specification supports tearing effect function in command mode displays. It enables the Host Processor to receive timing accurate information about where the display peripheral is in the process of reading the content of its frame buffer.
The tearing effect can be managed through
Tearing effect through a GPIO
When the tearing effect source (TESRC) bit of the DSI wrapper configuration register (DSI_WCFGR) is set, the tearing effect is signaled through a GPIO.
The polarity of the input signal can be configured by the tearing effect polarity (TEPOL) bit of the DSI wrapper configuration register (DSI_WCFGR).
When the programmed edge is detected, the tearing effect interrupt flag (TEIF) bit of the DSI wrapper interrupt and status register (DSI_WISR) is set.
If the tearing effect interrupt enable (TEIE) bit of the DSI wrapper interrupt enable register (DSI_WIER) is set, an interrupt is generated.
Tearing effect through DSI link
When the TESRC bit of the DSI wrapper configuration register (DSI_WCFGR) is reset, the tearing effect is managed through the DSI link:
The DSI Host performs a double bus Turn-Around (BTA) after sending the set_tear_on
command granting the ownership of the link to the DSI display. The display holds the ownership of the bus until the tear event occurs, which is indicated to the DSI Host by a D-PHY trigger event. The DSI Host then decodes the trigger and reports the event setting the tearing effect interrupt flag (TEIF) bit of the DSI wrapper interrupt and status register (DSI_WISR).
If the tearing effect interrupt enable (TEIE )bit of the DSI wrapper interrupt enable register (DSI_WIER) is set, an interrupt is generated.
To use this function, it is necessary to issue a set_tear_on command after the update of the display using the WMS and WMC DCS commands. This procedure halts the DSI link until the display is ready to receive a new frame update.
The DSI Host does not automatically generate the tearing effect request (double BTA) after a WMS/WMC sequence for flexibility purposes. This way several regions of the display can be updated improving DSI bandwidth usage. Tearing effect request must always be triggered by a set_tear_on command in the DSI Host implementation.
Configure the following registers to activate the tearing effect:
The APB slave interface allows the transmission of generic information in command mode, and follows a proprietary register interface. Commands sent through this interface are not constrained to comply with the DCS specification, and can include generic commands described in the DSI specification as manufacturer-specific.
The DSI Host supports the transmission of write and read command mode packets as described in the DSI specification. These packets are built using the APB register access. The DSI Host generic payload data register (DSI_GPDR) has two distinct functions based on the operation. Writing to this register sends the data as payload when sending a command mode packet. Reading this register returns the payload of a read back operation. The DSI Host generic header configuration register (DSI_GHCR) contains the command mode packet header type and header data. Writing to this register triggers the transmission of the packet implying that for a long command mode packet, the packet's payload needs to be written in advance in the DSI Host generic payload data register (DSI_GPDR).
The valid packets that can be transmitted through the generic interface are the following ones:
A set of bits in the DSI Host generic packet status register (DSI_GPSR) reports the status of the FIFO associated with APB interface support.
Generic interface packets are always transported using one of the DSI transmission modes, i.e. video mode or command mode. If neither of these modes is selected, the packets are not transmitted through the link and the related FIFO eventually becomes overflown.
The transfer of packets through the APB bus is based on the following conditions:
To drive the APB interface to achieve high bandwidth command mode traffic transported by the DSI link, the DSI Host should operate in the command mode only and the APB interface should be the only data source that is currently in use. Thus, the APB interface has the entire bandwidth of the DSI link and does not share it with any another input interface source.
The memory write commands require maximum throughput from the APB interface, because they contain the most amount of data conveyed by the DSI link. While writing the packet information, first write the payload of a given packet into the payload FIFO using the DSI Host generic payload data register (DSI_GPDR). When the payload data is for the command parameters, place the first byte to be transmitted in the least significant byte position of the APB data bus.
After writing the payload, write the packet header into the command FIFO. For more information about the packet header organization on the 32-bit APB data bus, so that it is correctly stored inside the command FIFO.
When the payload data is for a memory write command, it contains pixel information and it should follow the pixel to byte conversion organization referred in the Annexe A of the DCS specification.
Figures 130 to 134 show how the pixel data should be organized in the APB data write bus.
The memory write commands are conveyed in DCS long packets, encapsulated in a DSI packet. The DSI specifies that the DCS command should be present in the first payload byte of the packet. This is also included in the diagrams. In figures 130 to 134, the write memory
command can be replaced by the DCS command write memory Start and write memory
Continue.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
The DSI Host includes counters to manage timeout during the various communication phases. The duration of each timeout can be configured by the six DSI Host timeout counter configuration register (DSI_TCCR0..5).
There are two types of counters:
The DSI Host implements a set of counters and conditions to notify the errors. It features a set of registers to control the timers used to determine if a timeout has occurred, and also contains a set of interruption status registers that are cleared upon a read operation (detailed in Table 134). Optionally, these registers also trigger an interrupt signal that can be used by the system to be activated when an error occurs within the DSI connection.
| Timeout counter | Value register | Value field | Flag register | Flag field |
|---|---|---|---|---|
| High-speed transmission | DSI_TCCR0 | TOHSTX | DSI_ISR1 | TOHSTX |
| Low-power reception | DSI_TCCR0 | TOLPRX | DSI_ISR1 | TOLPRX |
Time units for these 16-bit counters are configured in cycles defined in the timeout clock division (TOCKDIV) field in the DSI Host clock control register (DSI_CCR).
The value written to the timeout clock division (TOCKDIV) field in the DSI Host clock control register (DSI_CCR) defines the time unit for the timeout limits using the lane byte clock as input.
This mechanism increases the range to define these limits.
High-speed transmission contention detection
The timeout duration is configured in the high-speed transmission timeout count (HSTX_TOCNT) field of the DSI Host timeout counter configuration register 1 (DSI_TCCR0). A 16-bit counter measures the time during which the high-speed mode is active.
If that counter reaches the value defined by the high-speed transmission timeout count (HSTX_TOCNT) field of the DSI Host timeout counter configuration register 1 (DSI_TCCR0), the timeout high-speed transmission (TOHSTX) bit in the DSI Host interrupt and status register 1 (DSI_ISR1) is asserted and an internal soft reset is generated to the DSI Host.
If the timeout high-speed transmission interrupt enable (TOHSTXIE) bit of the DSI Host interrupt enable register 1 (DSI_IER1) is set, an interrupt is generated.
Low-power reception contention detection
The timeout is configured in the low-power reception timeout counter (LPRX_TOCNT) field of the DSI Host timeout counter configuration register 1 (DSI_TCCR1). A 16-bit counter measures the time during which the low-power reception is active.
If that counter reaches the value defined by the low-power reception timeout counter (LPRX_TOCNT) field of the DSI Host timeout counter configuration register 1 (DSI_TCCR0), the timeout low-power reception (TOLPRX) bit in the DSI Host interrupt and status register 1 (DSI_ISR1) is asserted and an internal soft reset is generated to the DSI Host.
If the timeout low-power reception interrupt enable (TOLPRXIE) bit of the DSI Host interrupt enable register 1 (DSI_IER1) is set, an interrupt is generated. Once the software gets notified by the interrupt, it must reset the D-PHY by de-asserting and asserting the Digital enable (DEN) bit of the DSI Host PHY control register (DSI_PCTLR).
A peripheral may not immediately respond correctly to some received packets. For example, a peripheral receives a read request, but due to its architecture cannot access the RAM for a while. It may be because the panel is being refreshed and takes some time to respond. In this case, set a timeout to ensure that the host waits long enough so that the device is able to process the previous data before receiving the new data or responding correctly to new requests.
Table 135 lists the events belonging to various categories having an associated timeout for peripheral response.
| Category | Event |
|---|---|
| Items implying a BTA PRESP_TO | Bus-turn-around |
| READ requests indicating a PRESP_TO (replicated for HS and LP) |
(0x04) Generic read, no parameters short (0x14) Generic read, 1 parameter short (0x24) Generic read, 2 parameters short (0x06) DCS read, no parameters short |
| WRITE requests indicating a PRESP_TO (replicated for HS and LP) |
(0x03) Generic short write, no parameters short (0x13) Generic short write, 1 parameter short (0x23) Generic short write, 2 parameters short (0x29) Generic long write long (0x05) DCS short write, no parameters short (0x15) DCS short write, 1 parameter short (0x39) DCS long write/write_LUT, command packet long (0x37) Set maximum return packet size |
The DSI Host ensures that, on sending an event that triggers a timeout, the D-PHY switches to the Stop state and a counter starts running until it reaches the value of that timeout. The link remains in the LP-11 state and unused until the timeout ends, even if there are other events ready to be transmitted.
Figures 135 to 137 illustrate the flow of counting in the PRESP_TO counter for the three categories listed in Table 135.
| (omitted) |
| (omitted) |
| (omitted) |
Table 136 describes the fields used for the configuration of the PRESP_TO counter.
| Description | Register | Field |
|
|---|---|---|---|
| Period for which the DSI Host keeps the link still |
After sending a High-speed read operation |
DSI_TCCR1 | HSRD_TOCNT |
| After sending a Low-power read operation |
DSI_TCCR2 | LPRD_TOCNT |
|
| After completing a Bus-turn-around (BTA) |
DSI_TCCR5 | BTA_TOCNT |
|
| Period for which the DSI Host keeps the link inactive |
After sending a High-speed write operation |
DSI_TCCR3 | HSWR_TOCNT |
| After sending a Low-power write operation |
DSI_TCCR4 | LPWR_TOCNT |
|
The values in these registers are measured in number of cycles of the lane byte clock. These registers are only used in command mode because in video mode, there is a rigid timing schedule to be met to keep the display properly refreshed and it must not be broken by these or any other timeouts. Setting a given timeout to 0 disables going into LP-11 state and timeout for events of that category.
The read and the write requests in high-speed mode are distinct from the read and the write requests in low-power mode. For example, if HSRD_TOCNT is set to zero and LPRD_TOCNT is set to a non-zero value, a generic read with no parameters does not activate the PRESP_TO counter in high-speed, but it activates the PRESP_TO in low-power.
The DSI Host timeout counter configuration register 4 (DSI_TCCR3) includes a special Presp mode (PM) bit to change the normal behavior of PRESP_TO in Adaptive command
mode for high-speed write operation timeout. When set to 1, this bit allows the PRESP_TO from HSWR_TOCNT to be used only once, when both of the following conditions are met:
In this scenario, non-adapted command mode requests are not sent to the D-PHY, even if there is traffic from the generic interface ready to be sent, returning them to the Stop state. When it happens, the PRESP_TO counter is activated and only when it is completed, the DSI Host sends any other traffic that is ready, as illustrated in Figure 138.
|
dpivsync_edpiwms dpidataen dpidata[29:0] edpi_fifo_empty gen_wr_en gen_data[31:0] |
||||||
| linkstate[1:0] LP |
HS | LP | HS | LP | ||
| MSv35880V1 |
||||||
|
_ link_data[31:0] PRESP_TO_active |
||||||
The DSI Host supports the transmission of commands, both in high-speed and low-power, while in video mode. The DSI Host uses Blanking or low-power (BLLP) periods to transmit commands inserted through the APB generic interface. Those periods correspond to the gray areas of Figure 139.
| (omitted) |
Commands are transmitted in the blanking periods after the following packets/states:
Besides the areas corresponding to BLLP, large commands can also be sent during the last line of a frame. In that case, the line time for the video mode is violated and the edpihalt signal is set to request the DPI video timing signals to remain inactive. Only if a command does not fit into any BLLP area, it is postponed to the last line, causing the violation of the line time for the video mode, as illustrated in Figure 140.
| (omitted) |
Only one command is transmitted per line, even in the case of the last line of a frame but one command is possible for each line.
There can be only one command sent in low-power per line. However, one low-power command is possible for each line. In high-speed, the DSI Host can send more than one command, as many as it determines to fit in the available time.
The DSI Host avoids sending commands in the last line because it is possible that the last line is shorter than the other ones. For instance, the line time (tL) could be half a cycle longer than the tL on the LTDC interface, that is, each line in the frame taking half a cycle from time for the last line. This results in the last line being (½ cycle) x (number of lines -1) shorter than tL.
The COLM and SHTDN bits of the DSI wrapper control register (DSI_WCR) are also able to trigger the sending of command packets. The commands are:
These commands are not sent in the VACT region. If the low-power command enable (LPCE) bit of the DSI Host video mode configuration register (DSI_VMCR) is set, these commands are sent in low-power mode.
In low-power mode, the largest packet size (LPSIZE) field of the DSI Host low-power mode configuration register (DSI_LPMCR) is used to determine if these commands can be transmitted. It is assumed that largest packet size (LPSIZE) is greater than or equal to four bytes (number of bytes in a short packet), because the DSI Host does not transmit these commands on the last line.
If the frame bus-turn-around acknowledge enable (FBTAAE) bit is set in the DSI Host low-power mode configuration register (DSI_LPMCR), a BTA is generated by DSI Host after the last line of a frame. This may coincide with a write command or a read command. In either case, the LTDC interface is halted until an acknowledge is received (control of the DSI bus is returned to the host).
DSI Host can be configured to send the low-power commands during the high-speed video mode transmission.
To enable this feature, set the Low Power command enable (LPCE) bit of the DSI Host video mode configuration register (DSI_VMCR) to 1. In this case, it is necessary to calculate the time available, in bytes, to transmit a command in low-power mode to horizontal front-porch (HFP), vertical sync active (VSA), vertical back-porch (VBP), and vertical front-porch (VFP) regions.
to 13 of the video mode configuration register (DSI_VMCR) register indicates if DSI
video packets are in queue, DSI Host ignores the low-power configuration and transmits low-power commands, even if it is not allowed to enter low-power mode in a specific region. After the low-power commands transmission, DSI Host remains in low-power until a sync event occurs.
For example, consider that the VFP is selected as high-speed region (LPVFPE = 1'b0) with LPCE set as a command to transmit in low-power in the VPF region. This command is transmitted in low-power, and the line stays in low-power mode until a new HSS arrives.
Calculating the time to transmit commands in LP mode in the VSA, VBP, and
VFP Regions
The largest packet size (LPSIZE) field of the DSI Host low-power mode configuration register (DSI_LPMCR) indicates the time available (in bytes) to transmit a command in low-power mode (based on the escape clock) on a line during the VSA, VBP, and the VFP regions.
Calculation of largest packet size (LPSIZE) depends on the used video mode.
Figure 141 illustrates the timing intervals for the video mode in non-burst with sync pulses, while Figure 142 refers to video mode in burst and non-burst with sync events.
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This time is calculated as follows:
LPSIZE = (tL - (tH1 + tHS->LP + tLPHS + tLPDT + 2 tESCCLK)) / (2 × 8 × tESCCLK), where
In the above equation, division by eight is done to convert the available time to bytes. Division by two is done because one bit is transmitted every two escape clock cycles. The largest packet size (LPSIZE) field can be compared directly with the size of the command to be transmitted to determine if there is enough time to transmit the command. The maximum size of a command that can be transmitted in low-power mode is limited to 255 bytes by this field. You must program this register to a value greater than or equal to 4 bytes for the transmission of the DCTRL commands, such as shutdown and color in low-power mode.
Consider an example of a frame with 12.4 μs per line and assume an escape clock frequency of 20 MHz and a lane bit rate of 800 Mbits. In this case, it is possible to send 124 bits in escape mode (that is, 124 bit = 12.4 μs * 20 MHz / 2). Still, you need to take into consideration the D-PHY protocol and PHY timings.
The following assumptions are made:
In this example, a 13-byte command can be transmitted as follows:
LPSIZE = (12.4 μs - (420 ns + 180 ns +200 ns + (22 × 50 ns + 2 × 50 ns))) / (2 × 8 × 50 ns) = 13 bytes.
Calculating the time to transmit commands in low-power mode in HFP region
The VACT largest packet size (VLPSIZE) field of the DSI low-power mode configuration register (DSI_LPMCR) indicates the time available (in bytes) to transmit a command in low-power mode (based on the escape clock) in the vertical active (VACT) region.
To calculate the value of VACT largest packet size (VLPSIZE), consider the video mode being used. Figure 143 shows the timing intervals for video mode in non-burst with sync
pulses, Figure 144 those for video mode in non-burst with sync events, and Figure 145
refers to the burst video mode.
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This time is calculated as follows:
VLPSIZE = (tL - (tHSA + tHBP + tHACT + tHS->LP + tLP->HS + tLPDT + 2 tESCCLK)) /
(2 × 8 × tESCCLK)
where
The VLPSIZE field can be compared directly with the size of the command to be transmitted to determine if there is time to transmit the command.
Consider an example of a frame with 16.4 μs per line and assume an escape clock frequency of 20 MHz and a lane bit rate of 800 Mbits/s. In this case, it is possible to send 420 bits in escape mode (that is, 164 bits = 16.4 μs * 20 MHz / 2). Still, since it is the vertical active region of the frame, take into consideration the HSA, HBP, and HACT timings apart from the D-PHY protocol and PHY timings. The following assumptions are made:
In this example, consider that you send video in non-burst mode. The VLPSIZE is calculated as follows:
VLPSIZE = (16.4 µs -(420 ns + 800 ns + 12.8 µs + 180 ns +200 ns +
(22 × 50 ns + 2 × 50 ns)) / (2 × 8 × 50 ns) = 1 byte
Only one byte can be transmitted in this period. A short packet (for example, generic short write) requires a minimum of four bytes. Therefore, in this example, commands are not sent in the VACT region.
If burst mode is enabled, more time is available to transmit the commands in the VACT region, because HACT is time compressed.
VLPSIZE = (16.4 µs - (420 ns + 800 ns + (1280 × 3 / 4 × 10 ns) + 180 ns + 200 ns +
(22 × 50 ns + 2 × 50 ns) / (2 × 8 × 50 ns) = 5 bytes
For burst mode, the VLPSIZE is 5 bytes and then a 4-byte short packet can be sent.
Transmission of commands in different periods
The LPSIZE and VLPSIZE fields allow a simple comparison to determine if a command can be transmitted in any of the BLLP periods.
Figure 146 illustrates the meaning of VLPSIZE and LPSIZE, matching them with the shaded areas and the VACT region.
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If the LPCE bit of the DSI_VMCR register is 0, the commands are sent in high-speed in video mode. In this case, the DSI Host automatically determines the area where each command can be sent and no programming or calculation is required.
The MRD_TIME field of the DSI_DLTCR register configures the maximum amount of time required to perform a read command in lane byte clock cycles, it is calculated as:
MRD_TIME = time to transmit the read command in low-power mode + time to enter and leave low-power mode + time to return the read data packet from the peripheral device.
The time to return the read data packet from the peripheral depends on the number of bytes read and the escape clock frequency of the peripheral, not the escape clock of the host. The MRD_TIME field is used in both high-speed and low-power mode to determine if there is time to complete a read command in a BLLP period.
In high-speed mode (LPCE = 0), MRD_TIME is calculated as follows:
MRD_TIME = (tHS->LP + tLP->HS + tread + 2 x tBTA) / lanebyteclkperiod
In low-power mode (LPCE = 1), MRD_TIME is calculated as follows:
MRD_TIME = (tHS->LP + tLP->HS + tLPDT + tlprd + tread + 2 x tBTA) / lanebyteclkperiod, where:
It is recommended to keep the maximum number of bytes read from the peripheral to a minimum to have sufficient time available to issue the read commands in a line time. Ensure that MRD_TIME x lane byte clock period is less than LPSIZE x 16 x escape clock period of the host, otherwise, the read commands are dispatched on the last line of a frame. If it is necessary to read a large number of parameters (> 16), increase the MRD_TIME while the read command is being executed. When the read has completed, decrease the MRD_TIME to a lower value.
If a read command is issued on the last line of a frame, the LTDC interface is halted and stays halted until the read command is in progress. The video transmission should be stopped during this period.
To reduce the power consumption of the D-PHY, the DSI Host, when not transmitting in the high-speed mode, allows the clock lane to enter into the low-power mode. The controller automatically handles the transition of the clock lane from HS (clock lane active sending clock) to LP state without direct intervention by the software. This feature can be enabled by configuring the DPCC and the ACR bits of the DSI_CLCR register.
In the command mode, the DSI Host can place the clock lane in the low-power mode when it does not have any HS packets to transmit.
In the video mode (LTDC interface), the DSI Host controller uses its internal video and PHY timing configurations to determine if there is time available for the clock line to enter the low-power mode and not compromise the video data transmission of pixel data and sync events.
Along with a correct configuration of the video mode (see Section 20.5: Functional
description: video mode on LTDC interface), the DSI Host needs to know the time required by the clock lane to go from high-speed to low-power mode and viceversa. The values required can be obtained from the D-PHY specification: program the DSI_CLTCR register with the following values:
Based on the programmed values, the DSI Host calculates if there is enough time for the clock lane to enter the low-power mode during inactive regions of the video frame.
The DSI Host decides the best approach to follow regarding power saving out of the three possible scenarios:
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The DSI Host supports choosing the virtual channel (VC) for use for each interface. Using multiple virtual channels, the system can address multiples displays at the same time, when each display has a different virtual channel identifier.
When the LTDC interface is configured for a particular virtual channel, it is possible to use the APB slave generic interface to issue the commands while the video stream is being transmitted. With this, it is possible to send the commands through the ongoing video stream, addressing different virtual channels and thus enable the interface with multiple displays. During the video mode, the video stream transmission has the maximum priority. Therefore, the transmission of sideband packets such as the ones from the generic interface are only transported when there is time available within the video stream transmission. The DSI Host identifies the available time periods and uses them to transport the generic interface packets. Figure 150 illustrates where the DSI Host inserts the packets from the APB generic interface within the video stream transmitted by the LTDC interface.
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It is also possible to address the multiple displays with only the generic interface using different virtual channels. Because the generic interface is not restricted to any particular virtual channel through configuration, it is possible to issue the packets with different virtual channels. This enables the interface to time multiplex the packets to be provided to the displays with different virtual channels.
You can use the following configuration registers to select the virtual channel ID associated with transmissions over the LTDC and APB slave generic interfaces:
The video mode pattern generator allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any stimuli.
The frame requirements must be defined in video registers that are listed in Table 137.
| Register name | Description |
|---|---|
| DSI Host video mode configuration | Video mode configuration |
| DSI Host video packet configuration | Video packet size |
| DSI Host video chunks configuration | Number of chunks |
| DSI Host video null packet configuration | Null packet size |
| DSI Host video HSA configuration | Horizontal sync active time |
| DSI Host video HBP configuration | Horizontal back-porch time |
| DSI Host video line configuration | Line time |
| DSI Host video VSA configuration | Vertical sync active period |
| DSI Host video VBP configuration | Vertical back-porch period |
| DSI Host video VFP configuration | Vertical front-porch period |
| DSI Host video VA configuration | Vertical resolution |
The color bar pattern comprises eight bars for white, yellow, cyan, green, magenta, red, blue, and black colors.
Each color width is calculated by dividing the line pixel size (vertical pattern) or the number of lines (horizontal pattern) by eight. In the vertical color bar mode (Figure 151), each single color bar has a width of the number of pixels in a line divided by eight. In case the number of pixels in a line is not divisible by eight, the last color (black) contains the remaining.
In the horizontal color bar mode (Figure 152), each color line has a color width of the number of lines in a frame divided by eight. In case the number of lines in a frame is not divisible by eight, the last color (black) contains the remaining lines.
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Table 138 shows the RGB components used.
| White | Yellow | Cyan | Green | Magenta | Red | Blue | Black |
|
|---|---|---|---|---|---|---|---|---|
| R | High | High | Low | Low | High | High | Low | Low |
| G | High | High | High | High | Low | Low | Low | Low |
| B | High | Low | High | Low | High | Low | High | Low |
The BER testing pattern simplifies conformance testing. This pattern tests the RX D-PHY capability to receive the data correctly. The following data patterns are required:
In most cases, Y is equal to X. However, depending on line length and the color coding used, Y may be different from X. With RGB888 color coding and horizontal resolution in multiples of eight, the pattern shown in Figure 153 appears on the DSI display.
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Depending on the orientation, BER mode, and color coding, the smallest resolutions accepted by the video mode pattern generator are:
Vertical pattern
The width of each color bar is determined by the division of horizontal resolution (pixels) for eight test pattern colors. If the horizontal resolution is not divisible by eight, the last color (black) is extended to fill the resolution.
In the example in Figure 154, the horizontal resolution is 103.
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Horizontal pattern
The width of each color bar is determined by the division of the number of vertical resolution (lines) for eight test pattern colors. If the vertical resolution is not divisible by eight, the last color (black) will be extended to fill the resolution, as shown in Figure 155.
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The embedded MIPI® D-PHY is control directly by the DSI Host and is configured through the DSI wrapper.
A dedicated PLL and a dedicated 1.2 V regulator are also embedded to supply the clock and the power supply to the DSI Host and D-PHY.
The D-PHY configuration is carried out through the DSI wrapper thanks to the DSI_WPCRx registers.
Timing definition
The MIPI® D-PHY manages all the communication timing with dedicated timers. As all the timings are specified in nanoseconds (ns), it is mandatory to configure the unit interval field to ensure the good duration of all the timings.
Unit interval is configure through the DSI_WPCR0.UIX4 field. This value defines the bit period in high-speed mode in unit of 0.25 ns. If this period is not a multiple of 0.25 ns, the value driven must be rounded down.
As an example, for a 300 Mbit/s link, the unit interval is 3.33 ns, so UIX4 shall be 13.33. In this case a value of 13 (0x0D) has to be written.
Slew-rate and delay tuning on pins
To fine tune DSI communication, slew-rates and delay can be adjusted:
| Function | Lane(s) | Value field in DSI_WPCR1 |
|---|---|---|
| Slew-rate in high-speed transmission |
Clock lane | HSTXSRCCL |
| Data lanes | HSTXSRCDL |
|
| Slew-rate in low-power transmission |
Clock lanes | LPSRCCL |
| Data lanes | LPSRCDL |
|
| High-speed transmission delay |
Clock lane | HSTXDCL |
| Data lanes | HSTXDDL |
The default values for all this parameters is 2’h00. All these values can be programmed only when the DSI is stopped (DSI_WCR.DSIEN = 0 and CR.EN = 0).
Low-power reception filter tuning
The cut-off frequency of the low-pass on low-power receiver can be fine tuned through the LPRXFT field of the DSI_WPCR1 register. The default values is 2’h00 and it can be programmed only when the DSI is stopped (CR.DSIEN = 0 and CR.EN = 0).
Special Sdd control
An additional current path can be activated on both clock lane and data lane to meet the SddTX parameter defined in the MIPI® D-PHY Specification.
This activation is done setting the SDDC bit of the DSI_WPCR1 register.
Custom lane configuration
To ease DSI integration, lane pins can be swapped and/or high-speed signal can be inverted on a lane as described in Table 140.
| Function | Lane | Enable bit in DSI_WPCR0 |
|---|---|---|
| Swap lane pins |
Clock lane | SWCL |
| Data lane 0 | SWDL0 |
|
| Data lane 1 | SWDL1 |
|
| Invert high-speed signal on lane |
Clock lane | HSICL |
| Data lane 0 | HSIDL0 |
|
| Data lane 1 | HSIDL1 |
Custom timing configuration
Some of the MIPI® D-PHY timing can be tuned for specific purpose as described in Table 141.
| MIPI® timing | Enable bit in DSI_WPCR0 |
Configuration register | Field | Default value |
Default duration |
|---|---|---|---|---|---|
| tCLK-POST | TCLKPOSTEN | DSI_WPCR4 | TCLKPOST | 200 | 100 ns + 120*UI |
| tLPX (clock lane) | TLPXCEN |
DSI_WPCR3 |
TLPXC | 100 | 50 ns |
| tHS_EXIT | THSEXITEN | THSEXIT | 200 | 100 ns + 40*UI |
|
| tLPX (data lane) | TLPXDEN | TLPXD | 100 | 50 ns |
|
| tHS-ZERO | THSZEROEN | THSZERO | 175 | 175 ns + 8*UI |
|
| tHS-TRAIL | THSTRAIL |
DSI_WPCR2 |
THSTRAIL | 140 | 70 ns + 8*UI |
| tHS-PREPARE | THSPREPEN | THSPREP | 126 | 63 ns + 12*UI |
|
| tCLK-ZERO | TCLKZEROEN | TCLKZERO | 195 | 390 ns |
|
| tCLK-PREPARE | TCLKPREPEN | TCLKPREP | 120 | 60 ns + 20*UI |
All this values can be programmed only when the DSI is stopped (CR.DSIEN = 0 and CR.EN = 0).
The DSI wrapper features some control bits to force the D-PHY in some particular state and/or behavior.
Forcing lane state
It’s possible to force the data lane and/or the clock lane in TX Stop mode through the bits FTXSMDL and FTXSMCL of the DSI_WPCR0 register.
Setting this bits causes the respective lane module to immediately jump in transmit control mode and to begin transmitting a stop state (LP-11).
This feature can be used to go back in TX mode after a wrong BTA sequence.
Forcing low-power receiver in low-power mode
The FLPRXLPM bit of the DSI_WPCR1 register enables the low-power mode of the low power receiver (LPRX). When set, the LPRX operates in low-power mode all the time. When not set, the LPRX operates in low-power mode during ULPS only.
Disabling turn of data lane
When set, the TDDL bit of the DSI_WPCR0 register forces the data lane to remain in reception mode even if a bus-turn-around request (BTA) is received from the other side.
The embedded D-PHY offers specific features to optimize consumption.
Pull-down on lanes
The D-PHY embeds a pull-down on each lane to prevent floating states when the lanes are unused.
When set, the PDEN bit of the DSI_WPCR0 register enables the pull-down on the lanes.
Disabling contention detection on data lanes
The contention detector on the data lane can be turned off to lower the overall D-PHY consumption.
When set, the CDOFFDL bit of the DSI_WPCR0 register disables the contention detection on data lanes.
This can be used in forward escape mode to reduce the static power consumption.
The dedicated DSI PLL is controlled through the DSI wrapper, as shown in Figure 156
(analog blocks and signals in red, digital signals in black, digital blocks in light blue).
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The PLL output frequency is configured through the DSI_WRPCR register fields. The VCO frequency and the PLL output frequency are calculated as follows:
FVCO = (CLKIN / IDF) * 2 * NDIV,
PHI = FVCO / (2 * ODF)
where:
The PLL is enabled by setting the PLLEN bit in the DSI_WRPCR register.
Once the PLL is locked, the PLLLIF bit is set in the DSI_WISR. If the PLLLIE bit is set in the DSI_WIER, an interrupt is generated.
The PLL status (lock or unlock) can be monitored with the PLLLS flag in the DSI_WISR register.
If the PLL gets unlocked, the PLLUIF bit of the DSI_WISR is set. If the PLLUIE bit of the DSI_WIER register is set, an interrupt is generated.
The DSI PLL setting can be changed only when the PLL is disabled.
The DSI regulator providing the 1.2 V is controlled through the DSI wrapper.
The regulator is enabled setting the REGEN bit of the DSI_WRPCR register.
Once the regulator is ready, the RRIF bit of the DSI_WISR register is set. If the RRIE bit of the DSI_WIER register is set, an interrupt is generated.
The regulator status (ready or not) can be monitored with the RRS flag in the DSI_WISR register.
Note that the D-PHY has no separated Power ON control bit. The power ON/OFF of the
D-PHY is done directly enabling the 1.2 V regulator.
When the 1.2 V regulator is disabled, the 3.3 V part of the D-PHY is automatically powered OFF.
The interrupts can be generated either by the DSI Host or by the DSI wrapper.
All the interrupts are merged in one interrupt lane going to the interrupt controller.
An interrupt can be produced on the following events:
Separate interrupt enable bits are available for flexibility.
| Interrupt event | Event flag in DSI_WISR | Enable control bit in DSI_WIER |
|---|---|---|
| Tearing effect | TEIF | TEIE |
| End of refresh | ERIF | ERIE |
| PLL locked | PLLLIF | PLLLIE |
| PLL unlocked | PLLUIF | PLLUIE |
| Regulator ready | RRIF | RRIE |
The DSI_ISR0 and DSI_ISR1 registers are associated with error condition reporting. These registers can trigger an interrupt to inform the system about the occurrence of errors.
The DSI Host has one interrupt line that is set high when an error occurs in either the DSI_ISR0 or the DSI_ISR1 register.
The triggering of the interrupt can be masked by programming the mask registers DSI_IER0 and DSI_IER1. By default all errors are masked. When any bit of these registers is set to 1, it enables the interrupt for a specific error. The error bit is always set in the respective DSI_ISR register. The DSI_ISR0 and DSI_ISR1 registers are always cleared after a read operation. The interrupt line is cleared if all registers that caused the interrupt are read.
The interrupt force registers (DSI_FIR0 and DSI_FIR1) are used for test purposes, and they allow triggering the interrupt events individually without the need to activate the conditions that trigger the interrupt sources; this is because it is extremely complex to generate the stimuli for that purpose. This feature also facilitates the development and testing of the software associated with the interrupt events. Setting any bit of these registers to 1 triggers the corresponding interrupt.
The light yellow boxes in Figure 157 illustrate the location of some of the errors.
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Table 143 explains the reasons that set off these interrupts and also explains how to recover from these interrupts.
| DSI Host interrupt and status register |
Bit | Name | Cause of the error | Recommended method of handling the error |
|---|---|---|---|---|
| 0 | 20 | PE4 |
The D-PHY reports the LP1 contention error. The D-PHY host detects the contention while trying to drive the line high. |
Recover the D-PHY from contention. Reset the DSI Host and transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 19 | PE3 |
D-PHY reports the LP0 contention error. The D-PHY Host detects the contention while trying to drive the line low. |
Recover the D-PHY from contention. Reset the DSI Host and transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 18 | PE2 |
The D-PHY reports the false control error. The D-PHY detects an incorrect line state sequence in lane 0 lines. |
Device does not behave as expected, communication with the device is not properly established. This is an unrecoverable error. Reset the DSI Host and the D-PHY. If this error is recurrent, analyze the behavior of the device. |
| 0 | 17 | PE1 |
The D-PHY reports the LPDT error. The D-PHY detects that the LDPT did not match a multiple of 8 bits. |
The data reception is not reliable. The D- PHY recovers but the received data from the device might not be reliable. It is recommended to reset the DSI Host and repeat the RX transmission. |
| 0 | 16 | PE0 |
The D-PHY reports the escape entry error. The D-PHY does not recognize the received escape entry code. |
The D-PHY Host does not recognize the escape entry code. The transmission is ignored. The D-PHY Host recovers but the system should repeat the RX reception. |
| 0 | 15 | AE15 |
This error is directly retrieved from acknowledge with error packet. The device detected a protocol violation in the reception. |
Refer to the display documentation. When this error is active, the device should have another read-back command that reports additional information about this error. Read the additional information and take appropriate actions. |
| 0 | 14 | AE14 |
The acknowledge with error packet contains this error. The device chooses to use this bit for error report. |
Refer to the device documentation regarding possible reasons for this error and take appropriate actions. |
| 0 | 13 | AE13 |
The acknowledge with error packet contains this error. The device reports that the transmission length does not match the packet length. |
Possible reason for this is multiple errors present in the packet header (more than 2), so the error detection fails and the device does not discard the packet. In this case, the packet header is corrupt and can cause decoding mismatches. Transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 12 | AE12 |
The acknowledge with error packet contains this error. The device does not recognize the VC ID in at least one of the received packets. |
Possible reason for this is multiple errors present in the packet header (more than 2), so the error detection fails and the device does not discard the packet. In this case, the packet header is corrupt and can cause decoding mismatches. Transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 11 | AE11 |
The acknowledge with error packet contains this error. The device does not recognize the data type of at least one of the received packets. |
Check the device capabilities. It is possible that there are some packets not supported by the device. Repeat the transmission. |
| 0 | 10 | AE10 |
The acknowledge with error packet contains this error. The device detects the CRC errors in at least one of the received packets. |
Some of the long packets, transmitted after the last acknowledge request, might contain the CRC errors in the payload. If the payload content is critical, transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 9 | AE9 |
The acknowledge with error packet contains this error. The device detects multi-bit ECC errors in at least one of the received packets. |
The device does not interpret the packets transmitted after the last acknowledge request. If the packets are critical, transmit the packets again. If this error is recurrent, carefully analyze the connectivity between the Host and the device. |
| 0 | 8 | AE8 |
The acknowledge with error packet contains this error. The device detects and corrects the 1 bit ECC error in at least one of the received packets. |
No action is required. The device acknowledges the packet. If this error is recurrent, analyze the signal integrity or the noise conditions of the link. |
| 0 | 7 | AE7 |
The acknowledge with error packet contains this error. The device detects the line Contention through LP0/LP1 detection. |
This error might corrupt the low-power data reception and transmission. Ignore the packets and transmit them again. The device recovers automatically. If this error is recurrent, check the device capabilities and the connectivity between the Host and device. Refer to.section 7.2.1 of the DSI Specification 1.1. |
| 0 | 6 | AE6 |
The acknowledge with error packet contains this error. The device detects the false control error. |
The device detects one of the following:
The D-PHY communications are corrupted. This error is unrecoverable. |
| 0 | 5 | AE5 |
The acknowledge with error packet contains this error. The display timeout counters for a HS reception and LP transmission expire. |
It is possible that the Host and device timeout counters are not correctly configured. The device HS_TX timeout should be shorter than the Host HS_RX timeout. Host LP_RX timeout should be longer than the device LP_TX timeout. Check and confirm that the Host configuration is consistent with the device specifications. This error is automatically recovered, although there is no guarantee that all the packets in the transmission or reception are complete. For additional information about this error, see section 7.2.2 of the DSI Specification 1.1. |
| 0 | 4 | AE4 |
The acknowledge with error packet contains this error. The device reports that the LPDT is not aligned in an 8-bit boundary |
There is no guarantee that the device properly receives the packets. Transmit the packets again. For additional information about this error, see section 7.1.5 of the DSI Specification. |
| 0 | 3 | AE3 |
The acknowledge with error packet contains this error. The device does not recognize the escape mode entry command. |
The device does not recognize the escape mode entry code. Check the device capability. For additional information about this error, see section 7.1.4 of the DSI Specification. Repeat the transmission to the device. |
| 0 | 2 | AE2 |
The acknowledge with error packet contains this error. The device detects the HS transmission did not end in an 8-bit boundary when the EoT sequence is detected. |
There is no guarantee that the device properly received the packets. Re- transmission should be performed. Transmit the packets again. For additional information about this error, see section 7.1.3 of the DSI Specification 1.1. |
| 0 | 1 | AE1 |
The acknowledge with error packet contains this error. The device detects that the SoT leader sequence is corrupted. |
The device discards the incoming transmission. Re-transmission should be performed by the Host. For additional information about this error, see section 7.1.2 of the DSI Specification 1.1. |
| 0 | 0 | AE0 |
The acknowledge with error packet contains this error. The device reports that the SoT sequence is received with errors but synchronization can still be achieved. |
The device is tolerant to single bit and some multi-bit errors in the SoT sequence but the packet correctness is compromised. If the packet content was important, transmit the packets again. For additional information about this error, see section 7.1.1 of the DSI Specification 1.1. |
| 1 | 12 | GPRXE | An overflow occurs in the generic read FIFO. |
The read FIFO size is not correctly dimensioned for the maximum read-back packet size. Configure the device to return the read data with a suitable size for the Host dimensioned FIFO. Data stored in the FIFO is corrupted. Reset the DSI Host and repeat the read procedure. |
| 1 | 11 | GPRDE | An underflow occurs in the generic read FIFO. |
System does not wait for the read procedure to end and starts retrieving the data from the FIFO. The read data is requested before it is fully received. Data is corrupted. Reset the DSI Host and repeat the read procedure. Check that the read procedure is completed before reading the data through the APB interface. |
| 1 | 10 | GPTXE | An underflow occurs in the generic write payload FIFO. |
The system writes the packet header before the respective packet payload is completely loaded into the payload FIFO. This error is unrecoverable, the transmitted packet is corrupted. Reset the DSI Host and repeat the write procedure. |
| 1 | 9 | GPWRE | An overflow occurs in the generic write payload FIFO. |
The payload FIFO size is not correctly dimensioned to store the total payload of a long packet. Data stored in the FIFO is corrupted. Reset the DSI Host and repeat the write procedure. |
| 1 | 8 | GCWRE | An overflow occurs in the generic command FIFO. |
The command FIFO size is not correctly dimensioned to store the total headers of a burst of packets. Data stored in the FIFO is corrupted. Reset the DSI Host and repeat the write procedure. |
| 1 | 7 | LPWRE | An overflow occurs in the DPI pixel payload FIFO. |
The controller FIFO dimensions are not correctly set up for the operating resolution. Check the video mode configuration registers. They should be consistent with the LTDC video resolution. The pixel data sequence is corrupted. Reset the DSI Host and re-initiate the Video transmission. |
| 1 | 6 | EOTPE |
Host receives a transmission that does not end with an end of transmission packet. |
This error is not critical for the data integrity of the received packets. Check if the device supports the transmission of EoTp packets. |
| 1 | 5 | PSE |
Host receives a transmission that does not end in the expected by boundaries. |
The integrity of the received data cannot be guaranteed. Reset the DSI Host and repeat the read procedure. |
| 1 | 4 | CRCE |
Host reports that a received long packet has a CRC error in its payload. |
The received payload data is corrupted. Reset the DSI Host and repeat the read procedure. If this error is recurrent, check the DSI connectivity link for the noise levels. |
| 1 | 3 | ECCME |
Host reports that a received packet contains multiple ECC errors. |
The received packet is corrupted. The DSI Host ignores all the following packets. The DSI Host should repeat the read procedure. |
| 1 | 2 | ECCSE |
Host reports that a received packet contains a single bit error. |
This error is not critical because the DSI Host can correct the error and properly decode the packet. If this error is recurrent, check the DSI connectivity link for signal integrity and noise levels. |
| 1 | 1 | TOLPRX |
Host reports that the configured timeout counter for the low- power reception has expired. |
Once the configured timeout counter ends, the DSI Host automatically resets the controller side and recovers to normal operation. Packet transmissions happening during this event are lost. If this error is recurrent, check the timer configuration for any issue. This timer should be greater than the maximum low- power transmission generated by the device. |
| 1 | 0 | TOHSTX |
Host reports that the configured timeout counter for the high- speed transmission has expired. |
Once the configured timeout counter ends, the DSI Host automatically resets the controller side and recovers to normal operation. Packet transmissions happening during this event are lost. If this error is recurrent, check the timer configuration for any issue. This timer should be greater than the maximum high- speed transmission bursts generated by the Host. |
| DSI wrapper | 10 | PLLUF | The PLL of the D-PHY has unlocked. |
This error can be critical. The graphical subsystem shall be reconfigured and restarted. |
To operate DSI Host, you must be familiar with the MIPI® DSI specification. Every software programmable register is accessible through the APB interface.
The programming procedure for video mode or adapted command mode must respect the following order:
In video mode, the data streaming starts as soon as the LTDC is enabled.
In adapted command mode, the frame buffer update is launched as soon as the CR.LTDCEN bit is set.
The D-PHY requires a specific configuration prior starting any communications. The configuration parameters are stored either in the DSI Host or the DSI wrapper.
Configuring the D-PHY parameters in the DSI wrapper
The DSI wrapper can be used to fine tunes either timing or physical parameters of the D-PHY. This operation is not required for a standard usage of the D-PHY. All the fields and parameters are described in the register description of the DSI wrapper.
Only one filed is mandatory to properly start the D-PHY: the unit interval multiplied by 4 (UIX4) field of the DSI wrapper PHY configuration register 1 (DSI_WPCR0).
This field defines the bit period in high-speed mode in unit of 0.25 ns, and is used as a timebase for all the timings managed by the D-PHY.
If the link is working at 600 Mbit/s, the unit interval shall be 1.667 ns, that becomes 6.667 ns when multiplied by four. When rounded down, a value of 6 must be written in the UIX4 field of the DSI_WPCR0 register.
Configuring the D-PHY parameters in the DSI Host
The DSI Host stores the configuration of D-PHY timing parameters and number of lanes.
The following fields must be configured prior to any startup:
All the protocol timing shall be configured in the DSI Host.
Clock divider configuration
Two clocks are generated internally
The timeout clock is used as the timing unit in the configuration of HS to LP and LP to HS transition error. It’s division factor is configured by the timeout clock division (TOCKDIV) field of the DSI Host clock control register (DSI_CCR).
The TX escape clock is used in low-power transmission. Its division factor is configured by the TX escape clock division (TXECKDIV) field of the DSI Host clock control register (DSI_CCR) relatively to the lanebyteclock. It’s typical value shall be around 20MHz.
Timeout configuration
The timings for timeout management as described in Section 20.8 are configured in the DSI Host timeout counter configuration registers (DSI_TCCR0 to DSI_TCCR5).
The flow control is configured thanks to the DSI Host protocol configuration register (DSI_PCR). The configuration parameters are the following
Their values depends on the protocol to be used for the communication with the DSI display.
The virtual channel ID used for the generic DBI interface shall be configured by the virtual channel ID (VCID) field of the DSI Host generic VCID register (DSI_GVCIDR).
All the DCS command, depending on their type, can be transmitted or received either in high-speed or low-power. For each of them, a dedicated configuration bit shall be programmed in the DSI Host command mode configuration register (DSI_CMCR).
Acknowledge request for packet or tearing effect event shall also be configured in the DSI Host command mode configuration register (DSI_CMCR).
As the DSI Host is interface to the system through the LTDC for video mode or adapted command mode, the DSI wrapper perform a low level interfacing in between.
The parameter programmed into the DSI wrapper must be aligned with the parameters programmed into the LTDC and the DSI Host.
The following fields must be configured:
The video mode configuration shall defines the behavior of the controller in low-power for command transmission, the type of video transmission (burst or non-burst mode) and the panel horizontal and vertical timing:
Burst mode:
Configure the video mode type (DSI_VMCR.VMT) with value 2'b1x.
Configure the video packet size (DSI_VPCR.VPSIZE) with the size of the active line period, measured in pixels.
The registers DSI_VCCR and DSI_VNPCR are ignored by the DSI Host.
Non-burst mode:
Configure the video mode type (DSI_VMCR.VMT) with 2'b00 to enable the transmission of sync pulses or with 2'b01 to enable the transmission of sync events.
Configure the video packet size (DSI_VPCR.VPSIZE) with the number of pixels to be transmitted in a single packet. Selecting this value depends on the available memory of the attached peripheral, if the data is first stored, or on the memory you want to select for the FIFO in DSI Host.
Configure the number of chunks (DSI_VCCR.NUMC) with the number of packets to be transmitted per video line. The value of VPSIZE * NUMC is the number of pixels per line of video, except if NUMC is 0, which disables the multi-packets. If you set it to 1, there is still only one packet per line, but it can be part of a chunk, followed by a null packet.
Configure the null packet size (DSI_VNPCR.NPSIZE) with the size of null packets to be inserted as part of the chunks. Setting it to 0 disables null packets.
line, a malfunction occurs. This phenomenon can be avoided by configuring the DSI Host to go to low-power once per line.
Figure 158 illustrates the steps for configuring the DPI packet transmission.
| (omitted) |
Example of video configuration
The following is an example of video packet transmission configuration:
Video resolution:
Configuration steps:
Configure the low-power transitions:
DSI_VMCR[13:8] = 6'b111111, to enable LP in all video period.
DSI_VMCR.VMT = 2'b1x
DSI_VPCR.VPSIZE = 480
The adapted command mode requires the following parameters to be configured:
DSI Host can transmit a color bar pattern without horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli.
Figure 159 shows the programming sequence to send a test pattern:
| (omitted) |
| (omitted) |
Note: The number of pixels of payload is restricted to a multiple of a value provided in Table 133.
There are two ways to configure the software to enter and exit the ULPM:
Clock management for ULPM sequence
The ULPM management state machine is working on the lanebyteclock provided by the D-PHY.
Because the D-PHY is providing the lanebyteclock only when the clock lane is not in ULPM state, it is mandatory to switch the lanebyteclock source of the DSI Host before starting the ULPM mode entry sequence.
The lanebyteclock source is controlled by the RCC. It can be
Process flow to enter the ULPM
Implement the process described in detail in the following procedure to enter the ULPM on both clock lane and data lanes:
Verify that all active lanes are in Stop state and the D-PHY PLL is locked:
One-lane configuration: DSI_PSR[6:4] = 3'h3 and DSI_PSR[1] = 1’h0 and DSI_WISR.PLLS = 1’h1
Two -lanes configuration: DSI_PSR[8:4] = 5'h1B and DSI_PSR[1] = 1’h0 and DSI__WISR.PLLS = 1’h1
Wait until the D-PHY active lanes enter into ULPM:
The DSI Host is now in ULPM.
Process flow to exit the ULPM
Implement the process flow described in the following procedure to exit the ULPM on both clock lane and data lanes:
One-lane configuration:
DSI_PSR[5] = 1'b1
DSI_PSR[3] = 1'b1
Two-lanes configuration:
DSI_PSR[8] = 1'b1
DSI_PSR[5] = 1'b1
DSI_PSR[3] = 1'b1
One-lane configuration:
DSI_PSR[6:4] = 3'h3
DSI_PSR[1] = 1'h0
DSI_WRPCR.PLLEN = 1'b1
Two-lanes configuration:
DSI_PSR[8:4] = 5'h1B
DSI_PSR[1] = 1'h0
DSI_WRPCR.PLLEN = 1'b1
Address offset: 0x0000
Reset value: 0x3133 302A
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VERSION[31:16] |
VERSION[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | VERSION[31:0]: Version of the DSI Host |
|
This read-only register contains the version of the DSI Host |
Address offset: 0x0004
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN |
| rw |
| Bits 31:1 | Reserved, must be kept at reset value. |
| Bit 0 | EN: Enable |
|
This bit configures the DSI Host in either power-up mode or to reset. |
Address offset: 0x0008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
TOCKDIV[7:0] | TXECKDIV[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | TOCKDIV[7:0]: Timeout clock division |
|
This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. |
|
| Bits 7:0 | TXECKDIV[7:0]: TX escape clock division |
|
This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. |
Address offset: 0x000C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] |
|
| rw | rw |
||||||||||||||||||||||||||||||
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | VCID[1:0]: Virtual channel ID |
|
These bits configure the virtual channel ID for the LTDC interface traffic. |
Address offset: 0x0010
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPE | Res. | Res. | Res. | Res. | COLC[3:0] |
|||
| rw | rw | rw | rw | rw |
|||||||||||||||||||||||||||
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | LPE: Loosely packet enable |
|
This bit enables the loosely packed variant to 18-bit configuration |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | COLC[3:0]: Color coding |
|
This field configures the DPI color coding |
Address offset: 0x0014
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSP | VSP | DEP |
| rw | rw | rw |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | HSP: HSYNC polarity |
|
This bit configures the polarity of HSYNC pin. |
|
| Bit 1 | VSP: VSYNC polarity |
|
This bit configures the polarity of VSYNC pin. |
|
| Bit 0 | DEP: Data enable polarity |
|
This bit configures the polarity of data enable pin. |
Address offset: 0x0018
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPSIZE[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLPSIZE[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | LPSIZE[7:0]: Largest packet size |
|
This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. |
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | VLPSIZE[7:0]: VACT largest packet size |
|
This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. |
Address offset: 0x002C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCRXE | ECCRXE | BTAE | ETRXE | ETTXE |
| rw | rw | rw | rw | rw |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | CRCRXE: CRC reception enable |
|
This bit enables the CRC reception and error reporting. |
|
| Bit 3 | ECCRXE: ECC reception enable |
|
This bit enables the ECC reception, error correction, and reporting. |
|
| Bit 2 | BTAE: Bus-turn-around enable |
|
This bit enables the bus-turn-around (BTA) request. |
|
| Bit 1 | ETRXE: EoTp reception enable |
|
This bit enables the EoTp reception. |
|
| Bit 0 | ETTXE: EoTp transmission enable |
|
This bit enables the EoTP transmission. |
Address offset: 0x0030
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] |
|
| r | r |
||||||||||||||||||||||||||||||
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | VCID[1:0]: Virtual channel ID |
|
This field indicates the generic interface read-back virtual channel identification. |
Address offset: 0x0034
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CMDM |
| rw |
| Bits 31:1 | Reserved, must be kept at reset value. |
| Bit 0 | CMDM: Command mode |
|
This bit configures the DSI Host in either video or command mode. |
Address offset: 0x0038
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | PGO | Res. | Res. | Res. | PGM | Res. | Res. | Res. | PGE |
LPCE | FBTAAE | LPHFPE | LPHBPE | LPVAE | LPVFPE | LPVBPE | LPVSAE | Res. | Res. | Res. | Res. | Res. | Res. | VMT[1:0] |
|
| rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | PGO: Pattern generator orientation |
|
This bit configures the color bar orientation. |
|
| Bits 23:21 | Reserved, must be kept at reset value. |
| Bit 20 | PGM: Pattern generator mode |
|
This bit configures the pattern generator mode. |
|
| Bits 19:17 | Reserved, must be kept at reset value. |
| Bit 16 | PGE: Pattern generator enable |
|
This bit enables the video mode pattern generator. |
|
| Bit 15 | LPCE: Low-power command enable |
|
This bit enables the command transmission only in low-power mode. |
|
| Bit 14 | FBTAAE: Frame bus-turn-around acknowledge enable |
|
This bit enables the request for an acknowledge response at the end of a frame. |
|
| Bit 13 | LPHFPE: Low-power horizontal front-porch enable |
|
This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. |
|
| Bit 12 | LPHBPE: Low-power horizontal back-porch enable |
|
This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. |
|
| Bit 11 | LPVAE: Low-power vertical active enable |
|
This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. |
|
| Bit 10 | LPVFPE: Low-power vertical front-porch enable |
|
This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. |
|
| Bit 9 | LPVBPE: Low-power vertical back-porch enable |
|
This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. |
|
| Bit 8 | LPVSAE: Low-power vertical sync active enable |
|
This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. |
|
| Bits 7:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | VMT[1:0]: Video mode type |
|
This field configures the video mode transmission type : |
Address offset: 0x003C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | VPSIZE[13:0] |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | VPSIZE[13:0]: Video packet size |
|
This field configures the number of pixels in a single video packet. |
Address offset: 0x0040
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | NUMC[12:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | NUMC[12:0]: Number of chunks |
|
This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). |
Address offset: 0x0044
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | NPSIZE[12:0] |
||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | NPSIZE[12:0]: Null packet size |
|
This field configures the number of bytes inside a null packet. |
Address offset: 0x0048
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | HSA[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | HSA[11:0]: Horizontal synchronism active duration |
|
This fields configures the horizontal synchronism active period in lane byte clock cycles. |
Address offset: 0x004C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | HBP[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | HBP[11:0]: Horizontal back-porch duration |
|
This fields configures the horizontal back-porch period in lane byte clock cycles. |
Address offset: 0x0050
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | HLINE[14:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bits 14:0 | HLINE[14:0]: Horizontal line duration |
|
This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. |
Address offset: 0x0054
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VSA[9:0] |
|||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VSA[9:0]: Vertical synchronism active duration |
|
This fields configures the vertical synchronism active period measured in number of horizontal lines. |
Address offset: 0x0058
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VBP[9:0] |
|||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VBP[9:0]: Vertical back-porch duration |
|
This fields configures the vertical back-porch period measured in number of horizontal lines. |
Address offset: 0x005C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VFP[9:0] |
|||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VFP[9:0]: Vertical front-porch duration |
|
This fields configures the vertical front-porch period measured in number of horizontal lines. |
Address offset: 0x0060
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | VA[13:0] |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | VA[13:0]: Vertical active duration |
|
This fields configures the vertical active period measured in number of horizontal lines. |
Address offset: 0x0064
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CMDSIZE[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CMDSIZE[15:0]: Command size |
|
This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. |
Address offset: 0x0068
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | MRDPS | Res. | Res. | Res. | Res. | DLWTX | DSR0TX | DSW1TX | DSW0TX |
Res. | GLWTX | GSR 2TX |
GSR 1TX |
GSR 0TX |
GSW 2TX |
GSW 1TX |
GSW 0TX |
Res. | Res. | Res. | Res. | Res. | Res. | ARE | TEARE |
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | MRDPS: Maximum read packet size |
|
This bit configures the maximum read packet size command transmission type: |
|
| Bits 23:20 | Reserved, must be kept at reset value. |
| Bit 19 | DLWTX: DCS long write transmission |
|
This bit configures the DCS long write packet command transmission type: |
|
| Bit 18 | DSR0TX: DCS short read zero parameter transmission |
|
This bit configures the DCS short read packet with zero parameter command transmission type: |
|
| Bit 17 | DSW1TX: DCS short read one parameter transmission |
|
This bit configures the DCS short read packet with one parameter command transmission type: |
|
| Bit 16 | DSW0TX: DCS short write zero parameter transmission |
|
This bit configures the DCS short write packet with zero parameter command transmission type: |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | GLWTX: Generic long write transmission |
|
This bit configures the generic long write packet command transmission type : |
|
| Bit 13 | GSR2TX: Generic short read two parameters transmission |
|
This bit configures the generic short read packet with two parameters command transmission type: |
|
| Bit 12 | GSR1TX: Generic short read one parameters transmission |
|
This bit configures the generic short read packet with one parameters command transmission type: |
|
| Bit 11 | GSR0TX: Generic short read zero parameters transmission |
|
This bit configures the generic short read packet with zero parameters command transmission type: |
|
| Bit 10 | GSW2TX: Generic short write two parameters transmission |
|
This bit configures the generic short write packet with two parameters command transmission type: |
|
| Bit 9 | GSW1TX: Generic short write one parameters transmission |
|
This bit configures the generic short write packet with one parameters command transmission type: |
|
| Bit 8 | GSW0TX: Generic short write zero parameters transmission |
|
This bit configures the generic short write packet with zero parameters command transmission type: |
|
| Bits 7:2 | Reserved, must be kept at reset value. |
| Bit 1 | ARE: Acknowledge request enable |
|
This bit enables the acknowledge request after each packet transmission: |
|
| Bit 0 | TEARE: Tearing effect acknowledge request enable |
|
This bit enables the tearing effect acknowledge request: |
Address offset: 0x006C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WCMSB[7:0] |
WCLSB[7:0] | VCID[1:0] | DT[5:0] |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | WCMSB[7:0]: WordCount MSB |
|
This field configures the most significant byte of the header packet’s word count for long packets, or data 1 for short packets. |
|
| Bits 15:8 | WCLSB[7:0]: WordCount LSB |
|
This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. |
|
| Bits 7:6 | VCID[1:0]: Channel |
|
This field configures the virtual channel ID of the header packet. |
|
| Bits 5:0 | DT[5:0]: Type |
|
This field configures the packet data type of the header packet. |
Address offset: 0x0070
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA4[7:0] | DATA3[7:0] |
DATA2[7:0] | DATA1[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | DATA4[7:0]: Payload byte 4 |
|
This field indicates the byte 4 of the packet payload. |
|
| Bits 23:16 | DATA3[7:0]: Payload byte 3 |
|
This field indicates the byte 3 of the packet payload. |
|
| Bits 15:8 | DATA2[7:0]: Payload byte 2 |
|
This field indicates the byte 2 of the packet payload. |
|
| Bits 7:0 | DATA1[7:0]: Payload byte 1 |
|
This field indicates the byte 1 of the packet payload. |
Address offset: 0x0074
Reset value: 0x0000 0015
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RCB | PRDFF | PRDFE | PWRFF | PWRFE | CMDFF | CMDFE |
| r | r | r | r | r | r | r |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | RCB: Read command busy |
|
This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO: |
|
| Bit 5 | PRDFF: Payload read FIFO full |
|
This bit indicates the full status of the generic read payload FIFO: |
|
| Bit 4 | PRDFE: Payload read FIFO empty |
|
This bit indicates the empty status of the generic read payload FIFO: |
|
| Bit 3 | PWRFF: Payload write FIFO full |
|
This bit indicates the full status of the generic write payload FIFO: |
|
| Bit 2 | PWRFE: Payload write FIFO empty |
|
This bit indicates the empty status of the generic write payload FIFO: |
|
| Bit 1 | CMDFF: Command FIFO full |
|
This bit indicates the full status of the generic command FIFO: |
|
| Bit 0 | CMDFE: Command FIFO empty |
|
This bit indicates the empty status of the generic command FIFO: |
Address offset: 0x0078
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HSTX_TOCNT[15:0] |
LPRX_TOCNT[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | HSTX_TOCNT[15:0]: High-speed transmission timeout counter |
|
This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no sufficient time to switch from high-speed to low-power and back in the period which is from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then you should configure the TOCKDIV and HSTX_TOCNT to be in accordance with: |
|
| Bits 15:0 | LPRX_TOCNT[15:0]: Low-power reception timeout counter |
|
This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). |
Address offset: 0x007C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
HSRD_TOCNT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | HSRD_TOCNT[15:0]: High-speed read timeout counter |
|
This field sets a period for which the DSI Host keeps the link still, after sending a high- |
Address offset: 0x0080
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
LPRD_TOCNT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | LPRD_TOCNT[15:0]: Low-power read timeout counter |
|
This field sets a period for which the DSI Host keeps the link still, after sending a low- |
Address offset: 0x0084
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
HSWR_TOCNT[15:0] |
|||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | PM: Presp mode |
|
When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met:
In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready. |
|
| Bits 23:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | HSWR_TOCNT[15:0]: High-speed write timeout counter |
|
This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. |
Address offset: 0x0088
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
LPWR_TOCNT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | LPWR_TOCNT[15:0]: Low-power write timeout counter |
|
This field sets a period for which the DSI Host keeps the link still, after sending a low- |
Address offset: 0x008C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
BTA_TOCNT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | BTA_TOCNT[15:0]: Bus-turn-around timeout counter |
|
This field sets a period for which the DSI Host keeps the link still, after completing a bus- |
Address offset: 0x0094
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ACR | DPCC |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | ACR: Automatic clock lane control |
|
This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. |
|
| Bit 0 | DPCC: D-PHY clock control |
|
This bit controls the D-PHY clock state: |
Address offset: 0x0098
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | HS2LP_TIME[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | LP2HS_TIME[9:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||
| Bits 31:26 | Reserved, must be kept at reset value. |
| Bits 25:16 | HS2LP_TIME[9:0]: High-speed to low-power time |
|
This field configures the maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission measured in lane byte clock cycles. |
|
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | LP2HS_TIME[9:0]: Low-power to high-speed time |
|
This field configures the maximum time that the D-PHY clock lane takes to go from low- |
Address offset: 0x009C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HS2LP_TIME[7:0] | LP2HS_TIME[7:0] |
Res. | MRD_TIME[14:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| Bits 31:24 | HS2LP_TIME[7:0]: High-speed To low-power time |
|
This field configures the maximum time that the D-PHY data lanes take to go from high- |
|
| Bits 23:16 | LP2HS_TIME[7:0]: Low-power to high-speed time |
|
This field configures the maximum time that the D-PHY data lanes take to go from low- |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:0 | MRD_TIME[14:0]: Maximum read time |
|
This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. |
Address offset: 0x00A0
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKE | DEN | Res. |
| rw | rw |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | CKE: Clock enable |
|
This bit enables the D-PHY clock lane module: |
|
| Bit 1 | DEN: Digital enable |
|
When set to 0, this bit places the digital section of the D-PHY in the reset state 0: The digital section of the D-PHY is in the reset state. |
|
| Bit 0 | Reserved, must be kept at reset value. |
Address offset: 0x00A4
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
SW_TIME[7:0] | Res. | Res. | Res. | Res. | Res. | Res. | NL[1:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | SW_TIME[7:0]: Stop wait time |
|
This field configures the minimum wait period to request a high-speed transmission after the Stop state. |
|
| Bits 7:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | NL[1:0]: Number of lanes |
|
This field configures the number of active data lanes: |
Address offset: 0x00A8
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UEDL | URDL | UECL | URCL |
| rw | rw | rw | rw |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | UEDL: ULPS exit on data lane |
|
ULPS mode exit on all active data lanes. |
|
| Bit 2 | URDL: ULPS request on data lane |
|
ULPS mode request on all active data lanes. |
|
| Bit 1 | UECL: ULPS exit on clock lane |
|
ULPS mode exit on clock lane. |
|
| Bit 0 | URCL: ULPS request on clock lane |
|
ULPS mode request on clock lane. |
Address offset: 0x00AC
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TX_TRIG[3:0] |
|||
| rw | rw | rw | rw |
||||||||||||||||||||||||||||
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | TX_TRIG[3:0]: Transmission trigger |
|
Escape mode transmit trigger 0-3. |
Address offset: 0x00B0
Reset value: 0x0000 1528
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | UAN1 | PSS1 | RUE0 | UAN0 | PSS0 | UANC | PSSC | PD | Res. |
| r | r | r | r | r | r | r | r |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | UAN1: ULPS active not lane 1 |
|
This bit indicates the status of ulpsactivenot1lane D-PHY signal. |
|
| Bit 7 | PSS1: PHY stop state lane 1 |
|
This bit indicates the status of phystopstate1lane D-PHY signal. |
|
| Bit 6 | RUE0: RX ULPS escape lane 0 |
|
This bit indicates the status of rxulpsesc0lane D-PHY signal. |
|
| Bit 5 | UAN0: ULPS active not lane 1 |
|
This bit indicates the status of ulpsactivenot0lane D-PHY signal. |
|
| Bit 4 | PSS0: PHY stop state lane 0 |
|
This bit indicates the status of phystopstate0lane D-PHY signal. |
|
| Bit 3 | UANC: ULPS active not clock lane |
|
This bit indicates the status of ulpsactivenotclklane D-PHY signal. |
|
| Bit 2 | PSSC: PHY stop state clock lane |
|
This bit indicates the status of phystopstateclklane D-PHY signal. |
|
| Bit 1 | PD: PHY direction |
|
This bit indicates the status of phydirection D-PHY signal. |
|
| Bit 0 | Reserved, must be kept at reset value. |
Address offset: 0x00BC
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PE4 | PE3 | PE2 | PE1 | PE0 |
AE15 | AE14 | AE13 | AE12 | AE11 | AE10 | AE9 | AE8 | AE7 | AE6 | AE5 | AE4 | AE3 | AE2 | AE1 | AE0 |
| r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | PE4: PHY error 4 |
|
This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. |
|
| Bit 19 | PE3: PHY error 3 |
|
This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. |
|
| Bit 18 | PE2: PHY error 2 |
|
This bit indicates the ErrControl error from lane 0. |
|
| Bit 17 | PE1: PHY error 1 |
|
This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. |
|
| Bit 16 | PE0: PHY error 0 |
|
This bit indicates the ErrEsc escape entry error from lane 0. |
|
| Bit 15 | AE15: Acknowledge error 15 |
|
This bit retrieves the DSI protocol violation from the acknowledge error report. |
|
| Bit 14 | AE14: Acknowledge error 14 |
|
This bit retrieves the reserved (specific to the device) from the acknowledge error report. |
|
| Bit 13 | AE13: Acknowledge error 13 |
|
This bit retrieves the invalid transmission length from the acknowledge error report. |
|
| Bit 12 | AE12: Acknowledge error 12 |
|
This bit retrieves the DSI VC ID Invalid from the acknowledge error report. |
|
| Bit 11 | AE11: Acknowledge error 11 |
|
This bit retrieves the not recognized DSI data type from the acknowledge error report. |
|
| Bit 10 | AE10: Acknowledge error 10 |
|
This bit retrieves the checksum error (long packet only) from the acknowledge error report. |
|
| Bit 9 | AE9: Acknowledge error 9 |
|
This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. |
|
| Bit 8 | AE8: Acknowledge error 8 |
|
This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. |
|
| Bit 7 | AE7: Acknowledge error 7 |
|
This bit retrieves the reserved (specific to the device) from the acknowledge error report. |
|
| Bit 6 | AE6: Acknowledge error 6 |
|
This bit retrieves the false control error from the acknowledge error report. |
|
| Bit 5 | AE5: Acknowledge error 5 |
|
This bit retrieves the peripheral timeout error from the acknowledge error report. |
|
| Bit 4 | AE4: Acknowledge error 4 |
|
This bit retrieves the LP transmit sync error from the acknowledge error report. |
|
| Bit 3 | AE3: Acknowledge error 3 |
|
This bit retrieves the escape mode entry command error from the acknowledge error report. |
|
| Bit 2 | AE2: Acknowledge error 2 |
|
This bit retrieves the EoT sync error from the acknowledge error report. |
|
| Bit 1 | AE1: Acknowledge error 1 |
|
This bit retrieves the SoT sync error from the acknowledge error report. |
|
| Bit 0 | AE0: Acknowledge error 0 |
|
This bit retrieves the SoT error from the acknowledge error report. |
Address offset: 0x00C0
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | GPRXE | GPRDE | GPTXE | GPWRE | GCWRE | LPWRE | EOTPE | PSE | CRCE | ECCME | ECCSE | TOLPRX | TOHSTX |
| r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bit 12 | GPRXE: Generic payload receive error |
|
This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. |
|
| Bit 11 | GPRDE: Generic payload read error |
|
This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. |
|
| Bit 10 | GPTXE: Generic payload transmit error |
|
This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. |
|
| Bit 9 | GPWRE: Generic payload write error |
|
This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. |
|
| Bit 8 | GCWRE: Generic command write error |
|
This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. |
|
| Bit 7 | LPWRE: LTDC payload write error |
|
This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. |
|
| Bit 6 | EOTPE: EoTp error |
|
This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. |
|
| Bit 5 | PSE: Packet size error |
|
This bit indicates that the packet size error is detected during the packet reception. |
|
| Bit 4 | CRCE: CRC error |
|
This bit indicates that the CRC error is detected in the received packet payload. |
|
| Bit 3 | ECCME: ECC multi-bit error |
|
This bit indicates that the ECC multiple error is detected in a received packet. |
|
| Bit 2 | ECCSE: ECC single-bit error |
|
This bit indicates that the ECC single error is detected and corrected in a received packet. |
|
| Bit 1 | TOLPRX: Timeout low-power reception |
|
This bit indicates that the low-power reception timeout counter reached the end and contention is detected. |
|
| Bit 0 | TOHSTX: Timeout high-speed transmission |
|
This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. |
Address offset: 0x00C4
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PE4IE | PE3IE | PE2IE | PE1IE | PE0IE |
AE15IE | AE14IE | AE13IE | AE12IE | AE11IE | AE10IE | AE9IE | AE8IE | AE7IE | AE6IE | AE5IE | AE4IE | AE3IE | AE2IE | AE1IE | AE0IE |
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | PE4IE: PHY error 4 interrupt enable |
|
This bit enables the interrupt generation on PHY error 4. |
|
| Bit 19 | PE3IE: PHY error 3 interrupt enable |
|
This bit enables the interrupt generation on PHY error 4. |
|
| Bit 18 | PE2IE: PHY error 2 interrupt enable |
|
This bit enables the interrupt generation on PHY error 2. |
|
| Bit 17 | PE1IE: PHY error 1 interrupt enable |
|
This bit enables the interrupt generation on PHY error 1. |
|
| Bit 16 | PE0IE: PHY error 0 interrupt enable |
|
This bit enables the interrupt generation on PHY error 0. |
|
| Bit 15 | AE15IE: Acknowledge error 15 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 15. |
|
| Bit 14 | AE14IE: Acknowledge error 14 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 14. |
|
| Bit 13 | AE13IE: Acknowledge error 13 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 13. |
|
| Bit 12 | AE12IE: Acknowledge error 12 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 12. |
|
| Bit 11 | AE11IE: Acknowledge error 11 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 11. |
|
| Bit 10 | AE10IE: Acknowledge error 10 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 10. |
|
| Bit 9 | AE9IE: Acknowledge error 9 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 9. |
|
| Bit 8 | AE8IE: Acknowledge error 8 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 8. |
|
| Bit 7 | AE7IE: Acknowledge error 7 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 7. |
|
| Bit 6 | AE6IE: Acknowledge error 6 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 6. |
|
| Bit 5 | AE5IE: Acknowledge error 5 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 5. |
|
| Bit 4 | AE4IE: Acknowledge error 4 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 4. |
|
| Bit 3 | AE3IE: Acknowledge error 3 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 3. |
|
| Bit 2 | AE2IE: Acknowledge error 2 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 2. |
|
| Bit 1 | AE1IE: Acknowledge error 1 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 1. |
|
| Bit 0 | AE0IE: Acknowledge error 0 interrupt enable |
|
This bit enables the interrupt generation on acknowledge error 0. |
Address offset: 0x00C8
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | GPRXE IE |
GPRDE IE |
GPTXE IE |
GPWRE IE |
GCWR EIE |
LPWR EIE |
EOTPE IE |
PSE IE |
CRCE IE |
ECCM EIE |
ECCSE IE |
TOLPRX IE |
TOHSTX IE |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bit 12 | GPRXEIE: Generic payload receive error interrupt enable |
|
This bit enables the interrupt generation on generic payload receive error. |
|
| Bit 11 | GPRDEIE: Generic payload read error interrupt enable |
|
This bit enables the interrupt generation on generic payload read error. |
|
| Bit 10 | GPTXEIE: Generic payload transmit error interrupt enable |
|
This bit enables the interrupt generation on generic payload transmit error. |
|
| Bit 9 | GPWREIE: Generic payload write error interrupt enable |
|
This bit enables the interrupt generation on generic payload write error. |
|
| Bit 8 | GCWREIE: Generic command write error interrupt enable |
|
This bit enables the interrupt generation on generic command write error. |
|
| Bit 7 | LPWREIE: LTDC payload write error interrupt enable |
|
This bit enables the interrupt generation on LTDC payload write error. |
|
| Bit 6 | EOTPEIE: EoTp error interrupt enable |
|
This bit enables the interrupt generation on EoTp error. |
|
| Bit 5 | PSEIE: Packet size error interrupt enable |
|
This bit enables the interrupt generation on packet size error. |
|
| Bit 4 | CRCEIE: CRC error interrupt enable |
|
This bit enables the interrupt generation on CRC error. |
|
| Bit 3 | ECCMEIE: ECC multi-bit error interrupt enable |
|
This bit enables the interrupt generation on ECC multi-bit error. |
|
| Bit 2 | ECCSEIE: ECC single-bit error interrupt enable |
|
This bit enables the interrupt generation on ECC single-bit error. |
|
| Bit 1 | TOLPRXIE: Timeout low-power reception interrupt enable |
|
This bit enables the interrupt generation on timeout low-power reception. |
|
| Bit 0 | TOHSTXIE: Timeout high-speed transmission interrupt enable |
|
This bit enables the interrupt generation on timeout high-speed transmission . |
Address offset: 0x00D8
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FPE4 | FPE3 | FPE2 | FPE1 | FPE0 |
FAE15 | FAE14 | FAE13 | FAE12 | FAE11 | FAE10 | FAE9 | FAE8 | FAE7 | FAE6 | FAE5 | FAE4 | FAE3 | FAE2 | FAE1 | FAE0 |
| w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | FPE4: Force PHY error 4 |
|
Writing one to this bit forces a PHY error 4. |
|
| Bit 19 | FPE3: Force PHY error 3 |
|
Writing one to this bit forces a PHY error 3. |
|
| Bit 18 | FPE2: Force PHY error 2 |
|
Writing one to this bit forces a PHY error 2. |
|
| Bit 17 | FPE1: Force PHY error 1 |
|
Writing one to this bit forces a PHY error 1. |
|
| Bit 16 | FPE0: Force PHY error 0 |
|
Writing one to this bit forces a PHY error 0. |
|
| Bit 15 | FAE15: Force acknowledge error 15 |
|
Writing one to this bit forces an acknowledge error 15. |
|
| Bit 14 | FAE14: Force acknowledge error 14 |
|
Writing one to this bit forces an acknowledge error 14. |
|
| Bit 13 | FAE13: Force acknowledge error 13 |
|
Writing one to this bit forces an acknowledge error 13. |
|
| Bit 12 | FAE12: Force acknowledge error 12 |
|
Writing one to this bit forces an acknowledge error 12. |
|
| Bit 11 | FAE11: Force acknowledge error 11 |
|
Writing one to this bit forces an acknowledge error 11. |
|
| Bit 10 | FAE10: Force acknowledge error 10 |
|
Writing one to this bit forces an acknowledge error 10. |
|
| Bit 9 | FAE9: Force acknowledge error 9 |
|
Writing one to this bit forces an acknowledge error 9. |
|
| Bit 8 | FAE8: Force acknowledge error 8 |
|
Writing one to this bit forces an acknowledge error 8. |
|
| Bit 7 | FAE7: Force acknowledge error 7 |
|
Writing one to this bit forces an acknowledge error 7. |
|
| Bit 6 | FAE6: Force acknowledge error 6 |
|
Writing one to this bit forces an acknowledge error 6. |
|
| Bit 5 | FAE5: Force acknowledge error 5 |
|
Writing one to this bit forces an acknowledge error 5. |
|
| Bit 4 | FAE4: Force acknowledge error 4 |
|
Writing one to this bit forces an acknowledge error 4. |
|
| Bit 3 | FAE3: Force acknowledge error 3 |
|
Writing one to this bit forces an acknowledge error 3. |
|
| Bit 2 | FAE2: Force acknowledge error 2 |
|
Writing one to this bit forces an acknowledge error 2. |
|
| Bit 1 | FAE1: Force acknowledge error 1 |
|
Writing one to this bit forces an acknowledge error 1. |
|
| Bit 0 | FAE0: Force acknowledge error 0 |
|
Writing one to this bit forces an acknowledge error 0. |
Address offset: 0x00DC
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | FGP RXE |
FGP RDE |
FGP TXE |
FGP WRE |
FGC WRE |
FLP WRE |
FE OTPE |
FPSE | FCRCE | FECC ME |
FECC SE |
FTOLP RX |
FTOHS TX |
| w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bit 12 | FGPRXE: Force generic payload receive error |
|
Writing one to this bit forces a generic payload receive error. |
|
| Bit 11 | FGPRDE: Force generic payload read error |
|
Writing one to this bit forces a generic payload read error. |
|
| Bit 10 | FGPTXE: Force generic payload transmit error |
|
Writing one to this bit forces a generic payload transmit error. |
|
| Bit 9 | FGPWRE: Force generic payload write error |
|
Writing one to this bit forces a generic payload write error. |
|
| Bit 8 | FGCWRE: Force generic command write error |
|
Writing one to this bit forces a generic command write error. |
|
| Bit 7 | FLPWRE: Force LTDC payload write error |
|
Writing one to this bit forces a LTDC payload write error. |
|
| Bit 6 | FEOTPE: Force EoTp error |
|
Writing one to this bit forces a EoTp error. |
|
| Bit 5 | FPSE: Force packet size error |
|
Writing one to this bit forces a packet size error. |
|
| Bit 4 | FCRCE: Force CRC error |
|
Writing one to this bit forces a CRC error. |
|
| Bit 3 | FECCME: Force ECC multi-bit error |
|
Writing one to this bit forces a ECC multi-bit error. |
|
| Bit 2 | FECCSE: Force ECC single-bit error |
|
Writing one to this bit forces a ECC single-bit error. |
|
| Bit 1 | FTOLPRX: Force timeout low-power reception |
|
Writing one to this bit forces a timeout low-power reception. |
|
| Bit 0 | FTOHSTX: Force timeout high-speed transmission |
|
Writing one to this bit forces a timeout high-speed transmission. |
Address offset: 0x0100
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | UR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN |
| rw | rw |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | UR: Update register |
|
When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | EN: Enable |
|
When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. |
Address offset: 0x010C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] |
|
| rw | rw |
||||||||||||||||||||||||||||||
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | VCID[1:0]: Virtual channel ID |
|
This field returns the virtual channel ID for the LTDC interface. |
Address offset: 0x0110
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPE | Res. | Res. | Res. | Res. | COLC[3:0] |
|||
| r | r | r | r | r |
|||||||||||||||||||||||||||
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | LPE: Loosely packed enable |
|
This bit returns the current state of the loosely packed variant to 18-bit configurations. |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | COLC[3:0]: Color coding |
|
This field returns the current LTDC interface color coding |
Address offset: 0x0118
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPSIZE[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLPSIZE[7:0] |
||||||||||||||
| r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:16 | LPSIZE[7:0]: Largest packet size |
|
This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. |
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | VLPSIZE[7:0]: VACT largest packet size |
|
This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. |
Address offset: 0x0138
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | LPCE | FBTAAE | LPHFE | LPHBPE | LPVAE | LPVFPE | LPVBPE | LPVSAE | VMT[1:0] |
|
| r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bit 9 | LPCE: Low-power command enable |
|
This bit returns the current command transmission state in low-power mode. |
|
| Bit 8 | FBTAAE: Frame BTA acknowledge enable |
|
This bit returns the current state of request for an acknowledge response at the end of a frame. |
|
| Bit 7 | LPHFE: Low-power horizontal front-porch enable |
|
This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. |
|
| Bit 6 | LPHBPE: Low-power horizontal back-porch enable |
|
This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. |
|
| Bit 5 | LPVAE: Low-power vertical active enable |
|
This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. |
|
| Bit 4 | LPVFPE: Low-power vertical front-porch enable |
|
This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. |
|
| Bit 3 | LPVBPE: Low-power vertical back-porch enable |
|
This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. |
|
| Bit 2 | LPVSAE: Low-power vertical sync time enable |
|
This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. |
|
| Bits 1:0 | VMT[1:0]: Video mode type |
|
This field returns the current video mode transmission type: |
Address offset: 0x013C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | VPSIZE[13:0] |
|||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | VPSIZE[13:0]: Video packet size |
|
This field returns the number of pixels in a single video packet. |
Address offset: 0x0140
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | NUMC[12:0] |
||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r |
|||||||||||||||||||
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | NUMC[12:0]: Number of chunks |
|
This field returns the number of chunks being transmitted during a line period. |
Address offset: 0x0144
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | NPSIZE[12:0] |
||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r |
|||||||||||||||||||
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | NPSIZE[12:0]: Null packet size |
|
This field returns the number of bytes inside a null packet. |
Address offset: 0x0148
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | HSA[11:0] |
|||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | HSA[11:0]: Horizontal synchronism active duration |
|
This fields returns the horizontal synchronism active period in lane byte clock cycles. |
Address offset: 0x014C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | HBP[11:0] |
|||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | HBP[11:0]: Horizontal back-porch duration |
|
This fields returns the horizontal back-porch period in lane byte clock cycles. |
Address offset: 0x0150
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | HLINE[14:0] |
||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | |||||||||||||||||
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bits 14:0 | HLINE[14:0]: Horizontal line duration |
|
This fields return the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. |
Address offset: 0x0154
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VSA[9:0] |
|||||||||
| r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VSA[9:0]: Vertical synchronism active duration |
|
This fields return the current vertical synchronism active period measured in number of horizontal lines. |
Address offset: 0x0158
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VBP[9:0] |
|||||||||
| r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VBP[9:0]: Vertical back-porch duration |
|
This fields returns the current vertical back-porch period measured in number of horizontal lines. |
Address offset: 0x015C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | VFP[9:0] |
|||||||||
| r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | VFP[9:0]: Vertical front-porch duration |
|
This fields returns the current vertical front-porch period measured in number of horizontal lines. |
Address offset: 0x0160
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | VA[13:0] |
|||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:0 | VA[13:0]: Vertical active duration |
|
This fields returns the current vertical active period measured in number of horizontal lines. |
Address offset: 0x0400
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VSPOL | AR | TEPOL | TESRC | COLMUX[2:0] | DSIM |
||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | VSPOL: VSync polarity |
|
Select the VSync edge on which the LTDC is halted |
|
| Bit 6 | AR: Automatic refresh |
|
Selects the refresh mode in DBI mode |
|
| Bit 5 | TEPOL: TE polarity |
|
Selects the polarity of the external pin tearing effect (TE) source |
|
| Bit 4 | TESRC: TE source |
|
Selects the tearing effect (TE) source |
|
| Bits 3:1 | COLMUX[2:0]: Color multiplexing |
|
Selects the color multiplexing used by DSI Host |
|
| Bit 0 | DSIM: DSI mode |
|
Selects the mode for the video transmission |
Address offset: 0x0404
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DSIEN | LTDCEN | SHTDN | COLM |
| rw | rs | rw | rw |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | DSIEN: DSI enable |
|
Enables the DSI wrapper |
|
| Bit 2 | LTDCEN: LTDC enable |
|
Enables the LTDC for a frame transfer in adapted command mode |
|
| Bit 1 | SHTDN: Shutdown |
|
Controls the display shutdown in video mode: |
|
| Bit 0 | COLM: Color mode |
|
Controls the display color mode in video mode: |
Address offset: 0x0408
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | RRIE | Res. | Res. | PLLUIE | PLLLIE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ERIE | TEIE |
| rw | rw | rw | rw | rw |
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | RRIE: Regulator ready interrupt enable |
|
Enables the regulator ready interrupt |
|
| Bits 12:11 | Reserved, must be kept at reset value. |
| Bit 10 | PLLUIE: PLL unlock interrupt enable |
|
Enables the PLL unlock interrupt |
|
| Bit 9 | PLLLIE: PLL lock interrupt enable |
|
Enables the PLL lock interrupt |
|
| Bits 8:2 | Reserved, must be kept at reset value. |
| Bit 1 | ERIE: End of refresh interrupt enable |
|
Enables the end of refresh interrupt |
|
| Bit 0 | TEIE: Tearing effect interrupt enable |
|
Enables the tearing effect interrupt |
Address offset: 0x040C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | RRIF | RRS | Res. | PLLUIF | PLLLIF | PLLLS | Res. | Res. | Res. | Res. | Res. | BUSY | ERIF | TEIF |
| r | r | r | r | r | r | r | r |
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | RRIF: Regulator ready interrupt flag |
|
This bit is set when the regulator becomes ready: |
|
| Bit 12 | RRS: Regulator ready status |
|
This bit gives the status of the regulator: |
|
| Bit 11 | Reserved, must be kept at reset value. |
| Bit 10 | PLLUIF: PLL unlock interrupt flag |
|
This bit is set when the PLL becomes unlocked: |
|
| Bit 9 | PLLLIF: PLL lock interrupt flag |
|
This bit is set when the PLL becomes locked: |
|
| Bit 8 | PLLLS: PLL lock status |
|
This bit is set when the PLL is locked and cleared when it is unlocked: |
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bit 2 | BUSY: Busy flag |
|
This bit is set when the transfer of a frame in adapted command mode is ongoing: |
|
| Bit 1 | ERIF: End of refresh interrupt flag |
|
This bit is set when the transfer of a frame in adapted command mode is finished: |
|
| Bit 0 | TEIF: Tearing effect interrupt flag |
|
This bit is set when a tearing effect event occurs |
Address offset: 0x0410
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | CRRIF | Res. | Res. | CPLLUIF | CPLLLIF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CERIF | CTEIF |
| w | w | w | w | w |
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | CRRIF: Clear regulator ready interrupt flag |
|
Write 1 clears the RRIF flag in the DSI_WSR register |
|
| Bits 12:11 | Reserved, must be kept at reset value. |
| Bit 10 | CPLLUIF: Clear PLL unlock interrupt flag |
|
Write 1 clears the PLLUIF flag in the DSI_WSR register |
|
| Bit 9 | CPLLLIF: Clear PLL lock interrupt flag |
|
Write 1 clears the PLLLIF flag in the DSI_WSR register |
|
| Bits 8:2 | Reserved, must be kept at reset value. |
| Bit 1 | CERIF: Clear end of refresh interrupt flag |
|
Write 1 clears the ERIF flag in the DSI_WSR register |
|
| Bit 0 | CTEIF: Clear tearing effect interrupt flag |
|
Write 1 clears the TEIF flag in the DSI_WSR register |
Address offset: 0x0418
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | TCLK POSTEN |
TLPXC EN |
THSEXIT EN |
TLPXD EN |
THSZE ROEN |
THST RAILEN |
THSP REPEN |
TCLKZ EROEN |
TCLKP REPEN |
PDEN | Res. | TDDL |
Res. | CDOFF DL |
FTXS MDL |
FTXS MCL |
HSIDL1 | HSIDL0 | HSICL | SWDL1 | SWDL0 | SWCL | UIX4[5:0] |
|||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bit 27 | TCLKPOSTEN: Custom time for tCLK-POST enable |
|
This bit enable the manual programming of tCLK-POST duration in the D-PHY. The desired value must be programmed in the TCLKPOST field of the DSI_WPCR4 register. |
|
| Bit 26 | TLPXCEN: Custom time for tLPX for clock lane enable |
|
This bit enable the manual programming of tLPX duration for the clock lane in the D- |
|
| Bit 25 | THSEXITEN: Custom time for tHS-EXIT enable |
|
This bit enable the manual programming of tHS-EXIT duration in the D-PHY. The desired value must be programmed in the THSEXIT field of the DSI_WPCR3 register. |
|
| Bit 24 | TLPXDEN: Custom time for tLPX for data lanes enable |
|
This bit enable the manual programming of TLPX duration for the data lanes in the D- |
|
| Bit 23 | THSZEROEN: Custom time for tHS-ZERO enable |
|
This bit enable the manual programming of tHS-ZERO duration in the D-PHY. The desired value must be programmed in the THSZERO field of the DSI_WPCR3 register. |
|
| Bit 22 | THSTRAILEN: Custom time for tHS-TRAIL enable |
|
This bit enable the manual programming of THS-TRAIL duration in the D-PHY. The desired value must be programmed in the THSRAIL field of the DSI_WPCR2 register. |
|
| Bit 21 | THSPREPEN: Custom time for tHS-PREPARE enable |
|
This bit enable the manual programming of tHS-PREPARE duration in the D-PHY. The desired value must be programmed in the THSPREP field of the DSI_WPCR2 register. |
|
| Bit 20 | TCLKZEROEN: Custom time for tCLK-ZERO enable |
|
This bit enable the manual programming of tCLK-ZERO duration in the D-PHY. The desired value must be programmed in the TCLKZERO field of the DSI_WPCR2 register. |
|
| Bit 19 | TCLKPREPEN: Custom time for tCLK-PREPARE enable |
|
This bit enable the manual programming of tCLK-PREPARE duration in the D-PHY. The desired value must be programmed in the TLKCPREP field of the DSI_WPCR2 register. |
|
| Bit 18 | PDEN: Pull-down enable |
|
This bit enables a pull-down on the lane to prevent from floating states when unused: |
|
| Bit 17 | Reserved, must be kept at reset value. |
| Bit 16 | TDDL: Turn disable data lanes |
|
This bit forces the data lane to remain in RX event if it receives a bus-turn-around request from the other side: |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | CDOFFDL: Contention detection OFF on data lanes |
|
When only forward escape mode is used, this signal can be made high to switch off the contention detector and reduce static power consumption: |
|
| Bit 13 | FTXSMDL: Force in TX Stop mode the data lanes |
|
This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence: |
|
| Bit 12 | FTXSMCL: Force in TX Stop mode the clock lane |
|
This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence: |
|
| Bit 11 | HSIDL1: Invert the high-speed data signal on data lane 1 |
|
This bit invert the high-speed data signal on data lane 1: |
|
| Bit 10 | HSIDL0: Invert the high-speed data signal on data lane 0 |
|
This bit invert the high-speed data signal on clock lane: |
|
| Bit 9 | HSICL: Invert high-speed data signal on clock lane |
|
This bit invert the high-speed data signal on clock lane: |
|
| Bit 8 | SWDL1: Swap data lane 1 pins |
|
This bit swap the pins on clock lane |
|
| Bit 7 | SWDL0: Swap data lane 0 pins |
|
This bit swap the pins on data lane 0: |
|
| Bit 6 | SWCL: Swap clock lane pins |
|
This bit swap the pins on clock lane: |
|
| Bits 5:0 | UIX4[5:0]: Unit interval multiplied by 4 |
|
This field defines the bit period in high-speed mode in unit of 0.25 ns. |
Address offset: 0x041C
Reset value: 0x0000 0000
Note: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
CR.EN = 0).
| 31 | 30 | 29 | 28 | 27 | 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 | 17 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | LPRXFT[1:0] | Res. | Res. | FLPRXLPM | Res. | Res. | HSTXSRCDL[1:0] | HSTXSRCCL[1:0] |
Res. | Res. | Res. | SDDC | Res. | Res. | LPSRCDL[1:0] | LPSRCL[1:0] | Res. | Res. | HSTXDDL[1:0] | HSTXDCL[1:0] |
||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bits 26:25 | LPRXFT[1:0]: Low-power RX low-pass filtering tuning |
|
This signal can be used to tune the cutoff frequency of low-pass filter at the input of LPRX. |
|
| Bits 24:23 | Reserved, must be kept at reset value. |
| Bit 22 | FLPRXLPM: Forces LP receiver in low-power mode |
|
This bit enables the low-power mode of LP receiver (LPRX). When set, the LPRX |
|
| Bits 21:20 | Reserved, must be kept at reset value. |
| Bits 19:18 | HSTXSRCDL[1:0]: High-speed transmission slew-rate control on data lanes |
|
Slew-rate control for high-speed transmitter output. It can be used to change slew-rate of data lane HS transitions. |
|
| Bits 17:16 | HSTXSRCCL[1:0]: High-speed transmission slew-rate control on clock lane |
|
Slew-rate control for high-speed transmitter output. It can be used to change slew-rate of clock lane HS transitions. |
|
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bit 12 | SDDC: SDD control |
|
Switch on the additional current path to meet the SDDTx parameter defined by MIPI® |
|
| Bits 11:10 | Reserved, must be kept at reset value. |
| Bits 9:8 | LPSRCDL[1:0]: Low-power transmission slew-rate compensation on data lanes |
|
Can be used to change slew-rate of data lane LP transitions. |
|
| Bits 7:6 | LPSRCCL[1:0]: Low-power transmission slew-rate compensation on clock lane |
|
Can be used to change slew-rate of clock lane LP transitions. |
|
| Bits 5:4 | Reserved, must be kept at reset value. |
| Bits 3:2 | HSTXDDL[1:0]: High-speed transmission delay on data lanes |
|
Delay tuner control to change delay (up to DP/DN) in data path. Can be used to change data edge transition positions with respect to clock edge on DP/DN. |
|
| Bits 1:0 | HSTXDCL[1:0]: High-speed transmission delay on clock lane |
|
Delay tuner control to change delay (upto DP/DN) in clock path. Can be used to change clock edge position with respect to data bit transitions on DP/DN. |
Address offset: 0x0420
Reset value: 0x0000 0000
Note: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
CR.EN = 0).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| THSTRAIL[7:0] | THSPREP[7:0] |
TCLKZERO[7:0] | TCLKPREP[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | THSTRAIL: tHSTRAIL |
|
This field defines the tHS-TRAIL has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the THSTRAILEN bit of the DSI_WPCR0 is set. |
|
| Bits 23:16 | THSPREP: tHS-PREPARE |
|
This field defines the tHS-PREPARE has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the THSPREPEN bit of the DSI_WPCR0 is set. |
|
| Bits 15:8 | TCLKZERO: tCLK-ZERO |
|
This field defines the tCLK-ZERO has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the TCLKZEROEN bit of the DSI_WPCR0 is set. |
|
| Bits 7:0 | TCLKPREP: tCLK-PREPARE |
|
This field defines the tCLK-PREPARE has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the TCLKPREPEN bit of the DSI_WPCR0 is set. |
Address offset: 0x0424
Reset value: 0x0000 0000
Note: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
DSI_CR.EN = 0).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TLPXC[7:0] | THSEXIT[7:0] |
TLPXD[7:0] | THSZERO[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | TLPXC: tLPXC for clock lane |
|
This field defines the tLPX has specified in the MIPI® D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. |
|
| Bits 23:16 | THSEXIT: tHSEXIT |
|
This field defines the tHS-EXHigh-SpeedIT has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. |
|
| Bits 15:8 | TLPXD: tLPX for data lanes |
|
This field defines the tLPX has specified in the MIPI® D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. |
|
| Bits 7:0 | THSZERO: tHS-ZERO |
|
This field defines the tHS-ZERO has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. |
Address offset: 0x0428
Reset value: 0x0000 0000
Note: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
DSI_CR.EN = 0).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TCLKPOST[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | TCLKPOST: tCLK-POST |
|
This field defines the tCLK-POST has specified in the MIPI® D-PHY specification. This value is used by the D-PHY when the TCLKPOSTEN bit of the DSI_WPCR0 is set. |
Address offset: 0x0430
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | REGEN | Res. | Res. | Res. | Res. | Res. | Res. | ODF[1:0] |
|
| rw | rw |
||||||||||||||
| rw | rw | rw | rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | IDF[3:0] | Res. | Res. | NDIV[6:0] | Res. | PLLEN |
|||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | REGEN: Regulator enable |
|
This bit enables the DPHY regulator: |
|
| Bits 23:18 | Reserved, must be kept at reset value. |
| Bits 17:16 | ODF[1:0]: PLL output division factor |
|
This field configures the PLL output division factor: |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:11 | IDF[3:0]: PLL input division factor |
|
This field configures the PLL input division factor: |
|
| Bits 10:9 | Reserved, must be kept at reset value. |
| Bits 8:2 | NDIV[6:0]: PLL loop division factor |
|
This field configures the PLL loop division factor: |
|
| Bit 1 | Reserved, must be kept at reset value. |
| Bit 0 | PLLEN: PLL enable |
|
This bit enables the D-PHY PLL: |
The following table summarizes the DSI Host registers. Refer to the register boundary addresses table for the DSI Host register base address.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 | DSI_VR | VERSION[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
|
| 0x0004 |
DSI_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN |
| Reset value | 0 |
||||||||||||||||||||||||||||||||
| 0x0008 |
DSI_CCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TOCKDIV[7:0] | TXECKDIV[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x000C |
DSI_LVCIDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x0010 |
DSI_LCOLCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPE | Res. | Res. | Res. | Res. | COLC[3:0] |
|||
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0014 |
DSI_LPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSP | VSP | DEP |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x0018 |
DSI_LPMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPSIZE[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLPSIZE[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x001C- 0x0028 |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x002C |
DSI_PCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCRXE | ECCRXE | BTAE | ETRXE | ETTXE |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0030 |
DSI_GVCIDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x0034 |
DSI_MCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CMDM |
| Reset value | 1 |
||||||||||||||||||||||||||||||||
| 0x0038 |
DSI_VMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | PGO | Res. | Res. | Res. | PGM | Res. | Res. | Res. | PGE | LPCE | FBTAAE | LPHFPE | LPHBPE | LVAE | LPVFPE | LPVBPE | LPVSAE | Res. | Res. | Res. | Res. | Res. | Res. | VMT[1:0] | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x003C |
DSI_VPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VPSIZE[13:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0040 |
DSI_VCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NUMC[12:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x0044 |
DSI_VNPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NPSIZE[12:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||
| 0x0048 |
DSI_VHSACR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSA[11:0] |
||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x004C |
DSI_VHBPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HBP[11:0] |
||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x0050 |
DSI_VLCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HLINE[14:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0054 |
DSI_VVSACR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VSA[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x0058 |
DSI_VVBPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBP[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x005C |
DSI_VVFPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VFP[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x0060 |
DSI_VVACR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VA[13:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x0064 |
DSI_LCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CMDSIZE[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0068 |
DSI_CMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | MRDPS | Res. | Res. | Res. | Res. | DLWTX | DSR0TX | DSW1TX | DSW0TX | Res. | GLWTX | GSR2TX | GSR1TX | GSR0TX | GSW2TX | GSW1TX | GSW0TX | Res. | Res. | Res. | Res. | Res. | Res. | ARE | TEARE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x006C |
DSI_GHCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WCMSB[7:0] | WCLSB[7:0] | VCID | DT[5:0] |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0070 | DSI_GPDR | DATA4[7:0] | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x0074 |
DSI_GPSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RCB | PRDFF | PRDFE | PWRFF | PWRFE | CMDFF | CMDFE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x0078 | DSI_TCCR0 | HSTX_TOCNT[15:0] | LPRX_TOCNT[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x007C |
DSI_TCCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSRD_TOCNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0080 |
DSI_TCCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPRD_TOCNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0084 |
DSI_TCCR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSWR_TOCNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x0088 |
DSI_TCCR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSWR_TOCNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x008C |
DSI_TCCR5
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BTA_TOCNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0094 |
DSI_CLCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ACR | DPCC |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x0098 |
DSI_CLTCR
|
Res. | Res. | Res. | Res. | Res. | Res. | HS2LP_TIME[9:0] |
Res. | Res. | Res. | Res. | Res. | Res. | LP2HS_TIME[9:0] |
||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x009C | DSI_DLTCR | HS2LP_TIME[7:0] | LP2HS_TIME[7:0] |
Res. | MRD_TIME[14:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||
| 0x00A0 |
DSI_PCTLR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CKE | DEN | Res. |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x00A4 |
DSI_PCCONFR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SW_TIME[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | NL[1:0] | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x00A8 |
DSI_PUCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UEDL | URD | UECL | URC |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x00AC |
DSI_PTTCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TX_TRIG[3:0] | |||
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x00B0 |
DSI_PSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UAN1 | PSS1 | RUE0 | UAN0 | PSS0 | UANC | PSSC | PD | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x00B4 - 0x00B8 |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x00BC |
DSI_ISR0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PE4 | PE3 | PE2 | PE1 | PE0 | AE15 | AE14 | AE13 | AE12 | AE11 | AE10 | AE9 | AE8 | AE7 | AE6 | AE5 | AE4 | AE3 | AE2 | AE1 | AE0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x00C0 |
DSI_ISR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPRXE | GPRDE | GPTXE | GPWRE | GCWRE | LPWRE | EOTPE | PSE | CRCE | ECCME | ECCSE | TOLPRX | TOHSTX |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x00C4 |
DSI_IER0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PE4IE | PE3IE | PE2IE | PE1IE | PE0IE | AE15IE | AE14IE | AE13IE | AE12IE | AE11IE | AE10IE | AE9IE | AE8IE | AE7IE | AE6IE | AE5IE | AE4IE | AE3IE | AE2IE | AE1IE | AE0IE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x00C8 |
DSI_IER1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPRXEIE | GPRDEIE | GPTXEIE | GPWREIE | GCWREIE | LPWREIE | EOTPEIE | PSEIE | CRCEIE | ECCMEIE | ECCSEIE | TOLPRXIE | TOHSTXIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x00CC- 0x00D4 |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x00D8 |
DSI_FIR0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FPE4 | FPE3 | FPE2 | FPE1 | FPE0 | FAE15 | FAE14 | FAE13 | FAE12 | FAE11 | FAE10 | FAE9 | FAE8 | FAE7 | FAE6 | FAE5 | FAE4 | FAE3 | FAE2 | FAE1 | FAE0 |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x00DC |
DSI_FIR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FGPRXE | FGPRDE | FGPTXE | FGPWRE | FGCWRE | FLPWRE | FEOTPE | FPSE | FCRCE | FECCME | FECCSE | FTOLPRX | FTOHSTX |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x00E0 - 0x00FC |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0100 |
DSI_VSCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EN |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x0104 - 0x0108 |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x010C |
DSI_LCVCIDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VCID[1:0] | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x0110 |
DSI_LCCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPE | Res. | Res. | Res. | Res. | COLC[3:0] |
|||
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0114 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0118 |
DSI_LPMCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPSIZE[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLPSIZE[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x011C- 0x0134 |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0138 |
DSI_VMCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LPCE | FBTAAE | LPHFE | LPHBPE | LVAE | LPVFPE | LPVBPE | LPVSAE | VMT[1:0] | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x013C |
DSI_VPCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VPSIZE[13:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0140 |
DSI_VCCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NUMC[12:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x0144 |
DSI_VNPCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NPSIZE[12:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x0148 |
DSI_VHSACCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSA[11:0] |
||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x014C |
DSI_VHBPCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HBP[11:0] |
||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x0150 |
DSI_VLCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HLINE[14:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x0154 |
DSI_VVSACCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VSA[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x0158 |
DSI_VVBPCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBP[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x015C |
DSI_VVFPCCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VFP[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x0160 |
DSI_VVACCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VA[13:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x0164- 0x03FC |
Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0400 |
DSI_WCFGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VSPOL | AR | TEPOL | TESRC | COLMUX[2:0] | DSIM | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x0404 |
DSI_WCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DSIEN | LTDCEN | SHTDN | COLM |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x0408 |
DSI_WIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIE | Res. | Res. | PLLUIE | PLLLIE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ERIE | TEIE |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x040C |
DSI_WISR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RRIF | RRS | Res. | PLLUIF | PLLLIF | PLLLS | Res. | Res. | Res. | Res. | Res. | BUSY | ERIF | TEIF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x0410 |
DSI_WIFCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRRIF | Res. | Res. | CPLLUIF | CPLLLIF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CERIF | CTEIF |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x0414 | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0418 |
DSI_WPCR0
|
Res. | Res. | Res. | Res. | TCLKPOSTEN | TLPXCEN | THSEXITEN | TLPXDEN | THSZEROEN | THSTRAILEN | THSPREPEN | TCLKZEROEN | TCLKPREPEN | PDEN | Res. | TDDL | Res. | CDOFFDL | FTXSMDL | FTXSMCL | HSIDL1 | HSIDL0 | HSICL | SWDL1 | SWDL0 | SWCL | UIX4[:0] |
|||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x041C |
DSI_WPCR1
|
Res. | Res. | Res. | Res. | Res. | LPRXFT[1:0] | Res. | Res. | FLPRXLPM | Res. | Res. | HSTXSRCDL[1:0] | HSTXSRCCL[1:0] | Res. | Res. | Res. | SDCC | Res. | Res. | LPSRDL[1:0] | LPSRCL[1:0] | Res. | Res. | HSTXDLL[1:0] | HSTXDCL[1:0] | |||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0420 | DSI_WPCR2 | THSTRAIL[7:0] | THSPREP[7:0] | TCLKZEO[7:0] | TCLKPREP[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0424 | DSI_WPCR3 | TLPXC[7:0] | THSEXIT[7:0] | TLPXD[7:0] | THSZERO[7:0] |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0428 |
DSI_WPCR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | THSZERO[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x042C | Reserved |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x0430 |
DSI_WRPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | REGEN | Res. | Res. | Res. | Res. | Res. | Res. | ODF[1:0] | Res. | IDF[3:0] |
Res. | Res. | NDIV[6:0] |
Res. | PLLEN | ||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The hardware 8-bit JPEG codec encodes uncompressed image data stream or decodes JPEG-compressed image data stream. It also fully manages JPEG headers.
The block diagram of the JPEG codec is shown in Figure 161: JPEG codec block diagram.
| (omitted) |
The JPEG codec can decode a JPEG stream as defined in the ISO/IEC 10918-1
specification.
It can optionally parse the JPEG header and update accordingly the JPEG codec registers, the quantization tables and the Huffman tables.
The JPEG codec is configured in decode mode setting the DE bit (decode enable) of the JPEG_CONFR1 register.
The JPEG decode starts by setting the START bit of the JPEG_CONFR0 register.
The JPEG codec requests data for its input FIFO through generating one of:
DMA generation for input FIFO
DMA request is generated when the 32-byte input FIFO becomes at least half-empty, that is, when there is free room for writing 16 bytes of data.
The DMA request generation is independent of the START bit of the JPEG_CONFR0 register. If the input FIFO can accept 16 bytes and the DMA for the input FIFO is enabled (setting the IDMAEN bit of the JPEG_CR register), a DMA request is generated regardless of the state of the JPEG codec kernel.
A burst transfer is launched by the DMA to write 16 bytes of data.
Writes are ignored if the input FIFO is full.
At the end of the decoding process, extra bytes may remain in the input FIFO and/or a DMA request may be pending. The FIFO can be flushed by setting the IFF bit (input FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the DMA for the input FIFO must be disabled to prevent unwanted DMA request upon flushing the FIFO.
The consequence of not flushing the FIFO at the end of the decoding process is that any remaining data is taken into the next JPEG decoding.
DMA requests are no more generated once the EOCF flag of the JPEG_SR register is set.
Interrupt generation for input FIFO
Input FIFO can be managed using interrupts through two flags according to the FIFO state:
The interrupt generation is independent of the START bit of the JPEG_CONFR0 register. The input FIFO flags are generated regardless of the state of the JPEG codec kernel.
Writes are ignored if the input FIFO is full.
At the end of the decoding process, extra bytes may remain in the input FIFO and/or an interrupt request may be pending. The FIFO can be flushed by setting the IFF bit (Input FIFO Flush) of the JPEG_CR register.
Prior to flushing the FIFO, the interrupts for the input FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO.
The consequence of not flushing the FIFO at the end of the decoding process is that any remaining data is taken into the next JPEG decoding.
Header parsing
The header parsing can be activated setting the HDR bit of the JPEG_CONFR1 register.
The JPEG header parser supports all markers relevant to the JPEG baseline algorithm indicated in Annex B of the ISO/IEC 10918-1.
When parsing a supported marker, the JPEG header parser extracts the required parameters and stores them in shadow registers. At the end of the parsing the JPEG codec registers are updated.
If a DQT marker segment is located, quantization data associated with it is written into the quantization table memory.
If a DHT marker segment is located, the Huffman table data associated with it is converted into three different table formats (HuffMin, HuffBase and HuffSymb) and stored in their respective memories.
Once the parsing operation is completed, the HPDF (header parsing done flag) bit of the JPEG_SR register is set. An interrupt is generated if the EHPIE (end of header parsing interrupt enable) bit of the JPEG_CR register is set.
JPEG decoding
Once the JPEG header is parsed or JPEG codec registers and memories are properly programmed, the incoming data stream is decoded and the resulting MCUs are sent to the output FIFO.
When decoding two images successively, the START bit of the JPEG_CONFR0 register must be set again (even if already 1) after the header processing of the second image is completed.
DMA generation for output FIFO
DMA request is generated when the 32-byte output FIFO becomes at least half-full, that is, when there are at least 16 bytes of data.
A burst transfer is launched by the DMA to read 16 bytes of data.
Reads return 0 if the output FIFO is empty.
Once the decoding process is done, no extra bytes shall remain in the output FIFO and no DMA request shall be pending as the JPEG decoding generates blocks of 64 bytes.
In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed by setting the OFF bit (input FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the DMA for the output FIFO must be disabled to prevent unwanted DMA request upon flushing the FIFO.
Interrupt generation for output FIFO
The output FIFO can be managed using interrupts through two flags according to the FIFO state:
Reads return 0 if the output FIFO is empty.
In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed. If the FIFO needs to be flushed, it shall be done by software setting the FF bit (FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the interrupts for the output FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO.
The output FIFO must be flushed at the end of processing before any JPEG configuration change.
The JPEG codec can encode a JPEG stream as defined in the ISO/IEC 10918-1
specification.
It can optionally generate the JPEG Header.
The JPEG codec is configured in encode mode resetting the DE bit (decode enable) of the JPEG_CONFR1 register.
The configuration used for encoding the JPEG must be loaded in the JPEG codec:
The JPEG codec is started setting the START bit of the JPEG_CONFR0 register.
Once the JPEG codec has been started, it request data for its input FIFO generating one of:
DMA generation for input FIFO
DMA request is generated when the 32-byte input FIFO becomes at least half-empty, that is, when there is free room for writing 16 bytes of data.
The DMA request generation is independent of the START bit of the JPEG_CONFR0 register. If the input FIFO can accept 16 bytes and the DMA for the input FIFO is enabled (setting the IDMAEN bit of the JPEG_CR register), a DMA request is generated regardless of the state of the JPEG codec kernel.
A burst transfer is launched by the DMA to write 16 bytes of data.
Writes are ignored if the input FIFO is full.
At the end of the encoding process, extra bytes may remain in the input FIFO and/or a DMA request may be pending. The FIFO can be flushed by setting the IFF bit (input FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the DMA for the input FIFO must be disabled to prevent unwanted DMA request upon flushing the FIFO.
The consequence of not flushing the FIFO at the end of the encoding process is that any remaining data is taken into the next JPEG encoding.
The DMA requests are no more generated once the EOCF flag of the JPEG_SR register is set.
Interrupt generation for input FIFO
Input FIFO can be managed using interrupts through two flags according to the FIFO state:
The interrupt generation is independent of the START bit of the JPEG_CONFR0 register. The input FIFO flags are generated regardless of the state of the JPEG codec kernel.
Writes are ignored if the input FIFO is full.
At the end of the encoding process, extra bytes may remain in the input FIFO and/or an interrupt request may be pending. The FIFO can be flushed by setting the IFF bit (input FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the interrupts for the input FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO.
The consequence of not flushing the FIFO at the end of the encoding process is that any remaining data is taken into the next JPEG encoding.
JPEG encoding
Once the JPEG header generated, the incoming MCUs are encoded and the resulting data stream sent to the output FIFO.
DMA generation for output FIFO
DMA request is generated when the 32-byte output FIFO becomes at least half-full, that is, when there are at least 16 bytes of data.
A burst transfer is launched by the DMA to read 16 bytes of data.
Read returns 0 if the output FIFO is empty.
At the end of the encoding process, the last bytes may remain in the output FIFO as the stream padding may not be on 16 bytes.
These additional bytes shall be managed by the CPU using the output FIFO not empty flag.
In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed. The FIFO can be flushed by setting the OFF bit (output FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the DMA for the input FIFO shall be disabled to prevent unwanted DMA request upon flushing the FIFO.
Interrupt generation for output FIFO
Output FIFO can be managed using interrupts through two flags according to the FIFO state:
Reads return 0 if the output FIFO is empty.
In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed. The FIFO can be flushed by setting the FF bit (FIFO flush) of the JPEG_CR register.
Prior to flushing the FIFO, the interrupts for the output FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO.
The output FIFO must be flushed at the end of processing before any JPEG configuration change.
The EOCF bit (end of conversion flag) of the JPEG_SR register can only be cleared when the output FIFO is empty.
Clearing either of the HDR bit (header processing) of the JPEG_CONFR1 register and the JCEN bit (JPEG codec enable) of the JPEG_CR register is allowed only when the EOCF bit of the JPEG_SR register is cleared.
An interrupt can be produced on the following events:
Separate interrupt enable bits are available for flexibility.
| Interrupt event | Event flag | Enable Control bit |
|---|---|---|
| Input FIFO threshold reached | IFTF | IFTIE |
| Input FIFO not full | IFNFF | IFNFIE |
| Output FIFO threshold reached | OFTF | OFTIE |
| Output FIFO not empty | OFNEF | OFNEIE |
| End of conversion | EOCF | EOCIE |
| Header parsing done | HPDF | HPDIE |
Address offset: 0x0000
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | START |
| w |
| Bit 31 | 1 Reserved |
| Bit 0 | START: Start |
|
This bit start or stop the encoding or decoding process. 0: Stop/abort Reads always return 0. |
Address offset: 0x0004
Reset value: 0x0000 0000
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 |
| YSIZE[15:0] |
| rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 6 | 5 4 | 3 | 2 | 1 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | HDR | NS[1:0] | COLSPACE[1:0] | DE | Res. | NF[1:0] |
| Bit 31 | 16 YSIZE[15:0]: Y Size |
|
This field defines the number of lines in source image. |
|
| Bit 15 | 9 Reserved |
| Bit 8 | HDR: Header processing |
|
This bit enables the header processing (generation/parsing). 0: Disable |
|
| Bit 7 | 6 NS[1:0]: Number of components for scan |
|
This field defines the number of components minus 1 for scan header marker segment. |
|
| Bit 5 | 4 COLORSPACE[1:0]: Color space |
|
This filed defines the number of quantization tables minus 1 to insert in the output stream. 00: Grayscale (1 quantization table) |
|
| Bit 3 | DE: Codec operation as coder or decoder |
|
This bit selects the code or decode process 0: Code |
|
| Bit 2 | Reserved |
| Bit 1 | 0 NF[1:0]: Number of color components |
|
This field defines the number of color components minus 1. 00: Grayscale (1 color component) |
Address offset: 0x0008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 24 23 22 21 20 19 18 17 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | NMCU[25:16] |
| rw |
| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| NMCU[15:0] |
| rw |
| Bit 31 | 26 Reserved |
| Bit 25 | 0 NMCU[25:0]: Number of MCUs |
|
For encoding: this field defines the number of MCU units minus 1 to encode. For decoding: this field indicates the number of complete MCU units minus 1 to be decoded (this field is updated after the JPEG header parsing). If the decoded image size has not a X or Y size multiple of 8 or 16 (depending on the sub-sampling process), the resulting incomplete or empty MCU must be added to this value to get the total number of MCUs generated. |
Address offset: 0x000C
Reset value: 0x0000 0000
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 |
| XSIZE[15:0] |
| rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Bit 31 | 16 XSIZE[15:0]: X size |
|
This field defines the number of pixels per line. |
|
| Bit 15 | 0 Reserved |
Address offset: 0x0010 + 0x4 * i, where “i” is image component from 0 to 3
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSF[3:0] | VSF[3:0] | NB[3:0] | QT[1:0] | HA | HD |
| rw | rw | rw | rw | rw | rw |
| Bit 31 | 16 Reserved |
| Bit 15 | 12 HSF[3:0]: Horizontal sampling factor |
|
Horizontal sampling factor for component i. |
|
| Bit 11 | 8 VSF[3:0]: Vertical sampling factor |
|
Vertical sampling factor for component i. |
|
| Bit 7 | 4 NB[3:0]: Number of blocks |
|
Number of data units minus 1 that belong to a particular color in the MCU. |
|
| Bit 3 | 2 QT[1:0]: Quantization table |
|
Selects quantization table used for component i. 00: Quantization table 0 |
|
| Bit 1 | HA: Huffman AC |
|
Selects the Huffman table for encoding AC coefficients. 0: Not selected |
|
| Bit 0 | HD: Huffman DC |
|
Selects the Huffman table for encoding DC coefficients. 0: Not selected |
Address offset: 0x0030
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | OFF | IFF | ODMAEN | IDMAEN | Res. | Res. | Res. | Res. | HPDIE | EOCIE | OFNEIE | OFTIE | IFNFIE | IFTIE | JCEN |
| r0 | r0 | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | 15 Reserved |
| Bit 14 | OFF: Output FIFO flush |
|
This bit flushes the output FIFO. 0: No effect Reads always return 0. |
|
| Bit 13 | IFF: Input FIFO flush |
|
This bit flushes the input FIFO. 0: No effect Reads always return 0. |
|
| Bit 12 | ODMAEN: Output DMA enable |
|
Enables DMA request generation for the output FIFO. 0: Disabled |
|
| Bit 11 | IDMAEN: Input DMA enable |
|
Enables DMA request generation for the input FIFO. 0: Disabled |
|
| Bit 10 | 7 Reserved |
| Bit 6 | HPDIE: Header parsing done interrupt enable |
|
This bit enables interrupt generation upon the completion of the header parsing operation. 0: Disabled |
|
| Bit 5 | EOCIE: End of conversion interrupt enable |
|
This bit enables interrupt generation at the end of conversion. 0: Disabled |
|
| Bit 4 | OFNEIE: Output FIFO not empty interrupt enable |
|
This bit enables interrupt generation when the output FIFO is not empty. 0: Disabled |
|
| Bit 3 | OFTIE: Output FIFO threshold interrupt enable |
|
This bit enables interrupt generation when the output FIFO reaches a threshold. 0: Disabled |
|
| Bit 2 | IFNFIE: Input FIFO not full interrupt enable |
|
This bit enables interrupt generation when the input FIFO is not empty. 0: Disabled |
|
| Bit 1 | IFTIE: Input FIFO threshold interrupt enable |
|
This bit enables interrupt generation when the input FIFO reaches a threshold. 0: Disabled |
|
| Bit 0 | JCEN: JPEG core enable |
|
This bit enables the JPEG codec core. 0: Disabled (internal registers are reset). |
Address offset: 0x0034
Reset value: 0x0000 0006
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COF | HPDF | EOCF | OFNEF | OFTF | IFNFF | IFTF | Res. |
| ro | ro | ro | ro | ro | ro | ro |
| Bit 31 | 8 Reserved |
| Bit 7 | COF: Codec operation flag |
|
This bit flags code/decode operation in progress. 0: Not in progress |
|
| Bit 6 | HPDF: Header parsing done flag |
|
In decode mode, this bit flags the completion of header parsing and updating internal registers. 0: Not completed |
|
| Bit 5 | EOCF: End of conversion flag |
|
This bit flags the completion of encode/decode process and data transfer to the output FIFO. 0: Not completed |
|
| Bit 4 | OFNEF: Output FIFO not empty flag |
|
This bit flags that data is available in the output FIFO. 0: Empty (data not available) |
|
| Bit 4 | OFTF: Output FIFO threshold flag |
|
This bit flags that the amount of data in the output FIFO reaches or exceeds a threshold. 0: Below threshold |
|
| Bit 2 | IFNFF: Input FIFO not full flag |
|
This bit flags that the input FIFO is not full (data can be written). 0: Full |
|
| Bit 1 | IFTF: Input FIFO threshold flag |
|
This bit flags that the amount of data in the input FIFO is below a threshold. 0: At or above threshold |
|
| Bit 0 | Reserved |
Address offset: 0x0038
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CHPDF | CEOCF | Res. | Res. | Res. | Res. | Res. |
| w1c | w1c | Res. | Res. | Res. | Res. | Res. |
| Bit 31 | 7 Reserved |
| Bit 6 | CHPDF: Clear header parsing done flag |
|
Writing 1 clears the HPDF bit of the JPEG_SR register. 0: No effect |
|
| Bit 5 | CEOCF: Clear end of conversion flag |
|
Writing 1 clears the ECF bit of the JPEG_SR register. 0: No effect |
|
| Bit 4 | 0 Reserved |
Address offset: 0x0040
Reset value: 0x0000 0000
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 |
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| DATAIN[31:16] |
DATAIN[15:0] |
| wo |
| wo |
| Bit 31 | 0 DATAIN[31:0]: Data input FIFO |
|
Input FIFO data register. |
Address offset: 0x0044
Reset value: 0x0000 0000
| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 |
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
| DATAOUT[31:16] |
DATAOUT[15:0] |
| ro |
| ro |
| Bit 31 | 0 DATAOUT[31:0]: Data output FIFO |
|
Output FIFO data register. |
The following table summarizes the JPEG codec registers. Refer to the register boundary addresses table for the JPEG codec register base address.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 |
JPEG_CONFR0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | START | |||||||||||||||||||||||||||||||||
| Reset value | 0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0x0004 | JPEG_CONFR1 | YSIZE[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | HDR | NS[1:0] | COLSPACE[1:0] | DE | Res. | NF[1:0] | |||||||||||||||||||||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||
| 0x0008 |
JPEG_CONFR2
|
Res. | Res. | Res. | Res. | Res. | Res. | NMCU[25:0] |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||
| 0x000C | JPEG_CONFR3 | XSIZE[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ||||||||||||||||||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||||||||||
| 0x0010 |
JPEG_CONFR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSF[3:0] | VSF[3:0] | NB[3:0] |
QT[1:0] | HA | HD | |||||||||||||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||||||||||
| 0x0014 |
JPEG_CONFR5
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSF[3:0] | VSF[3:0] | NB[3:0] |
QT[1:0] | HA | HD | |||||||||||||||||||||||||||||||||||||||||||
| 0x0044 | Reset value | DATAOUT[31:0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||||||||
| 0x0018 |
JPEG_CONFR6
|
Reset value | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | Res. | 0 | HSF[3:0] | 0 | 0 | 0 | 0 | VSF[3:0] | 0 | 0 | 0 | 0 | NB[3:0] |
0 | 0 | 0 | 0 | QT[1:0] | 0 | 0 | HA | 0 | HD | 0 |
||||||||||
| 0x0050- 0x014C |
Reset value | QMem RAM |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||||||||
| 0x001C |
JPEG_CONFR7
|
Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | HSF[3:0] | X | X | X | X | VSF[3:0] | X | X | X | X | NB[3:0] |
X | X | X | X | QT[1:0] | X | X | HA | X | HD | X |
|||||||||||
| 0x0150- 0x018C |
Reset value | HuffMin RAM |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||||||||||||||||||||||
| 0x0020- 0x002C |
Reserved |
Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X | Res. | X |
|
| 0x0030 | 0x0190- 0x020C |
JPEG_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HuffBase RAM |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OFF | Res. | IFF | Res. | ODMAEN | Res. | IDMAEN | Res. | Res. | Res. | Res. | Res. | Res. | HuffBase RAM |
Res. | Res. | EOCIE | OFNEIE | OFTIE | IFNFIE | IFTIE | JCEN | ||||||||||||||||
| Reset value | X | X | X | X | X | X | X | X | X | 0 | 0 | 0 | 0 | X | X | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 |
X |
||||||||||||||||||||||||||||||||||||||
| 0x0034 | 0x0210- 0x035C |
JPEG_SR
|
Res. | HuffSymb RAM |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COF | HPDF | EOCF | OFNEF | OFTF | IFNFF | IFTF | Res. | |||||||||||||||||||||||||||||||
| Reset value | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 1 | X | 1 |
X | X |
|||||||||||||||||||||||||||
| 0x0038 | 0x0360- 0x04FC |
JPEG_CFR
|
Res. | DHTMem RAM |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CHPDF | CEOCF | Res. | Res. | Res. | Res. | Res. | |||||||||||||||||||||||||||||||
| Reset value | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | 0 | X | 0 |
X | X | X | X | X | X |
||||||||||||||||||||||||||||||||
| 0x0040 | 0x0500- 0x07FC |
JPEG_DIR | DATAIN[31:0] |
Res. | Res. | Res. | Res. | HuffEnc RAM |
Res. | Res. | Res. | Res. | HuffEnc RAM |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | 0 | 0 | 0 | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X | 0 | X |
||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
The RNG true random number generator has been validated according to the German
AIS-31 standard.
Figure 162 shows the RNG block diagram.
| (omitted) |
Table 147 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads).
| Signal name | Signal type | Description |
|---|---|---|
| rng_it | Digital output | RNG global interrupt request |
| rng_hclk | Digital input | AHB clock |
| rng_clk | Digital input | RNG dedicated clock, asynchronous to rng_hclk |
The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. The RNG implements the entropy source model pictured on Figure 163, and provides three main functions to the application:
| (omitted) |
The main components of the RNG are:
All those components are detailed below.
Noise source
The noise source is the component that contains the non-deterministic, entropy-providing activity that is ultimately responsible for the uncertainty associated with the bitstring output by the entropy source. It is composed of:
This noise source sampling is independent to the AHB interface clock frequency (rng_hclk).
Note: In Section 22.7: Entropy source validation recommended RNG clock frequencies are given.
Post processing
The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level.
The RNG post-processing consists of two stages, applied to each noise source bits:
This component is clocked by the RNG clock.
The times required between two random number generations, and between the RNG initialization and availability of first sample are described in Section 22.6: RNG processing
time.
Output buffer
The RNG_DR data output register can store up to two 16-bit words which have been output from the post-processing component (LFSR). In order to read back 32-bit random samples it is required to wait 42 RNG clock cycles.
Whenever a random number is available through the RNG_DR register the DRDY flag transitions from “0” to “1”. This flag remains high until output buffer becomes empty after reading one word from the RNG_DR register.
Note: When interrupts are enabled an interrupt is generated when this data ready flag transitions
from “0” to “1”. Interrupt is then cleared automatically by the RNG as explained above.
Health checks
This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability.
The RNG implements the following health check features:
The CECS and SECS status bits in the RNG_SR register indicate when an error condition is detected, as detailed in Section 22.3.7: Error management.
Note: An interrupt can be generated when an error is detected.
When a hardware reset occurs the following chain of events occurs:
The associated initialization time can be found in Section 22.6: RNG processing time.
Normal operations
To run the RNG using interrupts the following steps are recommended:
To run the RNG in polling mode following steps are recommended:
Note: When data is not ready (DRDY=”0”) RNG_DR returns zero.
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used, as described in Section 22.4: RNG low-power usage on page 765.
Software post-processing
If a NIST approved DRBG with 128 bits of security strength is required an approved random generator software must be built around the RNG true random number generator.
The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and the post-processing component. The RNG clock is used for noise source sampling. Recommended clock configurations are detailed in Section 22.7: Entropy source validation.
Caution: When the CED bit in the RNG_CR register is set to “0”, the RNG clock frequency must be
higher than AHB clock frequency divided by 16, otherwise the clock checker will flag a clock error (CECS or CEIS in the RNG_SR register) and the RNG will stop producing random numbers.
See Section 22.3.1: RNG block diagram for details (AHB and RNG clock domains).
In parallel to random number generation an health check block verifies the correct noise source behavior and the frequency of the RNG source clock as detailed in this section. Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too low, the RNG stops generating random numbers and sets to “1” both the CEIS and CECS
bits to indicate that a clock error occurred. In this case, the application should check that the RNG clock is configured correctly (see Section 22.3.6: RNG clocking) and then it must clear the CEIS bit interrupt flag. As soon as the RNG clock operates correctly, the CECS bit will be automatically cleared.
The RNG operates only when the CECS flag is set to “0”. However note that the clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can still be used.
Noise source error detection
When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
In order to fully recover from a seed error application must clear the SEIS bit by writing it to “0”, then clear and set the RNGEN bit to reinitialize and restart the RNG.
If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set to “1” by setting the RNGEN bit to “0” in the RNG_CR register. The 32-bit random value stored in the RNG_DR register will be still be available. If a new random is needed the application will need to re-enable the RNG and wait for 42+4 RNG clock cycles.
When disabling the RNG the user deactivates all the analog seed generators, whose power consumption is given in the datasheet electrical characteristics section.
In the RNG an interrupt can be produced on the following events:
Dedicated interrupt enable control bits are available as shown in Table 148
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Data ready flag | DRDY | IE |
| Seed error flag | SEIS | IE |
| Clock error flag | CEIS | IE |
The user can enable or disable the above interrupt sources individually by changing the mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.
The RNG can produce one 32-bit random numbers every 42 RNG clock cycles.
After enabling or re-enabling the RNG using the RNGEN bit it takes 46 RNG clock cycles before random data are available.
In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral against AIS-31 PTG.2 set of tests. The results can be provided on demand or the customer can reproduce the measurements using the AIS reference software. The customer could also test the RNG against an older NIST SP800-22 set of tests.
STMicroelectronics has validated the RNG true random number generator in the following conditions:
If raw data needs to be read instead of pre-processed data the developer is invited to contact STMicroelectronics to receive the correct procedure to follow.
The RNG is associated with a control register, a data register and a status register.
Address offset: 0x000
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CED | Res. | IE | RNGEN | Res. | Res. |
| rw | rw | rw |
| Bits 31:6 | Reserved, must be kept at reset value |
| Bit 5 | CED: Clock error detection |
|
0: Clock error detection is enable The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled. |
|
| Bit 4 | Reserved, must be kept at reset value. |
| Bit 3 | IE: Interrupt Enable |
|
0: RNG Interrupt is disabled |
|
| Bit 2 | RNGEN: True random number generator enable |
|
0: True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x004
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SEIS | CEIS | Res. | Res. | SECS | CECS | DRDY |
| rc_w0 | rc_w0 | r | r | r |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | SEIS: Seed error interrupt status |
|
This bit is set at the same time as SECS. It is cleared by writing it to ‘0’. 0: No faulty sequence detected An interrupt is pending if IE = ‘1’ in the RNG_CR register. |
|
| Bit 5 | CEIS: Clock error interrupt status |
|
This bit is set at the same time as CECS. It is cleared by writing it to ‘0’. 0: The RNG clock is correct (fRNGCLK > fHCLK/16) An interrupt is pending if IE = ‘1’ in the RNG_CR register. |
|
| Bits 4:3 | Reserved, must be kept at reset value. |
| Bit 2 | SECS: Seed error current status |
|
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. |
|
| Bit 1 | CECS: Clock error current status |
|
0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
CECS bit is valid only if the CED bit in the RNG_CR register is set to “0”.
|
|
| Bit 0 | DRDY: Data Ready |
|
0: The RNG_DR register is not yet valid, no random data is available. Once the RNG_DR register has been read, this bit returns to ‘0’ until a new random value is generated. If IE=’1’ in the RNG_CR register, an interrupt is generated when DRDY=’1’. |
Address offset: 0x008
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 42 periods of RNG clock if the output FIFO is empty.
The content of this register is valid when DRDY=’1’, even if RNGEN=’0’.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RNDATA[31:16] |
RNDATA[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | RNDATA[31:0]: Random data |
|
32-bit random data which are valid when DRDY=’1’. When DRDY=’0’ RNDATA value is zero. |
Table 149 gives the RNG register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 | RNG_CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CED | Res. | IE | RNGEN | Res. | Res. |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x004 | RNG_SR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SEIS | CEIS | Res. | Res. | SECS | CECS | DRDY |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x008 | RNG_DR | RNDATA[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
This section applies to all STM32F77xxx devices, unless otherwise specified.
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES or AES algorithms. It is a fully compliant implementation of the following standards:
Multiple key sizes and chaining modes are supported:
The CRYP is a 32-bit AHB peripheral. It supports DMA transfers for incoming and outgoing data (two DMA channels are required). The peripheral also includes input and output FIFOs (each 8 words deep) for better performance.
The CRYP peripheral provides hardware acceleration to AES and DES cryptographic algorithms packaged in STM32 cryptographic library.
Figure 164 shows the block diagram of the cryptographic processor.
| (omitted) |
Table 150 provides a list of useful-to-know internal signals available at cryptographic processor level and not at STM32 product level (on pads).
| Signal name | Signal type | Description |
|---|---|---|
| cryp_hclk | digital input | AHB bus clock |
| cryp_it | digital output | Cryptographic processor global interrupt request |
| cryp_in_dma | digital input/output | IN FIFO DMA burst request/ acknowledge |
| cryp_out_dma | digital input/output |
OUT FIFO DMA burst request/ acknowledge (with single request for DES) |
Overview
The DES/Triple-DES cryptographic core consists of three components:
The DES/Triple-DES cryptographic core provides two operating modes:
The operating mode is selected by programming the ALGODIR bit in the CRYP_CR register.
Typical data processing
Typical usage of the cryptographic processor in DES modes can be found inSection 23.3.10: CRYP DES/TDES basic chaining modes (ECB, CBC).
Note: The outputs of the intermediate DEA stages are never revealed outside the cryptographic
boundary, with the exclusion of the IV registers in CBC mode.
DES keying and chaining modes
The TDES allows three different keying options:
Three independent keys
The first option specifies that all the keys are independent, that is, K1, K2 and K3 are independent. FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to this option as the Keying Option 1 and, to the TDES as 3-key TDES.
Two independent keys
The second option specifies that K1 and K2 are independent and K3 is equal to K1, that is, K1 and K2 are independent, K3 = K1. FIPS PUB 46-3 – 1999 (and ANSI X9.52 TDES.
Three equal keys
The third option specifies that K1, K2 and K3 are equal, that is:
K1 = K2 = K3
FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to the third option as the Keying Option 3. This “1-key” TDES is equivalent to single DES.
The following chaining algorithms are supported by the DES hardware and can be selected through the ALGOMODE bits in the CRYP_CR register:
These modes are described in details in Section 23.3.10: CRYP DES/TDES basic chaining
modes (ECB, CBC).
Overview
The AES cryptographic core consists of the following components:
The AES core works on 128-bit data blocks of (four words) with 128-, 192- or 256-bit key lengths. Depending on the chaining mode, the peripheral requires zero or one 128-bit initialization vector (IV).
The cryptographic peripheral features two operating modes:
The operating mode is selected by programming the ALGODIR bit in the CRYP_CR register.
Typical data processing
A description of cryptographic processor typical usage in AES mode can be found in Section 23.3.11: CRYP AES basic chaining modes (ECB, CBC).
Note: The outputs of the intermediate AEA stages is never revealed outside the cryptographic
boundary, with the exclusion of the IV registers.
AES chaining modes
The following chaining algorithms are supported by the cryptographic processor and can be selected through the ALGOMODE bits in the CRYP_CR register:
A quick introduction on these chaining modes can be found in the following subsections.
For detailed instructions, refer to Section 23.3.11: CRYP AES basic chaining modes (ECB,
CBC) and onward.
AES Electronic CodeBook (ECB)
| (omitted) |
ECB is the simplest operating mode. There are no chaining operations, and no special initialization stage. The message is divided into blocks and each block is encrypted or decrypted separately.
Note: For decryption, a special key scheduling is required before processing the first block.
AES Cipher block chaining (CBC)
| (omitted) |
CBC operating mode chains the output of each block with the input of the following block. To make each message unique, an initialization vector is used during the first block processing.
Note: For decryption,a special key scheduling is required before processing the first block.
AES Counter mode (CTR)
| (omitted) |
The CTR mode uses the AES core to generate a key stream; these keys are then XORed with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation.
Note: Unlike ECB and CBC modes, no key scheduling is required for the CTR decryption, since in
this chaining scheme the AES core is always used in encryption mode for producing the
counter blocks.
AES Galois/Counter mode (GCM)
| (omitted) |
In Galois/Counter mode (GCM), the plaintext message is encrypted, while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special
Publication 800-38D, Recommendation for Block Cipher Modes of Operation -
Galois/Counter Mode (GCM) and GMAC.
GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a fixed finite field for computing the message authentication code. It requires an initial value and a particular 128-bit block at the end of the message.
AES Galois Message Authentication Code (GMAC)
| (omitted) |
Galois Message Authentication Code (GMAC) allows authenticating a message and generating the corresponding message authentication code (MAC). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation -
Galois/Counter Mode (GCM) and GMAC.
GMAC is similar to Galois/Counter mode (GCM), except that it is applied on a message composed only by clear-text authenticated data (i.e. only header, no payload).
AES Counter with CBC-MAC (CCM)
| (omitted) |
In Counter with Cipher Block Chaining-Message Authentication Code (CCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and the corresponding MAC (also known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for Block
Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality.
CCM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code. It requires an initial value.
Like GCM CCM chaining mode, AES-CCM mode can be applied on a message composed only by cleartext authenticated data (i.e. only header, no payload). Note that this way of using CCM is not called CMAC (it is not similar to GCM/GMAC), and its usage is not recommended by NIST.
Introduction
To understand how the cryptographic peripheral operates, a typical cipher operation is described below. For the detailed peripheral usage according to the cipher mode, refer to the specific section, e.g. Section 23.3.11: CRYP AES basic chaining modes (ECB, CBC).
The flowcharts shown in Figure 171 and Figure 172 describe the way STM32 cryptographic library implements DES (respectively AES) algorithm. The cryptographic processor accelerates the execution of the following cryptographic algorithms:
Note: For more details on the cryptographic library, refer to use manual UM1924 “STM32 crypto
library” available from www.st.com.
| (omitted) |
| (omitted) |
CRYP initialization
bit is set automatically. Wait until BUSY returns to 0 (CRYPEN is automatically cleared as well): the key is prepared for decryption.
Preliminary warning for all cases
If the ECB or CBC mode is selected and data are not a multiple of 64 bits (for DES) or 128 bits (for AES), the second and the last block management is more complex than the sequences below. Refer to Section 23.3.8: CRYP stealing and data padding for more details.
Appending data using the CPU in polling mode
Appending data using the CPU in interrupt mode
Appending data using the DMA
Caution: It is important that DMA controller empties the cryptographic processor output FIFO before filling up the cryptographic processor input FIFO. To achieve this, the DMA controller should be configured so that the transfer from the cryptographic peripheral to the memory has a higher priority than the transfer from the memory to the cryptographic peripheral.
The cryptographic processor is busy and processing data (BUSY set to 1 in CRYP_SR register) when all the conditions below are met:
Write operations to the CRYP_Kx(L/R)R key registers, to the CRYP_IVx(L/R)R initialization registers, or to bits [9:2] of the CRYP_CR register, are ignored when cryptographic processor is busy (i.e. the registers are not modified). It is thus not possible to modify the configuration of the cryptographic processor while it is processing a data block.
It is possible to clear the CRYPEN bit while BUSY bit is set to 1. In this case the ongoing DES/TDES or AES processing first completes (i.e. the word results are written to the output FIFO) before the BUSY bit is cleared by hardware.
Note: If the application needs to suspend a message to process another one with a higher priority,
refer to Section 23.3.9: CRYP suspend/resume operations
When a block is being processed in DES or TDES mode, if the output FIFO becomes full and the input FIFO contains at least one new block, then the new block is popped off the
input FIFO and the BUSY bit remains high until there is enough space to store this new block into the output FIFO.
When performing an AES ECB or CBC decryption, the AES key has to be prepared, i.e. a complete key schedule of encryption is required before performing the decryption. In other words, the key in the last round of encryption must be used as the first round key for decryption.
This preparation is not required in any other AES modes than AES ECB or CBC decryption.
If the application software stores somehow the initial key prepared for decryption, the key scheduling operation can be performed only once for all the data to be decrypted with a given cipher key.
Note: The latency of the key preparation operation is 14, 16 or 18 clock cycles depending on the
key size (128-, 192- or 256-bit).
The CRYP key preparation process is performed as follow:
Note: As the CRYPEN bitfield is reset by hardware at the end of the key preparation, the
application software must set it again for the next operation.
When using DES or AES algorithm in ECB or CBC modes to manage messages that are not multiple of the block size (64 bits for DES, 128 bits for AES), use ciphertext stealing techniques such as those described in NIST Special Publication 800-38A, Recommendation
for Block Cipher Modes of Operation: Three Variants of Ciphertext Stealing for CBC Mode. Since the cryptographic processor does not implement such techniques, the last two
blocks must be handled in a special way by the application.
Note: Ciphertext stealing techniques are not documented in this reference manual.
Similarly, when the AES algorithm is used in other modes than ECB or CBC, incomplete input data blocks (i.e. block shorter than 128 bits) have to be padded with zeroes by the application prior to encryption (i.e. extra bits should be appended to the trailing end of the data string). After decryption, the extra bits have to be discarded. The cryptographic processor does not implement automatic data padding operation to the last block, so the application should follow the recommendation given in Section 23.3.5: CRYP procedure to
perform a cipher operation to manage messages that are not multiple of 128 bits.
Note: Padding data are swapped in a similar way as normal data, according to the DATATYPE
field in CRYP_CR register (see Section 23.3.16: CRYP data registers and data swapping for
details).
With this version of cryptographic processor, a special workaround is required in order to properly compute authentication tags while doing a GCM encryption or a CCM decryption
with the last block of payload size inferior to 128 bits. This workaround is described below:
In the intermediate data (intdata_o which was generated with CTR), set to 0 the bits corresponding to the padded bits of the last payload block, XOR with temp1, XOR with temp2, and insert the resulting data into CRYP_DIN register. In other words:
CRYP_DIN=(intdata_o AND mask) XOR temp1 XOR temp2.
A message can be suspended if another message with a higher priority has to be processed. When this highest priority message has been sent, the suspended message can be resumed in both encryption or decryption mode.
Suspend/resume operations do not break the chaining operation and the message processing can be resumed as soon as cryptographic processor is enabled again to receive the next data block.
Figure 173 gives an example of suspend.resume operation: message 1 is suspended in order to send a higher priority message (message 2), which is shorter than message 1 (AES algorithm).
| (omitted) |
A detailed description of suspend/resume operations can be found in each AES mode section.
Overview
FIPS PUB 46-3 – 1999 (and ANSI X9.52-1998) provides a thorough explanation of the processing involved in the four operation modes supplied by the DES computing core: TDES-ECB encryption, TDES-ECB decryption, TDES-CBC encryption and TDES-CBC decryption. This section only gives a brief explanation of each mode.
DES/TDES-ECB encryption
Figure 174 illustrates the encryption in DES and TDES Electronic CodeBook (DES/TDES-ECB) mode. This mode is selected by writing in ALGOMODE to 0b000 and ALGODIR to 0 in CRYP_CR.
| (omitted) |
A 64-bit plaintext data block (P) is used after bit/byte/half-word as the input block (I). The input block is processed through the DEA in the encrypt state using K1. The output of this process is fed back directly to the input of the DEA where the DES is performed in the decrypt state using K2. The output of this process is fed back directly to the input of the DEA where the DES is performed in the encrypt state using K3. The resultant 64-bit output block (O) is used, after bit/byte/half-word swapping, as ciphertext (C) and it is pushed into the OUT FIFO.
Note: For more information on data swapping, refer to Section 23.3.16: CRYP data registers and
data swapping
.
Detailed DES/TDES encryption sequence can be found in Section 23.3.5: CRYP procedure
to perform a cipher operation
.
DES/TDES-ECB mode decryption
Figure 175 illustrates the decryption in DES and TDES Electronic CodeBook (DES/TDES-ECB) mode. This mode is selected by writing ALGOMODE to 0b000 and ALGODIR to 1 in CRYP_CR.
| (omitted) |
A 64-bit ciphertext block (C) is used, after bit/byte/half-word swapping, as the input block (I). The keying sequence is reversed compared to that used in the encryption process. The input block is processed through the DEA in the decrypt state using K3. The output of this process is fed back directly to the input of the DEA where the DES is performed in the encrypt state using K2. The new result is directly fed to the input of the DEA where the DES is performed in the decrypt state using K1. The resultant 64-bit output block (O), after bit/byte/half-word swapping, produces the plaintext (P).
Note: For more information on data swapping refer to Section 23.3.16: CRYP data registers and
data swapping
.
Detailed DES/TDES encryption sequence can be found in Section 23.3.5: CRYP procedure
to perform a cipher operation
.
DES/TDES-CBC encryption
Figure 176 illustrates the encryption in DES and TDES Cipher Block Chaining (DES/TDES-ECB) mode. This mode is selected by writing in ALGOMODE to 0b001 and ALGODIR to 0 in CRYP_CR.
| (omitted) |
K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: initialization vectors.
This mode begins by dividing a plaintext message into 64-bit data blocks. In TCBC encryption, the first input block (I1), obtained after bit/byte/half-word swapping, is formed by exclusive-ORing the first plaintext data block (P1) with a 64-bit initialization vector IV (I1 = IV ⊕ P1). The input block is processed through the DEA in the encrypt state using K1. The output of this process is fed back directly to the input of the DEA, which performs the DES in the decrypt state using K2. The output of this process is fed directly to the input of the DEA, which performs the DES in the encrypt state using K3. The resultant 64-bit output block (O1) is used directly as the ciphertext (C1), that is, C1 = O1.
This first ciphertext block is then exclusive-ORed with the second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second block. The second input block is processed through the TDEA to produce the second ciphertext block.
This encryption process continues to “chain” successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted.
If the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application.
Note: For more information on data swapping refer to Section 23.3.16: CRYP data registers and
data swapping
.
Detailed DES/TDES encryption sequence can be found in Section 23.3.5: CRYP procedure
to perform a cipher operation
.
DES/TDES-CBC decryption
Figure 176 illustrates the decryption in DES and TDES Cipher Block Chaining (DES/TDES-ECB) mode. This mode is selected by writing ALGOMODE to 0b001 and ALGODIR to 1 in CRYP_CR.
| (omitted) |
In this mode the first ciphertext block (C1) is used directly as the input block (I1). The keying sequence is reversed compared to that used for the encrypt process. The input block is processed through the DEA in the decrypt state using K3. The output of this process is fed directly to the input of the DEA where the DES is processed in the encrypt state using K2. This resulting value is directly fed to the input of the DEA where the DES is processed in the decrypt state using K1. The resulting output block is exclusive-ORed with the IV (which must be the same as that used during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV).
The second ciphertext block is then used as the next input block and is processed through the TDEA. The resulting output block is exclusive-ORed with the first ciphertext block to produce the second plaintext data block (P2 = O2 ⊕ C1). Note that P2 and O2 refer to the second block of data.
The DES/TDES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted.
Ciphertext representing a partial data block must be decrypted in a manner specified for the application.
Note: For more information on data swapping refer to Section 23.3.16: CRYP data registers and
data swapping
.
Detailed DES/TDES encryption sequence can be found in Section 23.3.5: CRYP procedure
to perform a cipher operation
.
DES/TDES suspend/resume operations in ECB/CBC modes
Before interrupting the current message, the user application must respect the following steps:
Note: Key registers do not need to be saved as the original key value is known by the application.
To resume message processing, the user application must respect the following sequence:
Overview
FIPS PUB 197 (November 26, 2001) provides a thorough explanation of the processing involved in the four basic operation modes supplied by the AES computing core: AES-ECB encryption, AES-ECB decryption, AES-CBC encryption and AES-CBC decryption. This section only gives a brief explanation of each mode.
AES ECB encryption
Figure 178 illustrates the AES Electronic codebook (AES-ECB) mode encryption. This mode is selected by writing ALGOMODE to 0b100 and ALGODIR to 0 in CRYP_CR.
| (omitted) |
In this mode a 128- bit plaintext data block (P) is used after bit/byte/half-word swapping as the input block (I). The input block is processed through the AEA in the encrypt state using the 128, 192 or 256-bit key. The resultant 128-bit output block (O) is used after bit/byte/half-word swapping as ciphertext (C). It is then pushed into the OUT FIFO.
For more information on data swapping refer to Section 23.3.16: CRYP data registers and
data swapping.
AES ECB decryption
Figure 179 illustrates the AES Electronic codebook (AES-ECB) mode decryption. This mode is selected by writing in ALGOMODE to 0b100 and ALGODIR to 1 in CRYP_CR.
| (omitted) |
To perform an AES decryption in ECB mode, the secret key has to be prepared (it is necessary to execute the complete key schedule for encryption) by collecting the last round key, and using it as the first round key for the decryption of the ciphertext. This preparation phase is computed by the AES core. Refer to Section 23.3.7: Preparing the CRYP AES key
for decryption for more details on how to prepare the key.
When the key preparation is complete, the decryption proceed as follow: a 128-bit ciphertext block (C) is used after bit/byte/half-word swapping as the input block (I). The keying sequence is reversed compared to that of the encryption process. The resultant 128-bit output block (O), after bit/byte or half-word swapping, produces the plaintext (P). The AES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted.
For more information on data swapping refer to Section 23.3.16: CRYP data registers and
data swapping.
AES CBC encryption
Figure 180 illustrates the AES Cipher block chaining (AES-CBC) mode encryption. This mode is selected by writing ALGOMODE to 0b101 and ALGODIR to 0 in CRYP_CR.
| (omitted) |
In this mode the first input block (I1) obtained after bit/byte/half-word swapping is formed by exclusive-ORing the first plaintext data block (P1) with a 128-bit initialization vector IV (I1 = IV ⊕ P1). The input block is processed through the AEA in the encrypt state using the 128-, 192- or 256-bit key (K0...K3). The resultant 128-bit output block (O1) is used directly as ciphertext (C1), that is, C1 = O1. This first ciphertext block is then exclusive-ORed with the second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second block. The second input block is processed through the AEA to produce the second ciphertext block. This encryption process continues to “chain” successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted.
If the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application, as explained in Section 23.3.8: CRYP stealing and data padding.
For more information on data swapping, refer to Section 23.3.16: CRYP data registers and
data swapping.
AES CBC decryption
Figure 181 illustrates the AES Cipher block chaining (AES-CBC) mode decryption. This mode is selected by writing ALGOMODE to 0b101 and ALGODIR to 1 in CRYP_CR.
| (omitted) |
In CBC mode, like in ECB mode, the secret key must be prepared to perform an AES decryption. Refer to Section 23.3.7: Preparing the CRYP AES key for decryption for more details on how to prepare the key.
When the key preparation process is complete, the decryption proceeds as follow: the first 128-bit ciphertext block (C1) is used directly as the input block (I1). The input block is processed through the AEA in the decrypt state using the 128-, 192- or 256-bit key. The resulting output block is exclusive-ORed with the 128-bit initialization vector IV (which must be the same as that used during encryption) to produce the first plaintext block (P1 = O1 ⊕
IV).
The second ciphertext block is then used as the next input block and is processed through the AEA. The resulting output block is exclusive-ORed with the first ciphertext block to produce the second plaintext data block (P2 = O2 ⊕ C1). Note that P2 and O2 refer to the second block of data. The AES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted.
Ciphertext representing a partial data block must be decrypted in a manner specified for the application, as explained in Section 23.3.8: CRYP stealing and data padding.
For more information on data swapping, refer to Section 23.3.16: CRYP data registers and
data swapping.
AES suspend/resume operations in ECB/CBC modes
Before interrupting the current message, the user application must respect the following sequence:
Note: Key registers do not need to be saved as the original key value is known by the application.
To resume message processing, the user application must respect the following sequence:
Overview
The AES counter mode (CTR) uses the AES block as a key stream generator. The generated keys are then XORed with the plaintext to obtain the ciphertext.
CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block
Cipher Modes of Operation. A typical message construction in CTR mode is given in Figure 182.
| (omitted) |
The structure of this message is as below:
AES CTR processing
Figure 183 (respectively Figure 184) describes the AES-CTR encryption (respectively decryption) process implemented within this peripheral. This mode is selected by writing in ALGOMODE bitfield to 0b110 in CRYP_CR.
| (omitted) |
| (omitted) |
In CTR mode, the output block is XORed with the subsequent input block before it is input to the algorithm. Initialization vectors in the peripheral must be initialized as shown on Table 151.
| CRYP_IV1R[31:0] | CRYP_IV1L[31:0] | CRYP_IV0R[31:0] | CRYP_IV0L[31:0] |
|---|---|---|---|
| nonce | IV[63:32] | IV[31:0] | 32-bit counter= 0x1 |
Unlike in CBC mode, which uses the CRYP_IVx registers only once when processing the first data block, in CTR mode IV registers are used for processing each data block, and the peripheral increments the least significant 32 bits (leaving the other most significant 96 bits unchanged).
CTR decryption does not differ from CTR encryption, since the core always encrypts the current counter block to produce the key stream that will be XORed with the plaintext or cipher as input. Thus when ALGOMODE is set to 0b110, ALGODIR is don’t care.
Note: In this mode the key must NOT be prepared for decryption.
The following sequence must be used to perform an encryption or a decryption in CTR chaining mode:
Suspend/resume operations in CTR mode
Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message which was interrupted. Detailed CBC sequence can be found in Section 23.3.11: CRYP AES basic chaining modes (ECB, CBC).
Note: Like for CBC mode, IV registers must be reloaded during the resume operation.
Overview
The AES Galois/counter mode (GCM) allows encrypting and authenticating the plaintext, and generating the correspondent ciphertext and tag (also known as message authentication code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a multiplier over a fixed finite field to generate the tag.
GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block
Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message construction in GCM mode is given in Figure 185.
| (omitted) |
The structure of this message is defined as below:
Note: GCM standard specifies that ciphertext C has same bit length as the plaintext P.
| Endianness | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
|---|---|---|---|---|
| Input data | 0x0 | Header length[31:0] | 0x0 | Payload length[31:0] |
AES GCM processing
This mode is selected by writing ALGOMODE bitfield to 0b110 in CRYP_CR.
The mechanism for the confidentiality of the plaintext in GCM mode is a variation of the Counter mode, with a particular 32-bit incrementing function that generates the necessary sequence of counter blocks.
CRYP_IV registers are used for processing each data block. The cryptographic processor automatically increments the 32 least signification bits of the counter block. The first counter block (CB1) written by the application is equal to the Initial Counter Block incremented by one (see Table 153).
| Register | CRYP_IV1R[31:0] | CRYP_IV1L[31:0] | CRYP_IV0R[31:0] | CRYP_IV0L[31:0] |
|---|---|---|---|---|
| Input data | ICB[127:96] | ICB[95:64] | ICB[63:32] |
ICB[31:0] 32-bit counter= 0x2 |
Note: In this mode the key must NOT be prepared for decryption.
The authentication mechanism in GCM mode is based on a hash function, called GF2mul, that performs multiplication by a fixed parameter, called the hash subkey (H), within a binary Galois field.
To process a GCM message, the driver must go through four phases, which are described in the following subsections.
GCM init phase
During this first step, the GCM hash subkey (H) is calculated and saved internally to be used for processing all the blocks. It is recommended to follow the sequence below:
GCM header phase
The below sequence shall be performed after the GCM init phase. It must be complete before jumping to the payload phase. The sequence is identical for encryption and decryption.
Note: This phase can be skipped if there is no additional authenticated data, i.e. Len(A)=0.
In header and payload phases, CRYPEN bit is not automatically cleared by the
cryptographic processor.
GCM payload phase (encryption or decryption)
When the payload size is not null, this sequence must be executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the CRYP_DOUT register.
Note: This phase can be skipped if there is no payload data, i.e. Len(C)=0 (see GMAC mode).
GCM final phase
In this last step, the cryptographic processor generates the GCM authentication tag and stores it in CRYP_DOUT register.
Note: In this final phase data have to be swapped according to the DATATYPE programmed in
CRYP_CR register.
Suspend/resume operations in GCM mode
Before interrupting the current message in header or payload phase, the user application must respect the following sequence:
Note: Key registers do not need to be saved as original their key value is known by the
application.
To resume message processing, the user must respect the following sequence:
Note: In Header phase, DMA OUT FIFO transfer is not used.
Overview
The Galois message authentication code (GMAC) allows authenticating a plaintext and generating the corresponding tag information (also known as message authentication code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D,
Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and
GMAC.
A typical message construction in GMAC mode is given in Figure 186.
| (omitted) |
AES GMAC processing
This mode is selected by writing ALGOMODE bitfield to 0b110 in CRYP_CR.
GMAC algorithm corresponds to the GCM algorithm applied on a message composed only of an header. As a consequence, all steps and settings are the same as in GCM mode, except that the payload phase (3) is not used.
Suspend/resume operations in GMAC
GMAC is exactly the same as GCM algorithm except that only header phase (2) can be interrupted.
Overview
The AES Counter with Cipher Block Chaining-Message Authentication Code (CCM) algorithm allows encrypting and authenticating the plaintext, and generating the correspondent ciphertext and tag (also known as message authentication code). To ensure confidentiality, CCM algorithm is based on AES counter mode. It uses Cipher Block Chaining technique to generate the message authentication code. This is commonly called CBC-MAC
Note: NIST does not approve this CBC-MAC as an authentication mode outside of the context of
the CCM specification.
CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block
Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality. A typical message construction in CCM mode is given in Figure 187
| (omitted) |
The structure of this message is as below:
Note: The cryptographic peripheral can only manage padded plaintext/ciphertext messages of
length Plen < 236 +1 bytes.
16-bytes blocks (B) associated to the Associated Data (A).
This part of the message is only authenticated, not encrypted. This section has a known length, ALen, that can be a non-multiple of 16 bytes (see Figure 187). The standard also states that, on the MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as defined below:
Note: CCM chaining mode can also be used with associated data only (i.e. no payload).
As an example, the C.1 section in NIST Special Publication 800-38C gives the following:
N: 10111213 141516 (Nlen= 56 bits or 0x7 bytes)
A: 00010203 04050607 (Alen= 64 bits or 0x8 bytes)
P: 20212223 (Plen= 32 bits i.e. Q= 0x4 bytes)
T: 6084341b (Tlen= 32 bits or t= 4)
B0: 4f101112 13141516 00000000 00000004
B1: 00080001 02030405 06070000 00000000
B2: 20212223 00000000 00000000 00000000
CTR0: 0710111213 141516 00000000 00000000
CTR1: 0710111213 141516 00000000 00000001
The usage of control blocks CTRx is explained in the following section. The generation of CTR0 from the first block (B0) must be managed by software.
AES CCM processing
This mode is selected by writing ALGOMODE bitfield to 0b1001 in CRYP_CR.
The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted data to generate a MAC, whose length is known. Counter mode encryption, which requires a sufficiently long sequence of counter blocks as input, is applied to the payload string and separately to the MAC. The resulting data, called the ciphertext C, is the output of the generation-encryption process on plaintext P.
CRYP_IV registers are used for processing each data block. The cryptographic processor automatically increments the CTR counter with a bit length defined by the first block (B0). The first counter written by application, CTR1, is equal to B0 with the first 5 bits zeroed and the most significant bits containing P byte length also zeroed, then incremented by one (see Table 154).
| Register | CRYP_IV0L[31:0] | CRYP_IV0R[31:0] | CRYP_IV1L[31:0] | CRYP_IV1R[31:0] |
|---|---|---|---|---|
| Endianness | IV[0:31] | IV[32:63] | IV[64:95] | IV[96:127] |
| Input data |
B0[31:0], where the 5 most significant bits are set to 0 (flag bits) |
B0[63:32] | B0[95:64] |
B0[127:96], where Q length bits are set to 0, except for bit 0 that is set to 1 |
Note: In this mode, the key must NOT be prepared for decryption.
To process a CCM message, the driver must go through four phases, which are described below.
CCM init phase
In this first step, the first block (B0) of the CCM message is programmed into the CRYP_DIN register. During this phase, the CRYP_DOUT register does not contain any output data. It is recommended to follow the sequence below:
Note: In this init phase data have to be swapped according to the DATATYPE programmed in
CRYP_CR register.
CCM header phase
The below sequence shall be performed after the CCM Init phase. It must be complete before jumping to the payload phase. The sequence is identical for encryption and decryption. During this phase, the CRYP_DOUT register does not contain any output data.
Note: This phase can be skipped if there is no associated data (Alen=0).
Note: The first block of the associated data B1 must be formatted with the associated data length.
This task must be managed by the driver.
CCM payload phase (encryption or decryption)
When the payload size is not null, this sequence must be performed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the CRYP_DOUT register.
Note: This phase can be skipped if there is no payload data, i.e. Plen=0 or Clen=Tlen
Note: Do not forget to remove LSBTlen(C) encrypted tag information when decrypting ciphertext C.
CCM final phase
In this last step, the cryptographic processor generates the CCM authentication tag and stores it in the CRYP_DOUT register.
Note: In this final phase, data have to be swapped according to the DATATYPE programmed in
CRYP_CR register.
Suspend/resume operations in CCM mode
Before interrupting the current message in payload phase, the user application must respect the following sequence:
Note: Key registers do not need to be saved as their original key value is known by the
application.
To resume message processing, the user application must respect the following sequence:
Note: In Header phase DMA OUT FIFO transfer is not used.
Introduction
The CRYP_DIN register is the 32-bit wide data input register of the peripheral. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time.
The first word written into the FIFO is the LSB of the input block. The MSB of the input block is written at the end. CRYP_DIN data endianness can be described as below when DATATYPE=”00” (no data swapping):
In the DES/TDES modes
(leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word
second word entered into the FIFO.
In the AES mode
(leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word
word written into the FIFO.
Similarly CRYP_DOUT register is the 32-bit wide data out register of the peripheral. It is a read-only register that is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time.
Like for the input data, the LSB of the output block is the first word read from the output FIFO. The MSB of the output block is read at the end. CRYP_DOUT data endianness can be described as below when DATATYPE=”00” (no data swapping):
In the DES/TDES modes
(leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word
word read from the FIFO.
In the AES mode
(leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word
word read from the FIFO.
DES/TDES data swapping feature
Depending on the type of data to be processed (e.g. byte swapping when data are ASCII text stream), a bit, byte, half-word or no swapping operation must be done on the data read from the input FIFO before entering the little-endian DES processing core. The same swapping must be performed on the data produced by the little-endian DES processing core before they are written to the output FIFO.
Figure 188 shows how the DES processing core 64-bit data block M1...64 is constructed from two consecutive 32-bit words popped into IN FIFO by the driver. This is done according to the DATATYPE bitfield in the CRYP_CR register.
Note: The same swapping is performed between the IN FIFO and the CRYP data block, and
between the CRYP data block and the OUT FIFO.
| (omitted) |
Note: The CRYP Key registers (CRYP_Kx(L/R)) and initialization registers (CRYP_IVx(L/R)) are
not sensitive to the swap mode selected. They have a fixed little-endian configuration (refer
to Section 23.3.17 and Section 23.3.18, respectively).
A typical example of data swapping is given in Table 155.
| (omitted) |
AES data swapping feature
Depending on the type of data to be processed (e.g. byte swapping when data are ASCII text stream), a bit, byte, half-word or no swapping operation must be done on data read from the input FIFO before entering the little-endian AES processing core. The same swapping must be performed on the data produced by the little-endian AES processing core before they are written to the output FIFO.
Figure 189 shows how the AES processing core 128-bit data block P0..127 is constructed from four consecutive 32-bit words written by the driver to the CRYP_DIN register. This is done according to the DATATYPE bitfield in the CRYP control register (CRYP_CR).
Note: The same swapping is performed between the CRYP_DIN and the CRYP data block, and
between the CRYP data block and the CRYP_DOUT.
| (omitted) |
Note: The swapping operation concerns only the CRYP_DOUT and CRYP_DIN registers. The
CRYP_KxL/KxR and CRYP_IVxL/IVxR registers are not sensitive to the swap mode
selected.They have a fixed little-endian configuration (refer to Section 23.3.17 and
Section 23.3.18).
Typical examples of data swapping are given in Table 156.
| DATATYPE in CRYP_CR | Swapping performed |
Data block representation (64-bit) 0x4E6F7720 69732074 |
|---|---|---|
| System memory data (little-endian) |
||
| 0b00 | No swapping |
Address @: 0x4E6F7720 (LSB, written first) Address @+4: 0x69732074 |
| 0b01 | Half-word (16-bit) swapping |
Address @: 0x77204E6F (swapped LSB, written first) Address @+4: 0x20746973 |
| 0b10 | Byte (8-bit) swapping |
Address @: 0x20776F4E (swapped LSB, written first) Address @+4: 0x74207369 |
| 0b11 | Bit swapping |
LSB data word: 0x4E6F7720 0b0100 1110 0110 1111 0111 0111 0010 0000 MSB data word: 0x69732074 0b0110 1001 0111 0011 0010 0000 0111 0100 Address @: 0x4EEF672 (swapped LSB, written first) Address @+4: 0x2E04CE96 |
The CRYP_Kx registers are used to store the encryption or decryption keys.
They are organized as eight registers in a little-endian configuration, as shown in Table 157.
| K0LR[31:0] | K0RR[31:0] | K1LR[31:0] | K1RR[31:0] | K2LR[31:0] | K2RR[31:0] | K3LR[31:0] |
K3RR[31:0]
|
| - | - | K1[1:32] | K1[33:64] | K2[1:32] | K2[33:64] | K2[1:32] | K2[33:64] |
| K0LR[31:0] | K0RR[31:0] | K1LR[31:0] | K1RR[31:0] | K2LR[31:0] | K2RR[31:0] | K3LR[31:0] |
K3RR[31:0]
|
| - | - | - | - | k[0:31] | k[32:63] | k[64:95] | k[96:127] |
| K0LR[31:0] | K0RR[31:0] | K1LR[31:0] | K1RR[31:0] | K2LR[31:0] | K2RR[31:0] | K3LR[31:0] |
K3RR[31:0]
|
| - | - | k[0:31] | k[32:63] | k[64:95] | k[96:127] | k[128:159] | k[160:191] |
| K0LR[31:0] | K0RR[31:0] | K1LR[31:0] | K1RR[31:0] | K2LR[31:0] | K2RR[31:0] | K3LR[31:0] |
K3RR[31:0]
|
| k[0:31] | k[32:63] | k[64:95] | k[96:127] | k[128:159] | k[160:191] | k[192:223] | k[224:255] |
Note: DES/TDES keys include 8-bit parity information that are not used by the cryptographic
processor. In other words, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64-bit key value
Kx[1:64] are not used.
Keys are considered as four 64-bit data items. They therefore do not have the same data format and representation in system memory as plaintext or ciphertext data.
Any write operation to the CRYP_Kx(L/R) registers when the BUSY bit is set to 1 in the CRYP_SR register is disregarded (i.e. register content not modified). Thus, the software must check that the BUSY equals 0 before modifying key registers.
Key registers are not affected by the data swapping feature controlled by DATATYPE value in CRYP_CR register.
Refer to Section 23.6: CRYP registers for a detailed description of CRYP_Kx(L/R) registers.
The CRYP_IVxL/IVxR registers are used to store the initialization vector or the nonce, depending on the chaining mode selected. When used, these registers are updated by the core after each computation round of the TDES or AES core.
They are organized as four registers in a little-endian configuration, as shown in Table 158.
| CRYP_IV1R[31:0] | CRYP_IV1L[31:0] | CRYP_IV0R[31:0] | CRYP_IV0L[31:0] |
|---|---|---|---|
| IV[96:127] | IV[64:95] | IV[32:63] | IV[0:31] |
Initialization vector registers are considered as two 64-bit data items. They therefore do not have the same data format and representation in system memory as plaintext or ciphertext data.
Any write operation to the CRYP_IV0...1(L/R) registers when the BUSY bit is set to 1 in the CRYP_SR register is disregarded (i.e. register content not modified). Therefore, the software must check that the BUSY equals 0 in the CRYP_SR register before modifying initialization vectors.
Reading the CRYP_IV0...1(L/R) register returns the latest counter value (useful for managing suspend mode) except for CCM/GCM.
Note: In DES/TDES mode, only CRYP_IV0x are used.
Initialization vector registers are not affected by the data swapping feature controlled by DATATYPE value in CRYP_CR register.
Refer to Section 23.6: CRYP registers for a detailed description of CRYP_IVxL/IVxR registers.
The cryptographic processor provides an interface to connect to the DMA (Direct Memory Access) controller. The DMA operation is controlled through the CRYP DMA control register (CRYP_DMACR).
Data input using DMA
DMA can be enabled for writing data into the cryptographic peripheral by setting the DIEN bit in the CRYP_DMACR register. When this bit is set, the cryptographic processor initiates a DMA request during the INPUT phase each time it requires a word to be written to the CRYP_DIN register.
Table 159 shows the recommended configuration to transfer data from memory to cryptographic processor through the DMA controller.
| DMA channel control register field | Programming recommendation |
|---|---|
| Transfer size |
Message length, multiple of 128-bit. This 128-bit granularity corresponds to two blocks for DES, one block for AES. According to the algorithm and the mode selected, special padding/ ciphertext stealing might be required. Refer to Section 23.3.8: CRYP |
| Source burst size (memory) | CRYP FIFO_size /2 /transfer_width = 4 |
| Destination burst size (peripheral) |
CRYP FIFO_size /2 /transfer_width = 4 (FIFO_size= 8x32-bit, transfer_width= 32-bit) |
| DMA FIFO size | CRYP FIFO_size /2 = 16 bytes |
| Source transfer width (memory) | 32-bit words |
| Destination transfer width (peripheral) | 32-bit words |
| Source address increment (memory) | Yes, after each 32-bit transfer. |
| Destination address increment (peripheral) |
Fixed address of CRYP_DIN shall be used (no increment). |
Data output using DMA
To enable the DMA for reading data from AES peripheral, set the DOEN bit in the CRYP_DMACR register. When this bit is set, the cryptographic processor initiates a DMA request during the OUTPUT phase each time it requires a word to be read from the CRYP_DOUT register.
Table 160 shows the recommended configuration to transfer data from cryptographic processor to memory through the DMA controller.
| DMA channel control register field | Programming recommendation |
|---|---|
| Transfer size |
Message length, multiple of 128-bit. This 128-bit granularity corresponds to two blocks for DES, one block for AES. Depending on the algorithm used, extra bits have to be discarded. |
| Source burst size (peripheral) |
When DES is used: Single transfer (burst size=1) When AES is used: CRYP FIFO_size /2 /transfer_width = 4 |
| Destination burst size (memory) | CRYP FIFO_size /2 /transfer_width = 4 |
| DMA FIFO size | CRYP FIFO_size /2 = 16 bytes |
| Source transfer width (peripheral) | 32-bit words |
| memory transfer width (memory) | 32-bit words |
| Source address increment (peripheral) |
Fixed address of CRYP_DOUT shall be used (no increment). |
| Destination address increment (memory) |
Yes, after each 32-bit transfer. |
DMA mode
When AES is used, the cryptographic processor manages two DMA transfer requests through cryp_in_dma and cryp_out_dma internal input/output signals, which are asserted:
When DES is used, the cryptographic processor manages two DMA transfer requests through cryp_in_dma and cryp_out_dma internal input/output signals, which are asserted:
All request signals are de-asserted if the cryptographic peripheral is disabled or the DMA enable bit is cleared (DIEN bit for the IN FIFO and DOEN bit for the OUT FIFO in the CRYP_DMACR register).
Caution: It is important that DMA controller empties the cryptographic peripheral output FIFO before filling up the CRYP input FIFO. To achieve it, the DMA controller should be configured so
that the transfer from the peripheral to the memory has a higher priority than the transfer from the memory to the peripheral.
For more detailed information on DMA operations, refer to Section 23.3.5: CRYP procedure
to perform a cipher operation.
No error flags are generated by the cryptographic processor.
Overview
There are two individual maskable interrupt sources generated by the cryptographic processor to signal the following events:
These two sources are combined into a single interrupt signal which is the only interrupt signal from the CRYP peripheral that drives the NVIC (nested vectored interrupt controller). The interrupt logic is summarized on Figure 190.
| (omitted) |
You can enable or disable CRYP interrupt sources individually by changing the mask bits in the CRYP_IMSCR register. Setting the appropriate mask bit to 1 enables the interrupt.
The status of the individual maskable interrupt sources can be read either from the CRYP_RISR register, for raw interrupt status, or from the CRYP_MISR register for masked interrupt status. The status of the individual source of event flags can be read from the CRYP_SR register.
Table 161 gives a summary of the available features.
| Interrupt event | Event flag (interrupt status) | Enable control bit | Event flag (source) |
|---|---|---|---|
| Output FIFO full |
OUTRIS, OUTMIS | OUTIM and CRYPEN |
OFFU |
| Output FIFO not empty | OFNE |
||
| Input FIFO not full |
OUTRIS, OUTMIS | INIM and CRYPEN |
IFNF |
| Input FIFO empty | IFEM |
Output FIFO service interrupt - OUTMIS
The output FIFO service interrupt is asserted when there is one or more (32-bit word) data items in the output FIFO. This interrupt is cleared by reading data from the output FIFO until there is no valid (32-bit) word left (that is when the interrupt follows the state of the output FIFO not empty flag OFNE).
The output FIFO service interrupt OUTMIS is NOT enabled with the CRYP enable bit. Consequently, disabling the CRYP will not force the OUTMIS signal low if the output FIFO is not empty.
Input FIFO service interrupt - INMIS
The input FIFO service interrupt is asserted when there are less than four words in the input FIFO. It is cleared by performing write operations to the input FIFO until it holds four or more words.
The input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the INMIS signal is low even if the input FIFO is empty.
The time required to process a 128-bit block for each mode of operation is summarized below.
| Algorithm / Key size | ECB | CBC | CTR |
|---|---|---|---|
| 128b | 14 | 14 | 14 |
| 192b | 16 | 16 | 16 |
| 256b | 18 | 18 | 18 |
| Algorithm / Key size |
GCM | CCM |
||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Init | Header | Payload | Tag | Total | Init | Header | Payload | Tag | Total |
|
| 128b | 24 | 10 | 14 | 14 | 62 | 12 | 14 | 25 | 14 |
65
|
| 192b | 28 | 10 | 16 | 16 | 70 | 14 | 16 | 29 | 16 |
75
|
| 256b | 32 | 10 | 18 | 18 | 78 | 16 | 18 | 33 | 18 | 85 |
The cryptographic core is associated with several control and status registers, eight key registers and four initialization vectors registers.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALGOM ODE[3] |
Res. | GCM_CCMPH[ 1:0] |
CRYPEN | FFLUSH | Res. | Res. | Res. | Res. | KEYSIZE[1:0] | DATATYPE[1:0] | ALGOMODE[2:0] | ALGODIR | Res. | Res. |
||||||||
| rw | rw | rw |
rw | w | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||
| Bits 31:20 | Reserved, must be kept at reset value. |
| Bit 18 | Reserved, must be kept at reset value. |
| Bits 17:16 | GCM_CCMPH[1:0]: GCM or CCM Phase selection |
|
This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected in ALGOMODE field. 00: Init phase |
|
| Bit 15 | CRYPEN: CRYP processor Enable |
|
0: Cryptographic processor peripheral is disabled |
|
| Bit 14 | FFLUSH: CRYP FIFO Flush |
|
0: No FIFO flush |
|
| Bits 13:10 | Reserved, must be kept at reset value. |
| Bits 9:8 | KEYSIZE[1:0]: Key Size selection (AES mode only) |
|
This bitfield defines the bit-length of the key used for the AES cryptographic core. This bitfield is ‘don’t care’ in the DES or TDES modes. |
|
| Bits 7:6 | DATATYPE[1:0]: Data Type selection |
|
This bitfield defines the format of data written in CRYP_DIN or read from CRYP_DOUT registers. For more details refer to Section 23.3.16: CRYP data Writing DATATYPE bits while BUSY=1 has no effect. These bits can only be configured when BUSY=0. |
Bits 19, 5:3 ALGOMODE[3:0]: Algorithm mode
Below definition includes the bit 19:
0000: TDES-ECB (triple-DES Electronic Codebook).
0001: TDES-CBC (triple-DES Cipher Block Chaining).
0010: DES-ECB (simple DES Electronic Codebook).
0011: DES-CBC (simple DES Cipher Block Chaining).
0100: AES-ECB (AES Electronic Codebook).
0101: AES-CBC (AES Cipher Block Chaining).
0110: AES-CTR (AES Counter Mode).
0111: AES key preparation for ECB or CBC decryption.
1000: AES-GCM (Galois Counter Mode) and AES-GMAC (Galois Message Authentication Code mode).
1001: AES-CCM (Counter with CBC-MAC).
Writing ALGOMODE bits while BUSY=1 has no effect. These bits can only be configured when BUSY=0.
| Bit 2 | ALGODIR: Algorithm Direction |
|
0: Encrypt Writing ALGODIR bit while BUSY=1 has no effect. It can only be configured when BUSY=0. |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x04
Reset value: 0x0000 0003
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | OFFU | OFNE | IFNF | IFEM |
| r | r | r | r | r |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | BUSY: Busy bit |
|
0: The CRYP core is not processing any data. The reason is:
ongoing (AES ECB or CBC decryption only). |
|
| Bit 3 | OFFU: Output FIFO full flag |
|
0: Output FIFO is not full |
|
| Bit 2 | OFNE: Output FIFO not empty flag |
|
0: Output FIFO is empty |
|
| Bit 1 | IFNF: Input FIFO not full flag |
|
0: Input FIFO is full |
|
| Bit 0 | IFEM: Input FIFO empty flag |
|
0: Input FIFO is not empty |
Address offset: 0x08
Reset value: 0x0000 0000
The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time.
To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section 23.3.16: CRYP data registers
and data swapping for more details.
When CRYP_DIN register is written to the data are pushed into the input FIFO.
When CRYP_DIN register is read:
Note: After the CRYP_DIN register has been read once or several times, the FIFO must be
flushed by setting the FFLUSH bit prior to processing new data.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATAIN[31:16] |
DATAIN[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATAIN[31:0]: Data Input |
|
On read FIFO is popped (last written value is returned), and its value is returned if CRYPEN=0. If CRYPEN=1 DATAIN register returns an undefined value. |
Address offset: 0x0C
Reset value: 0x0000 0000
The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time.
To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section 23.3.16: CRYP data registers
and data swapping for more details.
When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATAOUT[31:16] |
DATAOUT[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | DATAOUT[31:0]: Data Output |
|
On read returns output FIFO content (pointed to by read pointer), else returns an undefined value. |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOEN | DIEN |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | DOEN: DMA Output Enable |
|
When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. |
|
| Bit 0 | DIEN: DMA Input Enable |
|
When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. |
Address offset: 0x14
Reset value: 0x0000 0000
The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTIM | INIM |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | OUTIM: Output FIFO service interrupt mask |
|
0: Output FIFO service interrupt is masked |
|
| Bit 0 | INIM: Input FIFO service interrupt mask |
|
0: Input FIFO service interrupt is masked |
Address offset: 0x18
Reset value: 0x0000 0001
The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTRIS | INRIS |
| r | r |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | OUTRIS: Output FIFO service raw interrupt status |
|
This bit gives the output FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. |
|
| Bit 0 | INRIS: Input FIFO service raw interrupt status |
|
This bit gives the input FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. |
Address offset: 0x1C
Reset value: 0x0000 0000
The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTMIS | INMIS |
| r | r |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | OUTMIS: Output FIFO service masked interrupt status |
|
This bit gives the output FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. |
|
| Bit 0 | INMIS: Input FIFO service masked interrupt status |
|
This bit gives the input FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. |
Address offset: 0x20
Reset value: 0x0000 0000
CRYP key registers contain the cryptographic keys.
In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register.
For more information refer to Section 23.3.17: CRYP key registers.
Note: Write accesses to these registers are disregarded when the cryptographic processor is busy
(bit BUSY = 1 in the CRYP_SR register)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K255 | K254 | K253 | K252 | K251 | K250 | K249 | K248 | K247 | K246 | K245 | K244 | K243 | K242 | K241 | K240 |
K239 | K238 | K237 | K236 | K235 | K234 | K233 | K232 | K231 | K230 | K229 | K228 | K227 | K226 | K225 | K224 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[255:224]: AES key bit x (x= 224 to 255) |
|
This register is not used in DES mode
|
Address offset: 0x24
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K223 | K222 | K221 | K220 | K219 | K218 | K217 | K216 | K215 | K214 | K213 | K212 | K211 | K210 | K209 | K208 |
K207 | K206 | K205 | K204 | K203 | K202 | K201 | K200 | K199 | K198 | K197 | K196 | K195 | K194 | K193 | K192 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[223:192]: AES key bit x (x= 192 to 223) |
|
This register is not used in DES mode
|
Address offset: 0x28
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K191 | K190 | K189 | K188 | K187 | K186 | K185 | K184 | K183 | K182 | K181 | K180 | K179 | K178 | K177 | K176 |
K175 | K174 | K173 | K172 | K171 | K170 | K169 | K168 | K167 | K166 | K165 | K164 | K163 | K162 | K161 | K160 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[191:160]: AES key bit x (x= 160 to 191) |
|
In DES mode, K192 corresponds to key K1 bit 1 and K160 corresponds to key K1 bit 32. |
Address offset: 0x2C
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K159 | K158 | K157 | K156 | K155 | K154 | K153 | K152 | K151 | K150 | K149 | K148 | K147 | K146 | K145 | K144 |
K143 | K142 | K141 | K140 | K139 | K138 | K137 | K136 | K135 | K134 | K133 | K132 | K131 | K130 | K129 | K128 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[159:128]: AES key bit x (x= 128 to 159) |
|
In DES mode K159 corresponds to key K1 bit 33 and K128 corresponds to key K1 bit 64. |
Address offset: 0x30
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K127 | K126 | K125 | K124 | K123 | K122 | K121 | K120 | K119 | K118 | K117 | K116 | K115 | K114 | K113 | K112 |
K111 | K110 | K109 | K108 | K107 | K106 | K105 | K104 | K103 | K102 | K101 | K100 | K99 | K98 | K97 | K96 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[127:96]: AES key bit x (x= 96 to 127) |
|
In DES mode K127 corresponds to key K2 bit 1 and K96 corresponds to key K2 bit 32. |
Address offset: 0x34
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K95 | K94 | K93 | K92 | K91 | K90 | K89 | K88 | K87 | K86 | K85 | K84 | K83 | K82 | K81 | K80 |
K79 | K78 | K77 | K76 | K75 | K74 | K73 | K72 | K71 | K70 | K69 | K68 | K67 | K66 | K65 | K64 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[95:64]: AES key bit x (x= 64 to 95) |
|
In DES mode K95 corresponds to key K2 bit 33 and K64 corresponds to key K2 bit 64. |
Address offset: 0x38
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K63 | K62 | K61 | K60 | K59 | K58 | K57 | K56 | K55 | K54 | K53 | K52 | K51 | K50 | K49 | K48 |
K47 | K46 | K45 | K44 | K43 | K42 | K41 | K40 | K39 | K38 | K37 | K36 | K35 | K34 | K33 | K32 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[63:32]: AES key bit x (x= 32 to 63) |
|
In DES mode K63 corresponds to key K3 bit 1 and K32 corresponds to key K3 bit 32. |
Address offset: 0x3C
Reset value: 0x0000 0000
Refer to Section 23.6.9: CRYP key register 0L (CRYP_K0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| K31 | K30 | K29 | K28 | K27 | K26 | K25 | K24 | K23 | K22 | K21 | K20 | K19 | K18 | K17 | K16 |
K15 | K14 | K13 | K12 | K11 | K10 | K9 | K8 | K7 | K6 | K5 | K4 | K3 | K2 | K1 | K0 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
| Bits 31:0 | K[31:0]: AES key bit x (x= 0 to 31) |
|
In DES mode K31 corresponds to key K3 bit 33 and K0 corresponds to key K3 bit 64. |
Address offset: 0x40
Reset value: 0x0000 0000
The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section 23.3.18: CRYP initialization vector registers.
IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES.
Note: Write access to these registers are disregarded when the cryptographic processor is busy
(bit BUSY = 1 in the CRYP_SR register).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IV0 | IV1 | IV2 | IV3 | IV4 | IV5 | IV6 | IV7 | IV8 | IV9 | IV10 | IV11 | IV12 | IV13 | IV14 | IV15 |
IV16 | IV17 | IV18 | IV19 | IV20 | IV21 | IV22 | IV23 | IV24 | IV25 | IV26 | IV27 | IV28 | IV29 | IV30 | IV31 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | IV[0:31]: Initialization vector bit x (x= 0 to 31) |
Address offset: 0x44
Reset value: 0x0000 0000
Refer to Section 23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IV32 | IV33 | IV34 | IV35 | IV36 | IV37 | IV38 | IV39 | IV40 | IV41 | IV42 | IV43 | IV44 | IV45 | IV46 | IV47 |
IV48 | IV49 | IV50 | IV51 | IV52 | IV53 | IV54 | IV55 | IV56 | IV57 | IV58 | IV59 | IV60 | IV61 | IV62 | IV63 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | IV[32:63]: Initialization vector bit x (x= 32 to 63) |
Address offset: 0x48
Reset value: 0x0000 0000
Refer to Section 23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IV64 | IV65 | IV66 | IV67 | IV68 | IV69 | IV70 | IV71 | IV72 | IV73 | IV74 | IV75 | IV76 | IV77 | IV78 | IV79 |
IV80 | IV81 | IV82 | IV83 | IV84 | IV85 | IV86 | IV87 | IV88 | IV89 | IV90 | IV91 | IV92 | IV93 | IV94 | IV95 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | IV[64:95]: Initialization vector bit x (x= 64 to 95) |
|
This register is not used in DES mode |
Address offset: 0x4C
Reset value: 0x0000 0000
Refer to Section 23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IV96 | IV97 | IV98 | IV99 | IV100 | IV101 | IV102 | IV103 | IV104 | IV105 | IV106 | IV107 | IV108 | IV109 | IV110 | IV111 |
IV112 | IV113 | IV114 | IV115 | IV116 | IV117 | IV118 | IV119 | IV120 | IV121 | IV122 | IV123 | IV124 | IV125 | IV126 | IV127 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | IV[96:127]: Initialization vector bit x (x= 96 to 127) |
|
This register is not used in DES mode |
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 0x00 |
CRYP_CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALGOMODE[3] | Res. | GCM_CCMPH | CRYPEN | FFLUSH | Res. | Res. | Res. | Res. | KEYSIZE | DATATYPE | ALGOMODE[2:0] | ALGODIR | Res. | Res. | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x04 |
CRYP_SR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | OFFU | OFNE | IFNF | IFEM |
| Reset value | 0 | 0 | 0 | 1 | 1 |
||||||||||||||||||||||||||||
| 0x08 |
CRYP_DIN | DATAIN |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C |
CRYP_DOUT | DATAOUT |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 |
CRYP_DMACR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOEN | DIEN |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x14 |
CRYP_IMSCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTIM | INIM |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x18 |
CRYP_RISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTRIS | INRIS |
| Reset value | 0 | 1 |
|||||||||||||||||||||||||||||||
| 0x1C |
CRYP_MISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OUTMIS | INMIS |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x20 |
CRYP_K0LR | CRYP_K0LR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x24 |
CRYP_K0RR | CRYP_K0RR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| ... ... |
|||||||||||||||||||||||||||||||||
| 0x38 |
CRYP_K3LR | CRYP_K3LR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x3C |
CRYP_K3RR | CRYP_K3RR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x40 |
CRYP_IV0LR | CRYP_IV0LR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x44 |
CRYP_IV0RR | CRYP_IV0RR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x48 |
CRYP_IV1LR | CRYP_IV1LR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x4C |
CRYP_IV1RR | CRYP_IV1RR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
This section applies to the whole STM32F77xxx devices, unless otherwise specified.
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. HMAC is suitable for applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) approved digests of length of 160, 224, 256 bits, for messages of up to (261 – 1) bits. It also computes 128 bits digests for the MD5 algorithm.
SHA-1 (respectively SHA-256) algorithm
Figure 191 shows the block diagram of the hash processor.
| (omitted) |
Table 165 describes a list of useful to know internal signals available at HASH level, not at product level (on pads).
| Signal name | Signal type | Description |
|---|---|---|
| hash_hclk2 | digital input | AHB2 bus clock |
| hash_it | digital output | Hash processor global interrupt request |
| hash_in_dma | digital input/output | DMA burst request/ acknowledge |
The hash processor is a fully compliant implementation of the secure hash algorithm defined by FIPS PUB 180-4 standard and the IETF RFC1321 publication (MD5).
With each algorithm, the HASH computes a condensed representation of a message or data file. More specifically, when a message of any length below 264 bits is provided on input, the SHA-1, SHA-224, SHA-256 and MD5 processing core produces respectively a 160-bit, 224 bit, 256 bit and 128-bit output string called a message digest. The message digest can then be processed with a digital signature algorithm in order to generate or verify the signature for the message.
Signing the message digest rather than the message often improves the efficiency of the process because the message digest is usually much smaller in size than the message. The verifier of a digital signature has to use the same hash algorithm as the one used by the creator of the digital signature.
The SHA-2 functions supported by the hash processor are qualified as “secure” because it is computationally infeasible to find a message that corresponds to a given message digest (SHA-1 is no more qualified as secure since February 2017), or to find two different messages that produce the same message digest. Any change to a message in transit will, with very high probability, result in a different message digest, and the signature will fail to verify.
The message (or data file) to be processed by the HASH should be considered as a bit string. Per FIPS PUB 180-1 and 180-2 standards this message bit string grows from left to right, with hexadecimal words expressed in “big-endian” convention, so that within each word, the most significant bit is stored in the left-most bit position. For example message string “abc” with a bit string representation of “01100001 01100010 01100011” is represented by a 32-bit word 0x00636261, and 8-bit words 0x61626300.
Data are entered into the HASH one 32-bit word at a time, by writing them into the HASH_DIN register. The current contents of the HASH_DIN register are transferred to the 16 words input FIFO (IN FIFO) each time the register is written with new data. Hence HASH_DIN and the input FIFO form a seventeen 32-bit words length FIFO (named the IN buffer).
In accordance to the kind of data to be processed (e.g. byte swapping when data are ASCII text stream) there must be a bit, byte, half-word or no swapping operation to be performed on data from the input FIFO before entering the little-endian hash processing core. Figure 192 shows how the hash processing core 32-bit data block M0...31 is constructed from one 32-bit words popped into IN FIFO by the driver, according to the DATATYPE bitfield in the HASH control register (HASH_CR).
HASH_DIN data endianness when bit swapping is disabled (DATATYPE=”00”) can be described as following: the least significant bit of the message has to be at MSB position in the first word entered into the hash processor, the 32nd bit of the bit string has to be at MSB position in the second word entered into the hash processor and so on.
| (omitted) |
The hash processor sequentially processes 512-bit blocks when computing the message digest. Thus, each time 16 × 32-bit words (= 512 bits) have been written to the hash processor by the DMA or the CPU, the HASH automatically starts computing the message digest. This operation is known as ‘partial digest computation’.
As described in Section 24.3.4: Message data feeding, the message to be processed is entered into the HASH 32-bit word at a time, writing to the HASH_DIN register to fill the input FIFO. In order to perform the hash computation on this data below sequence shall be used by the application.
Caution: When programming step 2, it is important to set up before or at the same time the correct configuration values (ALGO, DATATYPE, HMAC mode, key length, NBLW).
this digest computation. To launch the final digest computation, the software must set MDMAT bit to 0 before the last DMA transfer in order to trigger the final digest computation as it is done for single DMA transfers (see description before).
| Algorithm | Valid output registers | Most significant bit | Digest size (in bits) |
|---|---|---|---|
| MD5 | HASH_H0 to HASH_H3 | HASH_H0[31] | 128 |
| SHA-1 | HASH_H0 to HASH_H4 | HASH_H0[31] | 160 |
| SHA-224 | HASH_H0 to HASH_H6 | HASH_H0[31] | 224 |
| SHA-256 | HASH_H0 to HASH_H7 | HASH_H0[31] | 256 |
For more information about HMAC detailed instructions, refer to Section 24.3.7: HMAC
operation.
Overview
When computing a condensed representation of a message, the process of feeding data into the hash processor (with automatic partial digest computation every 512-bit block) loops until the last bits of the original message are written to the HASH_DIN register.
As the length (number of bits) of a message can be any integer value, the last word written to the hash processor may have a valid number of bits between 1 and 32. This number of valid bits in the last word, NBLW, has to be written to the HASH_STR register, so that message padding is correctly performed before the final message digest computation.
Padding processing
Detailed padding sequences with DMA is enabled or disabled are described in Section 24.3.5: Message digest computing.
Padding example
As specified by Federal Information Processing Standards PUB 180-1 and PUB 180-2, message padding consists in appending a “1” followed by k “0”s, itself followed by a 64-bit integer that is equal to the length L in bits of the message. These three padding operations generate a padded message of length L + 1 + k + 64, which by construction is a multiple of 512 bits.
For the hash processor, the “1” is added to the last word written to the HASH_DIN register at the bit position defined by the NBLW bitfield, and the remaining upper bits are cleared (“0”s).
Example from FIPS PUB180-2
Let us assume that the original message is the ASCII binary-coded form of “abc”, of length L = 24:
byte 0 byte 1 byte 2 byte 3
01100001 01100010 01100011 UUUUUUUU
<-- 1st word written to HASH_DIN -->
NBLW has to be loaded with the value 24: a “1” is appended at bit location 24 in the bit string (starting counting from left to right in the above bit string), which corresponds to bit 31 in the HASH_DIN register (little-endian convention):
01100001 01100010 01100011 1UUUUUUU
Since L = 24, the number of bits in the above bit string is 25, and 423 “0” bits are appended, making now 448 bits.
This gives in hexadecimal (byte words in big-endian format):
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000
The message length value, L, in two-word format (that is 00000000 00000018) is appended. Hence the final padded message in hexadecimal (byte words in big-endian format):
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000018
If the hash processor is programmed to swap byte within HASH_DIN input register (DATATYPE=10 in HASH_CR), the above message has to be entered by following below the sequence:
The hash computing is complete with the message digest available in the HASH_HRx registers (x = 0...4) for the SHA-1 algorithm. For this FIPS example, the expected value is as follows:
HASH_H0 = 0xA9993E36
HASH_H1 = 0x4706816A
HASH_H2 = 0xBA3E2571
HASH_H3 = 0x7850C26C
HASH_H4 = 0x9CD0D89D
Overview
As specified by Internet Engineering Task Force RFC2104, HMAC: keyed-hashing for
message authentication, the HMAC algorithm is used for message authentication by irreversibly binding the message being processed to a key chosen by the user. The algorithm consists of two nested hash operations:
HMAC(message) = Hash((key | pad) XOR [0x5C]n
| Hash((key | pad) XOR [0x36]n | message))
where:
HMAC processing
Four different steps are required to compute the HMAC:
The key to be used for the inner hash function must be provided to the hash processor:
The key loading operation follows the same mechanism as the message bit string loading, i.e. write key data into HASH_DIN and complete the transfer by writing to HASH_STR register.
Note: Endianness details can be found in Section 24.3.4: Message data feeding.
Note: The computation latency of the HMAC primitive depends on the lengths of the keys and
message, as described in Section 24.5: HASH processing time.
HMAC example
Below is an example of HMAC SHA-1 algorithm (ALGO=”00” and MODE=”1” in HASH_CR) as specified by NIST.
Let us assume that the original message is the ASCII binary-coded form of “Sample message for keylen=blocklen”, of length L = 34 bytes. If the HASH is programmed in no swapping mode (DATATYPE=00 in HASH_CR), the following data must be loaded sequentially into HASH_DIN register:
00010203 04050607 08090A0B 0C0D0E0F 10111213 14151617
18191A1B 1C1D1E1F 20212223 24252627 28292A2B 2C2D2E2F
30313233 34353637 38393A3B 3C3D3E3F
53616D70 6C65206D 65737361 67652066 6F72206B 65796C65
6E3D626C 6F636B6C 656EUUUU
Final outer hash computing is then performed by the HASH. The HMAC SHA-1 digest result is available in the HASH_HRx registers (x = 0...4), as shown below:
HASH_H0 = 0x5FD596EE
HASH_H1 = 0x78D5553C
HASH_H2 = 0x8FF4E72D
HASH_H3 = 0x266DFD19
HASH_H4 = 0x2366DA29
Overview
It is possible to interrupt a hash/HMAC operation to perform another processing with a higher priority. The interrupted process completes later when the higher-priority task has been processed, as shown in Figure 193.
| (omitted) |
To do so, the context of the interrupted task must be saved from the HASH registers to memory, and then be restored from memory to the HASH registers.
The procedures where the data flow is controlled by software or by DMA are described below.
Data loaded by software
When the DMA is not used to load the message into the hash processor, the context can be saved only when no block processing is ongoing. This means that the user application must wait until DINIS = 1 (last block processed and input FIFO empty) or NBW ≠ 0 (FIFO not full and no processing ongoing). The detailed procedure is described below.
Current context saving
Before interrupting the current message digest calculation, the application must store the contents of the following registers into memory:
Current context restoring
To resume processing the interrupted message, the application must respect the following steps:
Data loaded by DMA
When the DMA is used to load the message into the hash processor, it is not possible to predict if a DMA transfer is ongoing. The user application must thus stop DMA transfers, then wait until the hash processor is ready before interrupting the current message digest calculation. The detailed procedure is described below.
Current context saving
Before interrupting the current message digest calculation using DMA, the application must respect the following steps:
Current context restoring
To resume processing the interrupted message using DMA, the application must respect the following steps:
Note: If the context swapping does not involve HMAC operations, the HASH_CSR38 to
HASH_CSR53 registers do not need to be saved and restored.
If the context swapping occurs between two blocks (the last block was completely
processed and the next block has not yet been pushed into the IN FIFO, NBW = 000 in the
HASH_CR register), the HASH_CSR22 to HASH_CSR37 registers do not need to be saved
and restored.
The hash processor provides an interface to connect to the DMA controller. This DMA can be used to write data to the HASH by setting the DMAE bit in the HASH_CR register. When this bit is set, the HASH asserts the burst request signal to the DMA controller when there is enough free words in the FIFO to support a burst of four words.
Once four 32-bit words have been received, the HASH automatically restarts this process, checks the FIFO size, and asserts a new request if the FIFO status allow a burst reception. For more information refer to Section 24.3.5: Message digest computing.
Before starting the DMA transfer, the software must program the number of valid bits in the last word that will be copied into HASH_DIN register. This is done by writing in HASH_STR register the following value:
NBLW = Len(Message)% 32
where “x%32” gives the remainder of x divided by 32.
DMAS bit in HASH_SR register provides information on the DMA interface activity. This bit is set with DMAE and cleared when DMAE is cleared to 0 and no DMA transfer is ongoing.
Note: No interrupt is associated to DMAS bit.
No error flags are generated by the HASH hardware.
Two individual maskable interrupt sources are generated by the hash processor to signal following events:
Both interrupt sources are connected to the same global interrupt request signal, as shown on Figure 194.
| (omitted) |
The above interrupt sources can be enabled or disabled individually by changing the mask bits in the HASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt.
The status of the individual interrupt events can be read from the HASH_SR register. Table 167 gives a summary of the available features.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Digest computation completed flag | DCIS | DCIE |
| Data input buffer ready to get a new block flag | DINIS | DINIE |
Table 168 summarizes the time required to process a 512-bit intermediate block for each mode of operation.
| Mode of operation | FIFO load(1) |
Computation phase | Total |
|---|---|---|---|
| MD5 | 16 | 50 |
66
|
| SHA-1 | 16 | 66 |
82
|
| SHA-224 |
16 | 50 |
66
|
| SHA-256 |
The time required to process the last block of a message (or of a key in HMAC) can be longer. This time depends on the length of the last block and the size of the key (in HMAC mode).
Compared to the processing of an intermediate block, it can be increased by the factor below:
The HASH core is associated with several control and status registers and five message digest registers. All these registers are accessible through 32-bit word accesses only, else an AHB2 error is generated.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALGO[1] | Res. | LKEY |
Res. | Res. | MDMAT | DINNE | NBW[3:0] | ALGO[0] | MODE | DATATYPE[1:0] | DMAE | INIT | Res. | Res. |
||||
| rw | rw |
rw | r | r | r | r | r | rw | rw | rw | rw | rw | w |
||||||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bit 18 | ALGO[1]: refer to bit 7 description |
| Bit 17 | Reserved, must be kept at reset value. |
| Bit 16 | LKEY: Long key selection |
|
This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC mode. This selection is only taken into account when the INIT bit is set and |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | Reserved, must be kept at reset value. |
| Bit 13 | MDMAT: Multiple DMA Transfers |
|
This bit is set when hashing large files when multiple DMA transfers are needed. 0: DCAL is automatically set at the end of a DMA transfer. |
|
| Bit 12 | DINNE: DIN not empty |
|
This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. |
|
| Bits 11:8 | NBW[3:0]: Number of words already pushed |
|
This bitfield reflects the number of words in the message that have already been pushed into the IN FIFO. NBW increments (+1) when a write access is performed to the HASH_DIN register while DINNE = 1. If the DMA is used |
Bits 18, 7 ALGO[1:0]: Algorithm selection
These bits selects the SHA-1, SHA-224, SHA-256 or the MD5 algorithm:
00: SHA-1 algorithm selected
01: MD5 algorithm selected
10: SHA-224 algorithm selected
11: SHA-256 algorithm selected
Note: This selection is only taken into account when the INIT bit is set. Changing
this bit during a computation has no effect.
| Bit 6 | MODE: Mode selection |
|
This bit selects the HASH or HMAC mode for the selected algorithm: This selection is only taken into account when the INIT bit is set. Changing |
|
| Bits 5:4 | DATATYPE[1:0]: Data type selection |
|
These bits define the format of the data entered into the HASH_DIN register: |
|
| Bit 3 | DMAE: DMA enable |
|
0: DMA transfers disabled |
|
| Bit 2 | INIT: Initialize message digest calculation |
|
Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x04
Reset value: 0x0000 0000
HASH_DIN is the data input register. It is 32-bit wide. This register is used to enter the message by blocks of 512 bits. When the HASH_DIN register is programmed, the value presented on the AHB databus is ‘pushed’ into the hash core and the register takes the new value presented on the AHB databus. To get a correct message format, the DATATYPE bits must have been previously configured in the HASH_CR register.
When a block of 16 words has been written to the HASH_DIN register, an intermediate digest calculation is launched:
When the last block has been written to the HASH_DIN register, the final digest calculation (including padding) is launched:
When a digest calculation (intermediate or final) is ongoing and a new write access to the HASH_DIN register is performed, wait-states are inserted on the AHB2 bus until the hash calculation completes.
When the HASH_DIN register is read, the last word written to this location is accessed (zero after reset).
.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATAIN[31:16] |
DATAIN[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATAIN[31:0]: Data input |
|
Reading this register returns the current register content. |
Address offset: 0x08
Reset value: 0x0000 0000
The HASH_STR register has two functions:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | DCAL | Res. | Res. | Res. | NBLW[4:0] |
||||
| w | rw | rw | rw | rw | rw |
||||||||||||||||||||||||||
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | DCAL: Digest calculation |
|
Writing this bit to 1 starts the message padding, using the previously written value of NBLW, and starts the calculation of the final message digest with all data words written to the IN FIFO since the INIT bit was last written to 1. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:0 | NBLW[4:0]: Number of valid bits in the last word |
|
When the last word of the message bit string is written in HASH_DIN register, the hash processor takes only the valid bits specified as below, after internal data swapping: |
These registers contain the message digest result named as follows:
HASH_HR0, HASH_HR1, HASH_HR2, HASH_HR3 and HASH_HR4 registers return the SHA-1 digest result
In this case, the HASH_HR5 to HASH_HR7 register are not used, and they are read as zero.
HASH_HR0, HASH_HR1, HASH_HR2 and HASH_HR3 registers return A, B, C and D (respectively), as defined by MD5.
In this case, the HASH_HR4 to HASH_HR7 registers are not used, and they are read as zero.
HASH_HR0 to HASH_HR6 registers return the SHA-224 digest result.
In this case, the HASH_HR7 register is not used, and it is read as zero.
In all cases, the digest most significant bit is stored in HASH_HR0[31] and it is not used.
If a read access to one of these registers is performed while the hash core is calculating an intermediate digest or a final message digest (that is when the DCAL bit has been written to 1), then the read operation is stalled until the hash calculation completes.
Note: HASH_HR0, HASH_HR1, HASH_HR2, HASH_HR3 and HASH_HR4 mapping are
duplicated in two memory regions.
HASH_HR0
Address offset: 0x0C and 0x310
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H0 |
H0 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR1
Address offset: 0x10 and 0x314
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H1 |
H1 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR2
Address offset: 0x14 and 0x318
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H2 |
H2 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR3
Address offset: 0x18 and 0x31C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H3 |
H3 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR4
Address offset: 0x1C and 0x320
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H4 |
H4 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR5
Address offset: 0x324
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H5 |
H5 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR6
Address offset: 0x328
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H6 |
H6 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
HASH_HR7
Address offset: 0x32C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| H7 |
H7 |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers are forced to their reset values.
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DCIE | DINIE |
| rw | rw |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | DCIE: Digest calculation completion interrupt enable |
|
0: Digest calculation completion interrupt disabled |
|
| Bit 0 | DINIE: Data input interrupt enable |
|
0: Data input interrupt disabled |
Address offset: 0x24
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | DMAS | DCIS | DINIS |
| r | r | rc_w0 | rc_w0 |
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | BUSY: Busy bit |
|
0: No block is currently being processed |
|
| Bit 2 | DMAS: DMA Status |
|
This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE=0 and no DMA transfer is ongoing. No interrupt is associated with this bit. |
|
| Bit 1 | DCIS: Digest calculation completion interrupt status |
|
This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. |
|
| Bit 0 | DINIS: Data input interrupt status |
|
This bit is set by hardware when the input buffer is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. |
These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task.
When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers.
HASH_CSR0
Address offset: 0x0F8
Reset value: 0x0000 0002
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CS0 |
CS0 |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
HASH_CSRx (x=1 to 53)
Address offset: 0x0F8 + x * 0x4
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CSx |
CSx |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Table 169 gives the summary HASH register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | HASH_CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALGO[1] | Res. | LKEY | Res. | Res. | .MDMAT | DINNE | NBW |
ALGO[0] | MODE | DATATYPE | DMAE | INIT | Res. | Res. | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x04 | HASH_DIN | DATAIN |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x08 | HASH_STR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DCAL | Res. | Res. | Res. | NBLW |
||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x0C | HASH_HR0 | H0 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 | HASH_HR1 | H1 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x14 | HASH_HR2 | H2 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x18 | HASH_HR3 | H3 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1C | HASH_HR4 | H4 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x20 | HASH_IMR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DCIE | DINIE |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x24 | HASH_SR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BUSY | DMAS | DCIS | DINIS |
| Reset value | 0 | 0 | 0 | 1 |
|||||||||||||||||||||||||||||
| 0xF8 | HASH_CSR0 | CSR0 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
| 0xFC | HASH_CSR1 | CSR1 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| ... ... |
|||||||||||||||||||||||||||||||||
| 0x1CC | HASH_CSR53 | CSR53 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
Reserved
|
|||||||||||||||||||||||||||||||||
| 0x310 | HASH_HR0 | H0 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x314 | HASH_HR1 | H1 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x318 | HASH_HR2 | H2 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x31C | HASH_HR3 | H3 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x320 | HASH_HR4 | H4 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x324 | HASH_HR5 | H5 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x328 | HASH_HR6 | H6 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x32C | HASH_HR7 | H7 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The advanced-control timers (TIM1/TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1/TIM8) and general-purpose (TIMy) timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 25.3.25: Timer synchronization.
TIM1/TIM8 timer features include:
| (omitted) |
The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 196 and Figure 197 give some examples of the counter behavior when the prescaler ratio is changed on the fly:
| (omitted) |
| (omitted) |
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1. Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1. Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11").
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Section 25.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 215). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.
In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow. If the RCR was written after launching the counter, the UEV occurs on the underflow.
For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event depending on when the RCR was written.
| (omitted) |
The timer features an external trigger input ETR. It can be used as:
Figure 216 below describes the ETR input conditioning. The input polarity is defined with the ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.
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The counter clock can be provided by the following clock sources:
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 217 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
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External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input.
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For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
Note: The capture prescaler is not used for triggering, so the user does not need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 220 gives an overview of the external trigger input block.
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For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.
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Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control).
Figure 222 to Figure 225 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
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The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.
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The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:
When an input capture occurs:
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
This mode is a particular case of input capture mode. The procedure is the same except:
For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):
| (omitted) |
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, user just needs to write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.
This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the microcontroller (for instance, for compound waveform generation or for ADC triggering).
When a match is found between the capture/compare register and the counter, the output compare function:
The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode).
Procedure
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 228.
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Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 866.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 229 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.
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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Downcounting mode on page 870
In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 873.
Figure 230 shows some center-aligned PWM waveforms in an example where:
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Hints on using center-aligned mode
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx register. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle:
Asymmetric PWM mode can be selected independently on two channel (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
When a given channel is used as asymmetric PWM channel, its complementary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 1.
Figure 231 represents an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Together with the deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be controlled.
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Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs:
Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 232 represents an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration:
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Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal. The 3-bits GC5C[3:1] in the TIMx_CCR5 allow selection on which reference signal the OC5REF is combined. The resulting signals, OCxREFC, are made of an AND logical combination of two reference PWMs:
Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting at least one of the 3-bits GC5C[3:1].
| (omitted) |
The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Refer to Section 25.3.26: ADC synchronization for more details.
The advanced-control timers (TIM1/TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 173: Output control bits for complementary OCx and OCxN channels with break
feature on page 941 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:
If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples)
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The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 25.4.18: TIM1/TIM8 break and dead-time register (TIMx_BDTR) for delay calculation.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.
This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 and TIM8 timers. The two break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. A number of internal MCU events can also be selected to trigger an output shut-down.
The break features two channels. A break channel which gathers both system-level fault (clock failure, PVD, Core Lockup,...) and application fault (from input pinsand DFSDM1 break output), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. A break2 channel which only includes application faults and is able to force the outputs to an inactive state.
The output enable signal and output levels during break are depending on several control bits:
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break functions by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break input polarities can be selected by configuring the BKP and BKP2 bits in the same register. BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal.
The break (BRK) event can be generated by two sources of events ORed together:
The break2 (BRK2) can be generated by:
Break events can also be generated by software using BG and B2G bits in the TIMx_EGR register. The software break generation using BG and BG2 is active whatever the BKE and BKE2 enable bits values.
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Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or
the CSS) must be used to guarantee that break events are handled.
When one of the breaks occurs (selected level on one of the break inputs):
regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components.
Note: The break inputs are active on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF
cannot be cleared.
In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The application can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 25.4.18: TIM1/TIM8 break and dead-time register (TIMx_BDTR). The LOCK bits can be written only once after an MCU reset.
Figure 238 shows an example of behavior of the outputs in response to a break.
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The two break inputs have different behaviors on timer outputs:
The BRK has a higher priority than BRK2 input, as described in Table 170.
Note: BRK2 must only be used with OSSR = OSSI = 1.
| BRK | BRK2 | Timer outputs state |
Typical use case |
|
|---|---|---|---|---|
| OCxN output (low side switches) |
OCx output (high side switches) |
|||
| Active | X |
|
ON after deadtime insertion | OFF |
| Inactive | Active | Inactive | OFF | OFF |
Figure 239 gives an example of OCx and OCxN output behavior in case of active signals on BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP = CCxNP = 0 in TIMx_CCER register).
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The OCxREF signal for a given channel can be driven low by applying a high level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains low until the next update event, UEV, occurs.
When ETRF is chosen, ETR must be configured as follows:
Figure 241 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode.
| (omitted) |
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register).
The Figure 242 describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations.
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One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:
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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in Section 25.3.19:
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for Retrigerrable OPM mode 1 or 2.
If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode, CCRx must be above or equal to ARR.
Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit are not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.
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To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an quadrature encoder. Refer to Table 171. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together.
Note: The prescaler must be set to zero when encoder mode is enabled
In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
| Active edge |
Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) |
TI1FP1 signal | TI2FP2 signal |
||
|---|---|---|---|---|---|
| Rising | Falling | Rising | Falling |
||
| Counting on TI1 only |
High | Down | Up | No Count | No Count |
| Low | Up | Down | No Count | No Count |
|
| Counting on TI2 only |
High | No Count | No Count | Up | Down |
| Low | No Count | No Count | Down | Up |
|
| Counting on TI1 and TI2 |
High | Down | Up | Up | Down |
| Low | Up | Down | Down | Up |
|
A quadrature encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.
The Figure 245 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:
| (omitted) |
Figure 246 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’).
| (omitted) |
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request.
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).
There is no latency between the UIF and UIFCPY flag assertions.
In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only accessible in write mode).
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).
There is no latency between the UIF and UIFCPY flags assertion.
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input capture. It is convenient to measure the interval between edges on two input signals, as per Figure 247 below.
| (omitted) |
This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4) referred to as “interfacing timer” in Figure 248. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (See Figure 222: Capture/compare channel (example: channel 1
input stage) on page 884). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-control timer (TIM1 or TIM8) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF).
The Figure 248 describes this example.
| (omitted) |
The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
Slave mode: Combined reset + trigger mode
In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter.
This mode is used for one-pulse mode.
Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
| (omitted) |
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as:
The triggers are issued on the TRGO2 internal line which is redirected to the ADC. There is a total of 16 possible events, which can be selected using the MMS2[3:0] bits in the TIMx_CR2 register.
An example of an application for 3-phase motor drives is given in Figure 233 on page 896.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
Note: The clock of the ADC must be enabled prior to receive events from the master timer, and
must not be changed on-the-fly while triggers are received from the timer.
The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.
The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register:
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.
When the microcontroller enters debug mode (Cortex®-M7 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0), typically to force a Hi-Z.
For more details, refer to Section 40.16.2: Debug support for timers, watchdog, bxCAN and
I2C.
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force them to Hi-Z.
Refer to for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | UIFRE MAP |
Res. | CKD[1:0] | ARPE | CMS[1:0] | DIR | OPM | URS | UDIS | CEN |
||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | UIFREMAP: UIF status bit remapping |
|
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bits 9:8 | CKD[1:0]: Clock division |
|
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx), |
|
| Bit 7 | ARPE: Auto-reload preload enable |
|
0: TIMx_ARR register is not buffered |
|
| Bits 6:5 | CMS[1:0]: Center-aligned mode selection |
|
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). It is not allowed to switch from edge-aligned mode to center-aligned mode as long as |
|
| Bit 4 | DIR: Direction |
|
0: Counter used as upcounter This bit is read only when the timer is configured in Center-aligned mode or Encoder |
|
| Bit 3 | OPM: One pulse mode |
|
0: Counter is not stopped at update event |
|
| Bit 2 | URS: Update request source |
|
This bit is set and cleared by software to select the UEV event sources.
enabled. |
|
| Bit 1 | UDIS: Update disable |
|
This bit is set and cleared by software to enable/disable UEV event generation.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
|
| Bit 0 | CEN: Counter enable |
|
0: Counter disabled External clock, gated mode and encoder mode can work only if the CEN bit has been |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS2[3:0] | Res. | OIS6 | Res. | OIS5 |
Res. | OIS4 | OIS3N | OIS3 | OIS2N | OIS2 | OIS1N | OIS1 | TI1S | MMS[2:0] | CCDS | CCUS | Res. | CCPC |
|||||
| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:20 | MMS2[3:0]: Master mode selection 2 |
|
These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: The clock of the slave timer or ADC must be enabled prior to receive events from the |
|
| Bit 19 | Reserved, must be kept at reset value. |
| Bit 18 | OIS6: Output Idle state 6 (OC6 output) |
|
Refer to OIS1 bit |
|
| Bit 17 | Reserved, must be kept at reset value. |
| Bit 16 | OIS5: Output Idle state 5 (OC5 output) |
|
Refer to OIS1 bit |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | OIS4: Output Idle state 4 (OC4 output) |
|
Refer to OIS1 bit |
|
| Bit 13 | OIS3N: Output Idle state 3 (OC3N output) |
|
Refer to OIS1N bit |
|
| Bit 12 | OIS3: Output Idle state 3 (OC3 output) |
|
Refer to OIS1 bit |
|
| Bit 11 | OIS2N: Output Idle state 2 (OC2N output) |
|
Refer to OIS1N bit |
|
| Bit 10 | OIS2: Output Idle state 2 (OC2 output) |
|
Refer to OIS1 bit |
|
| Bit 9 | OIS1N: Output Idle state 1 (OC1N output) |
|
0: OC1N=0 after a dead-time when MOE=0 This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed |
|
| Bit 8 | OIS1: Output Idle state 1 (OC1 output) |
|
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed |
|
| Bit 7 | TI1S: TI1 selection |
|
0: The TIMx_CH1 pin is connected to TI1 input |
|
| Bits 6:4 | MMS[2:0]: Master mode selection |
|
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. The clock of the slave timer or ADC must be enabled prior to receive events from the |
|
| Bit 3 | CCDS: Capture/compare DMA selection |
|
0: CCx DMA request sent when CCx event occurs |
|
| Bit 2 | CCUS: Capture/compare control update selection |
|
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
This bit acts only on channels that have a complementary output.
|
|
| Bit 1 | Reserved, must be kept at reset value. |
| Bit 0 | CCPC: Capture/compare preloaded control |
|
0: CCxE, CCxNE and OCxM bits are not preloaded
This bit acts only on channels that have a complementary output.
|
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] |
ETP | ECE | ETPS[1:0] | ETF[3:0] | MSM | TS[2:0] | Res. | SMS[2:0] |
||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | SMS[3]: Slave mode selection - bit 3 |
|
Refer to SMS description - bits 2:0. |
|
| Bit 15 | ETP: External trigger polarity |
|
This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. |
|
| Bit 14 | ECE: External clock enable |
|
This bit enables External clock mode 2. 0: External clock mode 2 disabled
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with 2: It is possible to simultaneously use external clock mode 2 with the following slave |
|
| Bits 13:12 | ETPS[1:0]: External trigger prescaler |
|
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. |
|
| Bits 11:8 | ETF[3:0]: External trigger filter |
|
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bit 7 | MSM: Master/slave mode |
|
0: No action |
|
| Bits 6:4 | TS[2:0]: Trigger selection |
|
This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) These bits must be changed only when they are not used (e.g. when SMS=000) to The other bit is at position 16 in the same register |
|
| Bit 3 | Reserved, must be kept at reset value. |
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
Codes above 1000: Reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.
| Slave TIM | ITR0 (TS = 000) | ITR1 (TS = 001) | ITR2 (TS = 010) | ITR3 (TS = 011) |
|---|---|---|---|---|
| TIM1 | TIM5 | TIM2 | TIM3 | TIM4 |
| TIM8 | TIM1 | TIM2 | TIM4 | TIM5 |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | TDE | COMDE | CC4DE | CC3DE | CC2DE | CC1DE | UDE | BIE | TIE | COMIE | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | TDE: Trigger DMA request enable |
|
0: Trigger DMA request disabled |
|
| Bit 13 | COMDE: COM DMA request enable |
|
0: COM DMA request disabled |
|
| Bit 12 | CC4DE: Capture/Compare 4 DMA request enable |
|
0: CC4 DMA request disabled |
|
| Bit 11 | CC3DE: Capture/Compare 3 DMA request enable |
|
0: CC3 DMA request disabled |
|
| Bit 10 | CC2DE: Capture/Compare 2 DMA request enable |
|
0: CC2 DMA request disabled |
|
| Bit 9 | CC1DE: Capture/Compare 1 DMA request enable |
|
0: CC1 DMA request disabled |
|
| Bit 8 | UDE: Update DMA request enable |
|
0: Update DMA request disabled |
|
| Bit 7 | BIE: Break interrupt enable |
|
0: Break interrupt disabled |
|
| Bit 6 | TIE: Trigger interrupt enable |
|
0: Trigger interrupt disabled |
|
| Bit 5 | COMIE: COM interrupt enable |
|
0: COM interrupt disabled |
|
| Bit 4 | CC4IE: Capture/Compare 4 interrupt enable |
|
0: CC4 interrupt disabled |
|
| Bit 3 | CC3IE: Capture/Compare 3 interrupt enable |
|
0: CC3 interrupt disabled |
|
| Bit 2 | CC2IE: Capture/Compare 2 interrupt enable |
|
0: CC2 interrupt disabled |
|
| Bit 1 | CC1IE: Capture/Compare 1 interrupt enable |
|
0: CC1 interrupt disabled |
|
| Bit 0 | UIE: Update interrupt enable |
|
0: Update interrupt disabled |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6IF | CC5IF |
Res. | Res. | CC4OF | CC3OF | CC2OF | CC1OF | B2IF | BIF | TIF | COMIF | CC4IF | CC3IF | CC2IF | CC1IF | UIF |
|
| rc_w0 | rc_w0 |
rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | CC6IF: Compare 6 interrupt flag |
|
Refer to CC1IF description (Note: Channel 6 can only be configured as output) |
|
| Bit 16 | CC5IF: Compare 5 interrupt flag |
|
Refer to CC1IF description (Note: Channel 5 can only be configured as output) |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 12 | CC4OF: Capture/Compare 4 overcapture flag |
|
Refer to CC1OF description |
|
| Bit 11 | CC3OF: Capture/Compare 3 overcapture flag |
|
Refer to CC1OF description |
|
| Bit 10 | CC2OF: Capture/Compare 2 overcapture flag |
|
Refer to CC1OF description |
|
| Bit 9 | CC1OF: Capture/Compare 1 overcapture flag |
|
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. |
|
| Bit 8 | B2IF: Break 2 interrupt flag |
|
This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. |
|
| Bit 7 | BIF: Break interrupt flag |
|
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. |
|
| Bit 6 | TIF: Trigger interrupt flag |
|
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. |
|
| Bit 5 | COMIF: COM interrupt flag |
|
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. |
|
| Bit 4 | CC4IF: Capture/Compare 4 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 3 | CC3IF: Capture/Compare 3 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 2 | CC2IF: Capture/Compare 2 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 1 | CC1IF: Capture/Compare 1 interrupt flag |
|
If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. |
|
| Bit 0 | UIF: Update interrupt flag |
|
This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
|
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | B2G | BG | TG | COMG | CC4G | CC3G | CC2G | CC1G | UG |
| w | w | w | w | w | w | w | w | w |
| Bits 15:9 | Reserved, must be kept at reset value. |
| Bit 8 | B2G: Break 2 generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 7 | BG: Break generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 6 | TG: Trigger generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 5 | COMG: Capture/Compare control update generation |
|
This bit can be set by software, it is automatically cleared by hardware
This bit acts only on channels having a complementary output.
|
|
| Bit 4 | CC4G: Capture/Compare 4 generation |
|
Refer to CC1G description |
|
| Bit 3 | CC3G: Capture/Compare 3 generation |
|
Refer to CC1G description |
|
| Bit 2 | CC2G: Capture/Compare 2 generation |
|
Refer to CC1G description |
|
| Bit 1 | CC1G: Capture/Compare 1 generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action |
|
| Bit 0 | UG: Update generation |
|
This bit can be set by software, it is automatically cleared by hardware. |
Address offset: 0x18
Reset value: 0x0000 0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] |
OC2 CE |
OC2M[2:0] | OC2 PE |
OC2 FE |
CC2S[1:0] |
OC1 CE |
OC1M[2:0] | OC1 PE |
OC1 FE |
CC1S[1:0] |
||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
IC2F[3:0] | IC2PSC[1:0] | IC1F[3:0] | IC1PSC[1:0] |
||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | OC2M[3]: Output Compare 2 mode - bit 3 |
|
Refer to OC2M description on bits 14:12. |
|
| Bits 23:17 | Reserved, must be kept at reset value. |
| Bit 16 | OC1M[3]: Output Compare 1 mode - bit 3 |
|
Refer to OC1M description on bits 6:4 |
|
| Bit 15 | OC2CE: Output Compare 2 clear enable |
| Bits 14:12 | OC2M[2:0]: Output Compare 2 mode |
| Bit 11 | OC2PE: Output Compare 2 preload enable |
| Bit 10 | OC2FE: Output Compare 2 fast enable |
| Bits 9:8 | CC2S[1:0]: Capture/Compare 2 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output
CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
|
|
| Bit 7 | OC1CE: Output Compare 1 clear enable |
|
0: OC1Ref is not affected by the ETRF input |
|
| Bits 6:4 | OC1M: Output Compare 1 mode |
|
These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. These bits can not be modified as long as LOCK level 3 has been programmed (LOCK In PWM mode, the OCREF level changes only when the result of the comparison On channels having a complementary output, this bit field is preloaded. If the CCPC bit |
|
| Bit 3 | OC1PE: Output Compare 1 preload enable |
|
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
1: These bits can not be modified as long as LOCK level 3 has been programmed 2: The PWM mode can be used without validating the preload register only in one |
|
| Bit 2 | OC1FE: Output Compare 1 fast enable |
|
This bit is used to accelerate the effect of an event on the trigger in input on the CC output. |
|
| Bits 1:0 | CC1S: Capture/Compare 1 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output
CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
|
Input capture mode
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:12 | IC2F: Input capture 2 filter |
| Bits 11:10 | IC2PSC[1:0]: Input capture 2 prescaler |
| Bits 9:8 | CC2S: Capture/Compare 2 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). |
|
| Bits 7:4 | IC1F[3:0]: Input capture 1 filter |
|
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bits 3:2 | IC1PSC: Input capture 1 prescaler |
|
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input |
|
| Bits 1:0 | CC1S: Capture/Compare 1 Selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output
CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
|
Address offset: 0x1C
Reset value: 0x0000 0000
Refer to the above CCMR1 register description.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC3M[3] |
OC4 CE |
OC4M[2:0] | OC4 PE |
OC4 FE |
CC4S[1:0] |
OC3 CE. |
OC3M[2:0] | OC3 PE |
OC3 FE |
CC3S[1:0] |
||||||
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
IC4F[3:0] | IC4PSC[1:0] | IC3F[3:0] | IC3PSC[1:0] |
||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | OC4M[3]: Output Compare 4 mode - bit 3 |
| Bits 23:17 | Reserved, must be kept at reset value. |
| Bit 16 | OC3M[3]: Output Compare 3 mode - bit 3 |
| Bit 15 | OC4CE: Output compare 4 clear enable |
| Bits 14:12 | OC4M: Output compare 4 mode |
| Bit 11 | OC4PE: Output compare 4 preload enable |
| Bit 10 | OC4FE: Output compare 4 fast enable |
| Bits 9:8 | CC4S: Capture/Compare 4 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output
CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
|
|
| Bit 7 | OC3CE: Output compare 3 clear enable |
| Bits 6:4 | OC3M: Output compare 3 mode |
| Bit 3 | OC3PE: Output compare 3 preload enable |
| Bit 2 | OC3FE: Output compare 3 fast enable |
| Bits 1:0 | CC3S: Capture/Compare 3 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output
CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
|
Input capture mode
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:12 | IC4F: Input capture 4 filter |
| Bits 11:10 | IC4PSC: Input capture 4 prescaler |
| Bits 9:8 | CC4S: Capture/Compare 4 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). |
|
| Bits 7:4 | IC3F: Input capture 3 filter |
| Bits 3:2 | IC3PSC: Input capture 3 prescaler |
| Bits 1:0 | CC3S: Capture/compare 3 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output
CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
|
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6P | CC6E | Res. | Res. | CC5P | CC5E |
CC4NP | Res. | CC4P | CC4E | CC3NP | CC3NE | CC3P | CC3E | CC2NP | CC2NE | CC2P | CC2E | CC1NP | CC1NE | CC1P | CC1E |
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | CC6P: Capture/Compare 6 output polarity |
|
Refer to CC1P description |
|
| Bit 20 | CC6E: Capture/Compare 6 output enable |
|
Refer to CC1E description |
|
| Bits 19:18 | Reserved, must be kept at reset value. |
| Bit 17 | CC5P: Capture/Compare 5 output polarity |
|
Refer to CC1P description |
|
| Bit 16 | CC5E: Capture/Compare 5 output enable |
|
Refer to CC1E description |
|
| Bit 15 | CC4NP: Capture/Compare 4 complementary output polarity |
|
Refer to CC1NP description |
|
| Bit 14 | Reserved, must be kept at reset value. |
| Bit 13 | CC4P: Capture/Compare 4 output polarity |
|
Refer to CC1P description |
|
| Bit 12 | CC4E: Capture/Compare 4 output enable |
|
Refer to CC1E description |
|
| Bit 11 | CC3NP: Capture/Compare 3 complementary output polarity |
|
Refer to CC1NP description |
|
| Bit 10 | CC3NE: Capture/Compare 3 complementary output enable |
|
Refer to CC1NE description |
|
| Bit 9 | CC3P: Capture/Compare 3 output polarity |
|
Refer to CC1P description |
|
| Bit 8 | CC3E: Capture/Compare 3 output enable |
|
Refer to CC1E description |
|
| Bit 7 | CC2NP: Capture/Compare 2 complementary output polarity |
|
Refer to CC1NP description |
|
| Bit 6 | CC2NE: Capture/Compare 2 complementary output enable |
|
Refer to CC1NE description |
|
| Bit 5 | CC2P: Capture/Compare 2 output polarity |
|
Refer to CC1P description |
|
| Bit 4 | CC2E: Capture/Compare 2 output enable |
|
Refer to CC1E description |
|
| Bit 3 | CC1NP: Capture/Compare 1 complementary output polarity |
|
CC1 channel configured as output: 0: OC1N active high. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the |
|
| Bit 2 | CC1NE: Capture/Compare 1 complementary output enable |
|
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the |
|
| Bit 1 | CC1P: Capture/Compare 1 output polarity |
|
CC1 channel configured as output: 0: OC1 active high This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the |
|
| Bit 0 | CC1E: Capture/Compare 1 output enable |
|
CC1 channel configured as output: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the |
| Control bits | Output states(1) |
|||||
|---|---|---|---|---|---|---|
| MOE bit | OSSI bit | OSSR bit | CCxE bit | CCxNE bit | OCx output state | OCxN output state |
| 1 | X |
X | 0 | 0 | Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 |
|
| 0 | 0 | 1 |
Output disabled (not driven by the timer: Hi-Z) OCx=0 |
OCxREF + Polarity OCxN = OCxREF xor CCxNP |
||
| 0 | 1 | 0 | OCxREF + Polarity OCx=OCxREF xor CCxP |
Output Disabled (not driven by the timer: Hi-Z) OCxN=0 |
||
| X | 1 | 1 | OCREF + Polarity + dead- time |
Complementary to OCREF (not OCREF) + Polarity + dead-time |
||
| 1 | 0 | 1 |
Off-State (output enabled with inactive state) OCx=CCxP |
OCxREF + Polarity OCxN = OCxREF x or CCxNP |
||
| 1 | 1 | 0 | OCxREF + Polarity OCx=OCxREF xor CCxP |
Off-State (output enabled with inactive state) OCxN=CCxNP |
||
| 0 |
0 |
X |
X | X | Output disabled (not driven by the timer anymore). The output state is defined by the GPIO controller and can be High, Low or Hi-Z. |
|
| 1 |
0 | 0 |
||||
| 0 | 1 |
Off-State (output enabled with inactive state) Then (this is valid only if BRK is triggered), if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state (may cause a short circuit when driving switches in half-bridge configuration). Note: BRK2 can only be used if OSSI = OSSR = 1. |
||||
| 1 | 0 |
|||||
| 1 | 1 |
|||||
The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UIF CPY |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CNT[15:0] |
|||||||||||||||
| r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bit 31 | UIFCPY: UIF copy |
|
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. |
|
| Bits 30:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CNT[15:0]: Counter value |
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PSC[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | PSC[15:0]: Prescaler value |
|
The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). |
Address offset: 0x2C
Reset value: 0xFFFF
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | ARR[15:0]: Auto-reload value |
|
ARR is the value to be loaded in the actual auto-reload register. |
Address offset: 0x30
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REP[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | REP[15:0]: Repetition counter value |
|
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. |
Address offset: 0x34
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR1[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR1[15:0]: Capture/Compare 1 value |
|
If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. |
Address offset: 0x38
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR2[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR2[15:0]: Capture/Compare 2 value |
|
If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). |
Address offset: 0x3C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR3[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR3[15:0]: Capture/Compare value |
|
If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. |
Address offset: 0x40
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR4[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR4[15:0]: Capture/Compare value |
|
If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). |
Address offset: 0x44
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | BK2P | BK2E | BK2F[3:0] | BKF[3:0] |
MOE | AOE | BKP | BKE | OSSR | OSSI | LOCK[1:0] | DTG[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
Note: As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0]
can be write-locked depending on the LOCK configuration, it can be necessary to configure
all of them during the first write access to the TIMx_BDTR register.
| Bits 31:26 | Reserved, must be kept at reset value. |
| Bit 25 | BK2P: Break 2 polarity |
|
0: Break input BRK2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. |
|
| Bit 24 | BK2E: Break 2 enable |
|
This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 237: Break and Break2 circuitry overview).
The BRKIN2 must only be used with OSSR = OSSI = 1.
This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. |
|
| Bits 23:20 | BK2F[3:0]: Break 2 filter |
|
This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in |
|
| Bits 19:16 | BKF[3:0]: Break filter |
|
This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in |
|
| Bit 15 | MOE: Main output enable |
|
This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled |
|
| Bit 14 | AOE: Automatic output enable |
|
0: MOE can be set only by software This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits |
|
| Bit 13 | BKP: Break polarity |
|
0: Break input BRK is active low This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. |
|
| Bit 12 | BKE: Break enable |
|
This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 237: Break and Break2 circuitry overview). This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. |
|
| Bit 11 | OSSR: Off-state selection for Run mode |
|
This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK |
|
| Bit 10 | OSSI: Off-state selection for Idle mode |
|
This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK |
|
| Bits 9:8 | LOCK[1:0]: Lock configuration |
|
These bits offer a write protection against software errors. The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register |
|
| Bits 7:0 | DTG[7:0]: Dead-time generator setup |
|
This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed |
Address offset: 0x48
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | DBL[4:0] | Res. | Res. | Res. | DBA[4:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:8 | DBL[4:0]: DMA burst length |
|
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below).
(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL
|
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:0 | DBA[4:0]: DMA base address |
|
This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. |
Address offset: 0x4C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMAB[31:16] |
DMAB[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DMAB[31:0]: DMA register for burst accesses |
|
A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). |
Address offset: 0x54
Reset value: 0x0000 0000
Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in output.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC6M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC5M[3] |
OC6 CE |
OC6M[2:0] | OC6 PE |
OC6FE | Res. | Res. | OC5 CE |
OC5M[2:0] | OC5PE | OC5FE | Res. | Res. |
||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 23:17 | Reserved, must be kept at reset value. |
| Bit 15 | OC6CE: Output compare 6 clear enable |
Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode
| Bit 11 | OC6PE: Output compare 6 preload enable |
| Bit 10 | OC6FE: Output compare 6 fast enable |
| Bits 9:8 | Reserved, must be kept at reset value. |
| Bit 7 | OC5CE: Output compare 5 clear enable |
Bits 16, 6, 5, 4 OC5M[3:0]: Output compare 5 mode
| Bit 3 | OC5PE: Output compare 5 preload enable |
| Bit 2 | OC5FE: Output compare 5 fast enable |
| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x58
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GC5C3 | GC5C2 | GC5C1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CCR5[15:0] |
|||||||||||||||
| rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||
| Bit 31 | GC5C3: Group Channel 5 and Channel 3 |
|
Distortion on Channel 3 output:
it is also possible to apply this distortion on combined PWM signals.
|
|
| Bit 30 | GC5C2: Group Channel 5 and Channel 2 |
|
Distortion on Channel 2 output:
it is also possible to apply this distortion on combined PWM signals.
|
|
| Bit 29 | GC5C1: Group Channel 5 and Channel 1 |
|
Distortion on Channel 1 output:
it is also possible to apply this distortion on combined PWM signals.
|
|
| Bits 28:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CCR5[15:0]: Capture/Compare 5 value |
|
CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). |
Address offset: 0x5C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR6[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR6[15:0]: Capture/Compare 6 value |
|
CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). |
Address offset: 0x60
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | BKINP | BKDFBKE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BKINE |
| rw | rw | rw |
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bit 9 | BKINP: BRK BKIN input polarity |
|
This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
|
| Bit 8 | BKDFBKE: BRK dfsdm1_break[0] enable |
|
This bit enables the dfsdm1_break[0] for the timer BRK input. dfsdm1_break[0] output is ‘ORed’ with the other BRK sources. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | BKINE: BRK BKIN input enable |
|
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
Address offset: 0x64
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | BK2 INP |
BK2DF BKE |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | BK2 INE |
| rw | rw | rw |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 9 | BK2INP: BRK2 BKIN2 input polarity |
|
This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BKP2 polarity bit. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
|
| Bit 8 | BK2DFBKE: BRK2 dfsdm1_break enable |
|
0: dfsdm1_break input disabled This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | BK2INE: BRK2 BKIN input enable |
|
This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled This bit can not be modified as long as LOCK level 1 has been programmed (LOCK |
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIM1_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMAP | Res. | CKD [1:0] |
ARPE | CMS [1:0] |
DIR | OPM | URS | UDIS | CEN | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x04 |
TIM1_CR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS2[3:0] |
Res. | OIS6 | Res. | OIS5 | Res. | OIS4 | OIS3N | OIS3 | OIS2N | OIS2 | OIS1N | OIS1 | TI1S | MMS [2:0] |
CCDS | CCUS | Res. | CCPC | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x08 |
TIM1_SMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] | ETP | ECE | ETP S [1:0] |
ETF[3:0] |
MSM | TS[2:0] |
Res. | SMS[2:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0C |
TIM1_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TDE | COMDE | CC4DE | CC3DE | CC2DE | CC1DE | UDE | BIE | TIE | COMIE | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x10 |
TIM1_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6IF | CC5IF | Res. | Res. | CC4OF | CC3OF | CC2OF | CC1OF | B2IF | BIF | TIF | COMIF | CC4IF | CC3IF | CC2IF | CC1IF | UIF | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x14 |
TIM1_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | B2G | BG | TG | COM | CC4G | CC3G | CC2G | CC1G | UG |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x18 |
TIM1_CCMR1 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] | OC2CE | OC2M [2:0] |
OC2PE | OC2FE | CC2 S [1:0] |
OC1CE | OC1M [2:0] |
OC1PE | OC1FE | CC1 S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIM1_CCMR1 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC2F[3:0] |
IC2 PSC [1:0] |
CC2 S [1:0] |
IC1F[3:0] |
IC1 PSC [1:0] |
CC1 S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1C |
TIM1_CCMR2 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC3M[3] | OC4CE | OC4M [2:0] |
OC4PE | OC4FE | CC4 S [1:0] |
OC3CE | OC3M [2:0] |
OC3PE | OC3FE | CC3 S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIM1_CCMR2 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC4F[3:0] |
IC4 PSC [1:0] |
CC4 S [1:0] |
IC3F[3:0] |
IC3 PSC [1:0] |
CC3 S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x20 |
TIM1_CCER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6P | CC6E | Res. | Res. | CC5P | CC5E | Res. | Res. | CC4P | CC4E | CC3NP | CC3NE | CC3P | CC3E | CC2NP | CC2NE | CC2P | CC2E | CC1NP | CC1NE | CC1P | CC1E |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x24 |
TIM1_CNT
|
UIFCP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||
| 0x28 |
TIM1_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIM1_ARR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARR[15:0] |
|||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||
| 0x30 |
TIM1_RCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | REP[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x34 |
TIM1_CCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x38 |
TIM1_CCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR2[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x3C |
TIM1_CCR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR3[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x40 |
TIM1_CCR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR4[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x44 |
TIM1_BDTR
|
Res. | Res. | Res. | Res. | Res. | Res. | BK2P | BK2E | BK2F[3:0] | BKF[3:0] |
MOE | AOE | BKP | BKE | OSSR | OSSI | LOC K [1:0] |
DT[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x48 |
TIM1_DCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBL[4:0] |
Res. | Res. | Res. | DBA[4:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x4C |
TIM1_DMAR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMAB[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x54 |
TIM1_CCMR3 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC6M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC5M[3] | OC6CE | OC6M [2:0] |
OC6PE | OC6FE | Res. | Res. | OC5CE | OC5M [2:0] |
OC5PE | OC5FE | Res. | Res. | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x58 |
TIM1_CCR5
|
GC5C3 | GC5C2 | GC5C1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR5[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x5C |
TIM1_CCR6
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR6[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x60 |
TIM1_AF1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BKINP | BKDFBKE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BKINE |
| Reset value | 0 | 0 | 1 |
||||||||||||||||||||||||||||||
| 0x64 |
TIM1_AF2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BK2INP | BK2DFBKE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BK2INE |
| Reset value | 0 | 0 | 1 |
||||||||||||||||||||||||||||||
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
TIM8 registers are mapped as 16-bit addressable registers as described in the table below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIM8_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMA | Res. | CKD [1:0] |
ARPE | CMS [1:0] |
DIR | OPM | URS | UDIS | CEN | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x04 |
TIM8_CR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS2[3:0] |
Res. | OIS6 | Res. | OIS5 | Res. | OIS4 | OIS3N | OIS3 | OIS2N | OIS2 | OIS1N | OIS1 | TI1S | MMS [2:0] |
CCDS | CCUS | Res. | CCPC | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x08 |
TIM8_SMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] | ETP | ECE | ETP S [1:0] |
ETF[3:0] |
MSM | TS[2:0] |
Res. | SMS[2:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x0C |
TIM8_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TDE | COMDE | CC4DE | CC3DE | CC2DE | CC1DE | UDE | BIE | TIE | COMIE | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x10 |
TIM8_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6IF | CC5IF | Res. | Res. | SBIF | CC4OF | CC3OF | CC2OF | CC1OF | B2IF | BIF | TIF | COMIF | CC4IF | CC3IF | CC2IF | CC1IF | UIF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x14 |
TIM8_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | B2G | BG | TG | COM | CC4G | CC3G | CC2G | CC1G | UG |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x18 |
TIM8_CCMR1 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] | OC2CE | OC2M [2:0] |
OC2PE | OC2FE | CC2 S [1:0] |
OC1CE | OC1M [2:0] |
OC1PE | OC1FE | CC1 S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIM8_CCMR1 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC2F[3:0] |
IC2 PSC [1:0] |
CC2 S [1:0] |
IC1F[3:0] |
IC1 PSC [1:0] |
CC1 S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1C |
TIM8_CCMR2 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC3M[3] | OC4CE | OC4M [2:0] |
OC4PE | OC4FE | CC4 S [1:0] |
OC3CE | OC3M [2:0] |
OC3PE | OC3FE | CC3 S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIM8_CCMR2 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC4F[3:0] |
IC4 PSC [1:0] |
CC4 S [1:0] |
IC3F[3:0] |
IC3 PSC [1:0] |
CC3 S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x20 |
TIM8_CCER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC6P | CC6E | Res. | Res. | CC5P | CC5E | Res. | Res. | CC4P | CC4E | CC3NP | CC3NE | CC3P | CC3E | CC2NP | CC2NE | CC2P | CC2E | CC1NP | CC1NE | CC1P | CC1E |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x24 |
TIM8_CNT
|
UIFCPY | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||
| 0x28 |
TIM8_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIM8_ARR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARR[15:0] |
|||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||
| 0x30 |
TIM8_RCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | REP[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x34 |
TIMx_CCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x38 |
TIM8_CCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR2[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x3C |
TIM8_CCR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR3[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x40 |
TIM8_CCR4
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR4[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x44 |
TIM8_BDTR
|
Res. | Res. | Res. | Res. | Res. | Res. | BK2P | BK2E | BK2F[3:0] | BKF[3:0] |
MOE | AOE | BKP | BKE | OSSR | OSSI | LOC K [1:0] |
DT[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x48 |
TIM8_DCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBL[4:0] |
Res. | Res. | Res. | DBA[4:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x4C |
TIM8_DMAR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMAB[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x54 |
TIM8_CCMR3 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC6M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC5M[3] | OC6CE | OC6M [2:0] |
OC6PE | OC6FE | Res. | Res. | OC5CE | OC5M [2:0] |
OC5PE | OC5FE | Res. | Res. | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x58 |
TIM8_CCR5
|
GC5C3 | GC5C2 | GC5C1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR5[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x5C |
TIM8_CCR6
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR6[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x60 |
TIM8_AF1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BKINP | BKDFBKE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BKINE |
| Reset value | 0 | 0 | 1 |
||||||||||||||||||||||||||||||
| 0x64 |
TIM8_AF2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BK2INP | BK2DFBKE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BK2INE |
| Reset value | 0 | 0 | 1 |
||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 26.3.19: Timer synchronization.
General-purpose TIMx timer features include:
| (omitted) |
The main block of the programmable timer is a 16-bit/32-bit counter with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 254 and Figure 255 give some examples of the counter behavior when the prescaler ratio is changed on the fly:
| (omitted) |
| (omitted) |
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
The counter clock can be provided by the following clock sources:
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 273 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
| (omitted) |
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input.
| (omitted) |
For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 276 gives an overview of the external trigger input block.
| (omitted) |
For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.
| (omitted) |
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
| (omitted) |
The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.
| (omitted) |
| (omitted) |
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register.
When an input capture occurs:
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
This mode is a particular case of input capture mode. The procedure is the same except:
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):
| (omitted) |
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section.
This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).
Procedure
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 282.
| (omitted) |
Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only:
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting
mode on page 965.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1. If the compare value is 0 then OCxREF is held at ‘0. Figure 283 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.
| (omitted) |
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting
mode on page 968.
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at 100%. PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 971.
Figure 284 shows some center-aligned PWM waveforms in an example where:
| (omitted) |
Hints on using center-aligned mode:
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle:
Asymmetric PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
When a given channel is used as asymmetric PWM channel, its secondary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 2.
Figure 285 shows an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1).
| (omitted) |
Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs:
Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 286 shows an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration:
| (omitted) |
The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs.
This function can be used only in the output compare and PWM modes. It does not work in forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows:
Figure 287 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode.
| (omitted) |
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the
next counter overflow.
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:
| (omitted) |
For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in Section 26.3.13:
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for Retriggerable OPM mode 1 or 2.
If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode CCRx must be above or equal to ARR.
Note: In retriggerable one pulse mode, the CCxIF flag is not significant.
The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit is not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.
| (omitted) |
To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 176. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
| Active edge |
Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) |
TI1FP1 signal | TI2FP2 signal |
||
|---|---|---|---|---|---|
| Rising | Falling | Rising | Falling |
||
| Counting on TI1 only |
High | Down | Up | No Count | No Count |
| Low | Up | Down | No Count | No Count |
|
| Counting on TI2 only |
High | No Count | No Count | Up | Down |
| Low | No Count | No Count | Down | Up |
|
| Counting on TI1 and TI2 |
High | Down | Up | Up | Down |
| Low | Up | Down | Down | Up |
|
An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.
Figure 290 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:
| (omitted) |
Figure 291 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1).
| (omitted) |
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock.
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into bit 31 of the timer counter register’s bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).
There is no latency between the UIF and UIFCPY flag assertions.
In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only accessible in write mode).
The TI1S bit in the TIM1xx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input capture.
An example of this feature used to interface Hall sensors is given in Section 25.3.24:
Interfacing with Hall sensors on page 912.
The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Note: The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not
have any effect in gated mode because gated mode acts on a level and not on an edge.
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
Slave mode: External Clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
| (omitted) |
The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Figure 296: Master/Slave timer example presents an overview of the trigger selection and the master mode selection blocks.
| (omitted) |
Using one timer as prescaler for another timer
For example, you can configure TIM3 to act as a prescaler for TIM. Refer to Figure 296. To do this:
Note: If OCx is selected on TIM3 as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIM.
Using one timer to enable another timer
In this example, we control the enable of TIM with the output compare 1 of Timer 3. Refer to Figure 296 for connections. TIM counts on the divided internal clock only when OC1REF of TIM3 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
Note: The counter clock is not synchronized with counter 1, this mode only affects the TIM
counter enable signal.
| (omitted) |
In the example in Figure 297, the TIM counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given
value by resetting both timers before starting TIM3. You can then write any value you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers.
In the next example (refer to Figure 298), we synchronize TIM3 and TIM. TIM3 is the master and starts from 0. TIM is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. TIM stops when TIM3 is disabled by writing ‘0 to the CEN bit in the TIM3_CR1 register:
| (omitted) |
Using one timer to start another timer
In this example, we set the enable of Timer with the update event of Timer 3. Refer to Figure 296 for connections. Timer starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the update event is generated by Timer 1. When Timer receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
| (omitted) |
As in the previous example, you can initialize both counters before starting counting. Figure 300 shows the behavior with the same configuration as in Figure 299 but in trigger mode instead of gated mode (SMS=110 in the TIM_SMCR register).
| (omitted) |
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2 with the enable of TIM3. Refer to Figure 296 for connections. To ensure the counters are aligned, TIM3 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to TIM2):
When a rising edge occurs on TI1 (TIM3), both counters starts counting synchronously on the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on TIM3.
| (omitted) |
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.
The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes).
The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register:
Example:
00000: TIMx_CR1
00001: TIMx_CR2
00010: TIMx_SMCR
As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
This example is for the case where every CCRx register has to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.
When the microcontroller enters debug mode (Cortex®-M7 core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 40.16.2: Debug support for
timers, watchdog, bxCAN and I2C.
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | UIFRE MAP |
Res. | CKD[1:0] | ARPE | CMS | DIR | OPM | URS | UDIS | CEN |
||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | UIFREMAP: UIF status bit remapping |
|
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bits 9:8 | CKD[1:0]: Clock division |
|
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), |
|
| Bit 7 | ARPE: Auto-reload preload enable |
|
0: TIMx_ARR register is not buffered |
|
| Bits 6:5 | CMS: Center-aligned mode selection |
|
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). It is not allowed to switch from edge-aligned mode to center-aligned mode as long as |
|
| Bit 4 | DIR: Direction |
|
0: Counter used as upcounter This bit is read only when the timer is configured in Center-aligned mode or Encoder |
|
| Bit 3 | OPM: One-pulse mode |
|
0: Counter is not stopped at update event |
|
| Bit 2 | URS: Update request source |
|
This bit is set and cleared by software to select the UEV event sources.
enabled. |
|
| Bit 1 | UDIS: Update disable |
|
This bit is set and cleared by software to enable/disable UEV event generation.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
|
| Bit 0 | CEN: Counter enable |
|
0: Counter disabled External clock, gated mode and encoder mode can work only if the CEN bit has been CEN is cleared automatically in one-pulse mode, when an update event occurs. |
Address offset: 0x04
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI1S | MMS[2:0] | CCDS | Res. | Res. | Res. |
||
| rw | rw | rw | rw | rw | |||||||||||
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bit 7 | TI1S: TI1 selection |
|
0: The TIMx_CH1 pin is connected to TI1 input |
|
| Bits 6:4 | MMS[2:0]: Master mode selection |
|
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: The clock of the slave timer or ADC must be enabled prior to receive events from the |
|
| Bit 3 | CCDS: Capture/compare DMA selection |
|
0: CCx DMA request sent when CCx event occurs |
|
| Bits 2:0 | Reserved, must be kept at reset value. |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] |
ETP | ECE | ETPS[1:0] | ETF[3:0] | MSM | TS[2:0] | OCCS | SMS[2:0] |
||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | SMS[3]: Slave mode selection - bit 3 |
|
Refer to SMS description - bits 2:0. |
|
| Bit 15 | ETP: External trigger polarity |
|
This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge |
|
| Bit 14 | ECE: External clock enable |
|
This bit enables External clock mode 2. |
|
| Bits 13:12 | ETPS[1:0]: External trigger prescaler |
|
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. |
|
| Bits 11:8 | ETF[3:0]: External trigger filter |
|
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bit 7 | MSM: Master/Slave mode |
|
0: No action |
|
| Bits 6:4 | TS: Trigger selection |
|
This bit-field selects the trigger input to be used to synchronize the counter. These bits must be changed only when they are not used (e.g. when SMS=000) to |
|
| Bit 3 | OCCS: OCREF clear selection |
|
This bit is used to select the OCREF clear source |
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
0000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.
| Slave TIM | ITR0 (TS = 000) | ITR1 (TS = 001) | ITR2 (TS = 010) | ITR3 (TS = 011) |
|---|---|---|---|---|
| TIM2 | TIM1 | TIM8/ETH_PTP/OTG_FS _SOF/OTG_HS_SOF(1) |
TIM3 | TIM4 |
| TIM3 | TIM1 | TIM2 | TIM5 | TIM4 |
| TIM4 | TIM1 | TIM2 | TIM3 | TIM8 |
| TIM5 | TIM2 | TIM3 | TIM4 | TIM8 |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | TDE | Res. | CC4DE | CC3DE | CC2DE | CC1DE | UDE | Res. | TIE | Res. | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | TDE: Trigger DMA request enable |
|
0: Trigger DMA request disabled. |
|
| Bit 13 | Reserved, must be kept at reset value. |
| Bit 12 | CC4DE: Capture/Compare 4 DMA request enable |
|
0: CC4 DMA request disabled. |
|
| Bit 11 | CC3DE: Capture/Compare 3 DMA request enable |
|
0: CC3 DMA request disabled. |
|
| Bit 10 | CC2DE: Capture/Compare 2 DMA request enable |
|
0: CC2 DMA request disabled. |
|
| Bit 9 | CC1DE: Capture/Compare 1 DMA request enable |
|
0: CC1 DMA request disabled. |
|
| Bit 8 | UDE: Update DMA request enable |
|
0: Update DMA request disabled. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | TIE: Trigger interrupt enable |
|
0: Trigger interrupt disabled. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | CC4IE: Capture/Compare 4 interrupt enable |
|
0: CC4 interrupt disabled. |
|
| Bit 3 | CC3IE: Capture/Compare 3 interrupt enable |
|
0: CC3 interrupt disabled. |
|
| Bit 2 | CC2IE: Capture/Compare 2 interrupt enable |
|
0: CC2 interrupt disabled. |
|
| Bit 1 | CC1IE: Capture/Compare 1 interrupt enable |
|
0: CC1 interrupt disabled. |
|
| Bit 0 | UIE: Update interrupt enable |
|
0: Update interrupt disabled. |
Address offset: 0x10
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CC4OF | CC3OF | CC2OF | CC1OF | Res. | Res. | TIF | Res. | CC4IF | CC3IF | CC2IF | CC1IF | UIF |
| rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 |
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bit 12 | CC4OF: Capture/Compare 4 overcapture flag |
|
refer to CC1OF description |
|
| Bit 11 | CC3OF: Capture/Compare 3 overcapture flag |
|
refer to CC1OF description |
|
| Bit 10 | CC2OF: Capture/compare 2 overcapture flag |
|
refer to CC1OF description |
|
| Bit 9 | CC1OF: Capture/Compare 1 overcapture flag |
|
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. |
|
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | TIF: Trigger interrupt flag |
|
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | CC4IF: Capture/Compare 4 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 3 | CC3IF: Capture/Compare 3 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 2 | CC2IF: Capture/Compare 2 interrupt flag |
|
Refer to CC1IF description |
|
| Bit 1 | CC1IF: Capture/compare 1 interrupt flag |
|
If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description) and in retriggerable one pulse mode. It is cleared by software. |
|
| Bit 0 | UIF: Update interrupt flag |
|
This bit is set by hardware on an update event. It is cleared by software. |
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TG | Res. | CC4G | CC3G | CC2G | CC1G | UG |
| w | w | w | w | w | w |
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bit 6 | TG: Trigger generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | CC4G: Capture/compare 4 generation |
|
Refer to CC1G description |
|
| Bit 3 | CC3G: Capture/compare 3 generation |
|
Refer to CC1G description |
|
| Bit 2 | CC2G: Capture/compare 2 generation |
|
Refer to CC1G description |
|
| Bit 1 | CC1G: Capture/compare 1 generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 0 | UG: Update generation |
|
This bit can be set by software, it is automatically cleared by hardware. |
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M [3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M [3] |
OC2CE | OC2M[2:0] | OC2PE | OC2FE |
CC2S[1:0] |
OC1CE | OC1M[2:0] | OC1PE | OC1FE |
CC1S[1:0] |
||||||
| Res. | Res. |
IC2F[3:0] | IC2PSC[1:0] | IC1F[3:0] | IC1PSC[1:0] |
||||||||||||||||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, always read as 0. |
| Bit 24 | OC2M[3]: Output Compare 2 mode - bit 3 |
| Bits 23:17 | Reserved, always read as 0. |
| Bit 16 | OC1M[3]: Output Compare 1 mode - bit 3 |
| Bit 15 | OC2CE: Output compare 2 clear enable |
| Bits 14:12 | OC2M[2:0]: Output compare 2 mode |
|
refer to OC1M description on bits 6:4 |
|
| Bit 11 | OC2PE: Output compare 2 preload enable |
| Bit 10 | OC2FE: Output compare 2 fast enable |
| Bits 9:8 | CC2S[1:0]: Capture/Compare 2 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output
CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
|
|
| Bit 7 | OC1CE: Output compare 1 clear enable |
|
0: OC1Ref is not affected by the ETRF input |
|
| Bits 6:4 | OC1M: Output compare 1 mode |
|
These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
1: These bits can not be modified as long as LOCK level 3 has been programmed 2: In PWM mode, the OCREF level changes only when the result of the comparison |
|
| Bit 3 | OC1PE: Output compare 1 preload enable |
|
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
1: These bits can not be modified as long as LOCK level 3 has been programmed
2: The PWM mode can be used without validating the preload register only in one- |
|
| Bit 2 | OC1FE: Output compare 1 fast enable |
|
This bit is used to accelerate the effect of an event on the trigger in input on the CC output. |
|
| Bits 1:0 | CC1S: Capture/Compare 1 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output.
CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
|
Input capture mode
| Bits 31:16 | Reserved, always read as 0. |
| Bits 15:12 | IC2F: Input capture 2 filter |
| Bits 11:10 | IC2PSC[1:0]: Input capture 2 prescaler |
| Bits 9:8 | CC2S: Capture/compare 2 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). |
|
| Bits 7:4 | IC1F: Input capture 1 filter |
|
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bits 3:2 | IC1PSC: Input capture 1 prescaler |
|
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). |
|
| Bits 1:0 | CC1S: Capture/Compare 1 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output
CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
|
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4M [3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC3M [3] |
OC4CE | OC4M[2:0] | OC4PE | OC4FE |
CC4S[1:0] |
OC3CE | OC3M[2:0] | OC3PE | OC3FE |
CC3S[1:0] |
||||||
| Res. | Res. |
IC4F[3:0] | IC4PSC[1:0] | IC3F[3:0] | IC3PSC[1:0] |
||||||||||||||||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, always read as 0. |
| Bit 24 | OC4M[3]: Output Compare 2 mode - bit 3 |
| Bits 23:17 | Reserved, always read as 0. |
| Bit 16 | OC3M[3]: Output Compare 1 mode - bit 3 |
| Bit 15 | OC4CE: Output compare 4 clear enable |
| Bits 14:12 | OC4M: Output compare 4 mode |
|
Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |
|
| Bit 11 | OC4PE: Output compare 4 preload enable |
| Bit 10 | OC4FE: Output compare 4 fast enable |
| Bits 9:8 | CC4S: Capture/Compare 4 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output
CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
|
|
| Bit 7 | OC3CE: Output compare 3 clear enable |
| Bits 6:4 | OC3M: Output compare 3 mode |
|
Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |
|
| Bit 3 | OC3PE: Output compare 3 preload enable |
| Bit 2 | OC3FE: Output compare 3 fast enable |
| Bits 1:0 | CC3S: Capture/Compare 3 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output
CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
|
Input capture mode
| Bits 31:16 | Reserved, always read as 0. |
| Bits 15:12 | IC4F: Input capture 4 filter |
| Bits 11:10 | IC4PSC: Input capture 4 prescaler |
| Bits 9:8 | CC4S: Capture/Compare 4 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). |
|
| Bits 7:4 | IC3F: Input capture 3 filter |
| Bits 3:2 | IC3PSC: Input capture 3 prescaler |
| Bits 1:0 | CC3S: Capture/Compare 3 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output
CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
|
Address offset: 0x20
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CC4NP | Res. | CC4P | CC4E | CC3NP | Res. | CC3P | CC3E | CC2NP | Res. | CC2P | CC2E | CC1NP | Res. | CC1P | CC1E |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 15 | CC4NP: Capture/Compare 4 output Polarity. |
|
Refer to CC1NP description |
|
| Bit 14 | Reserved, must be kept at reset value. |
| Bit 13 | CC4P: Capture/Compare 4 output Polarity. |
|
Refer to CC1P description |
|
| Bit 12 | CC4E: Capture/Compare 4 output enable. |
|
refer to CC1E description |
|
| Bit 11 | CC3NP: Capture/Compare 3 output Polarity. |
|
Refer to CC1NP description |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bit 9 | CC3P: Capture/Compare 3 output Polarity. |
|
Refer to CC1P description |
|
| Bit 8 | CC3E: Capture/Compare 3 output enable. |
|
Refer to CC1E description |
|
| Bit 7 | CC2NP: Capture/Compare 2 output Polarity. |
|
Refer to CC1NP description |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bit 5 | CC2P: Capture/Compare 2 output Polarity. |
|
refer to CC1P description |
|
| Bit 4 | CC2E: Capture/Compare 2 output enable. |
|
Refer to CC1E description |
|
| Bit 3 | CC1NP: Capture/Compare 1 output Polarity. |
|
CC1 channel configured as output: CC1NP must be kept cleared in this case. |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1P: Capture/Compare 1 output Polarity. |
|
CC1 channel configured as output: |
|
| Bit 0 | CC1E: Capture/Compare 1 output enable. |
|
CC1 channel configured as output: |
| CCxE bit | OCx output state |
| 0 | Output Disabled (OCx=0, OCx_EN=0) |
| 1 | OCx=OCxREF + Polarity, OCx_EN=1 |
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO and AFIO registers.
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CNT[31] or UIFCPY |
CNT[30:16] |
CNT[15:0] |
|||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | Value depends on IUFREMAP in TIMx_CR1. |
|
If UIFREMAP = 0 |
|
| Bits 30:16 | CNT[30:16]: Most significant part counter value (on TIM2 and TIM5) |
| Bits 15:0 | CNT[15:0]: Least significant part of counter value |
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PSC[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | PSC[15:0]: Prescaler value |
|
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
Address offset: 0x2C
Reset value: 0xFFFF FFFF
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[31:16] |
ARR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | ARR[31:16]: High auto-reload value (on TIM2 and TIM5) |
| Bits 15:0 | ARR[15:0]: Low Auto-reload value |
|
ARR is the value to be loaded in the actual auto-reload register. |
Address offset: 0x34
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR1[31:16] (depending on timers) |
CCR1[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5) |
| Bits 15:0 | CCR1[15:0]: Low Capture/Compare 1 value |
|
If channel CC1 is configured as output: If channel CC1is configured as input: |
Address offset: 0x38
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR2[31:16] (depending on timers) |
CCR2[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5) |
| Bits 15:0 | CCR2[15:0]: Low Capture/Compare 2 value |
|
If channel CC2 is configured as output: |
Address offset: 0x3C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR3[31:16] (depending on timers) |
CCR3[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5) |
| Bits 15:0 | CCR3[15:0]: Low Capture/Compare value |
|
If channel CC3 is configured as output: |
Address offset: 0x40
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR4[31:16] (depending on timers) |
CCR4[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5) |
| Bits 15:0 | CCR4[15:0]: Low Capture/Compare value |
|
Address offset: 0x48
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | DBL[4:0] | Res. | Res. | Res. | DBA[4:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:8 | DBL[4:0]: DMA burst length |
|
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bits 4:0 | DBA[4:0]: DMA base address |
|
This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. |
Address offset: 0x4C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMAB[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | DMAB[15:0]: DMA register for burst accesses |
|
A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). |
Address offset: 0x50
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | ITR1_RMP[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
|
| rw | rw |
||||||||||||||
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:10 | ITR1_RMP[1:0]: Internal trigger 1 remap |
|
Set and cleared by software. |
|
| Bits 9:0 | Reserved, must be kept at reset value. |
Address offset: 0x50
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI4_RMP[1:0] | Res. | Res. | Res. | Res. | Res. | Res. |
|
| rw | rw |
||||||||||||||
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bits 7:6 | TI4_RMP[1:0]: Timer Input 4 remap |
|
Set and cleared by software. |
|
| Bits 5:0 | Reserved, must be kept at reset value. |
TIMx registers are mapped as described in the table below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIMx_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMA | Res. | CKD [1:0] |
ARPE | CMS [1:0] |
DIR | OPM | URS | UDIS | CEN | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x04 |
TIMx_CR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI1S | MMS[2:0] |
CCDS | Res. | Res. | Res. | ||
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x08 |
TIMx_SMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] | ETP | ECE | ETPS [1:0] | ETF[3:0] |
MSM | TS[2:0] |
OCCS | SMS[2:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x0C |
TIMx_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TDE | COMDE | CC4DE | CC3DE | CC2DE | CC1DE | UDE | Res. | TIE | Res. | CC4IE | CC3IE | CC2IE | CC1IE | UIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x10 |
TIMx_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC4OF | CC3OF | CC2OF | CC1OF | Res. | Res. | TIF | Res. | CC4IF | CC3IF | CC2IF | CC1IF | UIF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x14 |
TIMx_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TG | Res. | CC4G | CC3G | CC2G | CC1G | UG |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x18 |
TIMx_CCMR1 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] | OC2CE | OC2M [2:0] |
OC2PE | OC2FE | CC2S [1:0] |
OC1CE | OC1M [2:0] |
OC1PE | OC1FE | CC1S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIMx_CCMR1 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC2F[3:0] |
IC2 PSC [1:0] |
CC2S [1:0] | IC1F[3:0] |
IC1 PSC [1:0] |
CC1S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1C |
TIMx_CCMR2 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC4M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC3M[3] | O24CE | OC4M [2:0] |
OC4PE | OC4FE | CC4S [1:0] |
OC3CE | OC3M [2:0] |
OC3PE | OC3FE | CC3S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| TIMx_CCMR2 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC4F[3:0] |
IC4 PSC [1:0] |
CC4S [1:0] | IC3F[3:0] |
IC3 PSC [1:0] |
CC3S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x20 |
TIMx_CCER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC4NP | Res. | CC4P | CC4E | CC3NP | Res. | CC3P | CC3E | CC2NP | Res. | CC2P | CC2E | CC1NP | Res. | CC1P | CC1E |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||
| 0x24 |
TIMx_CNT
|
CNT[31] or UIFCPY | CNT[30:16] (TIM2 and TIM5 only, reserved on the other timers) |
CNT[15:0] |
|||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x28 |
TIMx_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIMx_ARR | ARR[31:16] (TIM2 and TIM5 only, reserved on the other timers) |
ARR[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x30 | Reserved |
||||||||||||||||||||||||||||||||
| 0x34 |
TIMx_CCR1 | CCR1[31:16] (TIM2 and TIM5 only, reserved on the other timers) |
CCR1[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x38 |
TIMx_CCR2 | CCR2[31:16] (TIM2 and TIM5 only, reserved on the other timers) |
CCR2[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x3C |
TIMx_CCR3 | CCR3[31:16] (TIM2 and TIM5 only, reserved on the other timers) |
CCR3[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x40 |
TIMx_CCR4 | CCR4[31:16] (TIM2 and TIM5 only, reserved on the other timers) |
CCR4[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x44 | Reserved |
||||||||||||||||||||||||||||||||
| 0x48 |
TIMx_DCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBL[4:0] |
Res. | Res. | Res. | DBA[4:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x4C |
TIMx_DMAR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMAB[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x50 |
TIM2_OR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ITR1_RMP[1:0 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x50 |
TIM5_OR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI4_RMP[1:0 | Res. | Res. | Res. | Res. | Res. | Res. | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 general-purpose timers consist in a 16-bit auto-reload counter driven by a programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 27.3.17:
Timer synchronization (TIM9/TIM12).
The features of the TIM9/TIM12 general-purpose timers include:
| (omitted) |
The features of general-purpose timers TIM10/TIM11/TIM13/TIM14 include:
| (omitted) |
The main block of the timer is a 16-bit up-counter with its related auto-reload register. The counters counts up.
The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in details for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 304 and Figure 305 give some examples of the counter behavior when the prescaler ratio is changed on the fly.
| (omitted) |
| (omitted) |
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9/TIM12) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
The counter clock can be provided by the following clock sources:
Internal clock source (CK_INT)
The internal clock source is the default clock source for TIM10/TIM11/TIM13/TIM14.
For TIM9/TIM12, the internal clock source is selected when the slave mode controller is disabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 312 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
r
| (omitted) |
External clock source mode 1 (TIM9/TIM12)
This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input.
| (omitted) |
For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Figure 315 to Figure 317 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
| (omitted) |
The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.
| (omitted) |
| (omitted) |
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register.
When an input capture occurs:
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.
This mode is a particular case of input capture mode. The procedure is the same except:
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):
| (omitted) |
In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘0101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘0100’ in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below.
This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).
Procedure:
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 319.
| (omitted) |
Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT ≤ TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 320 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.
| (omitted) |
Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs:
Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
When a given channel is used as a combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 321 represents an example of signals that can be generated using combined PWM mode, obtained with the following configuration:
| (omitted) |
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows:
CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
| (omitted) |
For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.
Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with non-retriggerable one pulse mode described in Section 27.3.11: One-pulse mode:
The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for retrigerrable OPM mode 1 or 2.
If the timer is configured in up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in down-counting mode, CCRx must be above or equal to ARR.
Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the
most significant bit are not contiguous with the 3 least significant ones.
This mode must not be used with center-aligned PWM modes. It is mandatory to have
CMS[1:0] = 00 in TIMx_CR1.
| (omitted) |
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2.
The XOR output can be used with all the timer input functions such as trigger or input capture. It is useful for measuring the interval between the edges on two input signals, as shown in Figure 324.
| (omitted) |
The TIM9/TIM12 timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
| (omitted) |
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
| (omitted) |
In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter.
This mode is used for one-pulse mode.
The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 26.3.19: Timer synchronization for details.
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
When the microcontroller enters debug mode (Cortex®-M7 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 40.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | UIFRE MAP |
Res. | CKD[1:0] | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
|
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | UIFREMAP: UIF status bit remapping |
|
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bits 9:8 | CKD[1:0]: Clock division |
|
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), |
|
| Bit 7 | ARPE: Auto-reload preload enable |
|
0: TIMx_ARR register is not buffered. |
|
| Bits 6:4 | Reserved, must be kept at reset value. |
| Bit 3 | OPM: One-pulse mode |
|
0: Counter is not stopped on the update event |
|
| Bit 2 | URS: Update request source |
|
This bit is set and cleared by software to select the UEV event sources.
|
|
| Bit 1 | UDIS: Update disable |
|
This bit is set and cleared by software to enable/disable update event (UEV) generation.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. |
|
| Bit 0 | CEN: Counter enable |
|
0: Counter disabled
External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware. |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MSM | TS[2:0] | Res. | SMS[2:0] |
||||
| rw |
rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | SMS[3]: Slave mode selection - bit 3 |
|
Refer to SMS description - bits 2:0 |
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bit 7 | MSM: Master/Slave mode |
|
0: No action |
|
| Bits 6:4 | TS[2:0]: Trigger selection |
|
This bitfield selects the trigger input to be used to synchronize the counter. These bits must be changed only when they are not used (e.g. when SMS=’000’) to |
|
| Bit 3 | Reserved, must be kept at reset value. |
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
0001: Reserved 0010: Reserved 0011: Reserved
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Note: The clock of the slave timer must be enabled prior to receive events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.
| Slave TIM | ITR0 (TS = ‘000’) | ITR1 (TS = ‘001’) | ITR2 (TS = ‘010’) | ITR3 (TS = ‘011’) |
|---|---|---|---|---|
| TIM9 | TIM2 | TIM3 | TIM10_OC | TIM11_OC |
| TIM12 | TIM4 | TIM5 | TIM13_OC | TIM14_OC |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TIE | Res. | Res. | Res. | CC2IE | CC1IE | UIE |
| rw | rw | rw | rw |
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bit 6 | TIE: Trigger interrupt enable |
|
0: Trigger interrupt disabled. |
|
| Bits 5:3 | Reserved, must be kept at reset value. |
| Bit 2 | CC2IE: Capture/Compare 2 interrupt enable |
|
0: CC2 interrupt disabled. |
|
| Bit 1 | CC1IE: Capture/Compare 1 interrupt enable |
|
0: CC1 interrupt disabled. |
|
| Bit 0 | UIE: Update interrupt enable |
|
0: Update interrupt disabled. |
Address offset: 0x10
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | CC2OF | CC1OF | Res. | Res. | TIF | Res. | Res. | Res. | CC2IF | CC1IF | UIF |
| rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 |
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bit 10 | CC2OF: Capture/compare 2 overcapture flag |
|
refer to CC1OF description |
|
| Bit 9 | CC1OF: Capture/Compare 1 overcapture flag |
|
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. |
|
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | TIF: Trigger interrupt flag |
|
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. |
|
| Bits 5:3 | Reserved, must be kept at reset value. |
| Bit 2 | CC2IF: Capture/Compare 2 interrupt flag |
|
refer to CC1IF description |
|
| Bit 1 | CC1IF: Capture/compare 1 interrupt flag |
|
If channel CC1 is configured as output: |
|
| Bit 0 | UIF: Update interrupt flag |
|
This bit is set by hardware on an update event. It is cleared by software.
|
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TG | Res. | Res. | Res. | CC2G | CC1G | UG |
| w | w | w | w |
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bit 6 | TG: Trigger generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bits 5:3 | Reserved, must be kept at reset value. |
| Bit 2 | CC2G: Capture/compare 2 generation |
|
refer to CC1G description |
|
| Bit 1 | CC1G: Capture/compare 1 generation |
|
This bit is set by software to generate an event, it is automatically cleared by hardware. |
|
| Bit 0 | UG: Update generation |
|
This bit can be set by software, it is automatically cleared by hardware. |
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. So you must take care that the same bit can have different meanings for the input stage and the output stage.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OC2M [3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OC1M [3] |
Res. | OC2M[2:0] | OC2PE | OC2FE |
CC2S[1:0] |
Res. | OC1M[2:0] | OC1PE | OC1FE |
CC1S[1:0] |
||||||
| Res. | Res. |
IC2F[3:0] | IC2PSC[1:0] | IC1F[3:0] | IC1PSC[1:0] |
||||||||||||||||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||
Output compare mode
| Bits 31:25 | Reserved, always read as 0 |
| Bit 24 | OC2M[3]: Output Compare 2 mode - bit 3 |
|
Refer to OC2M description on bits 14:12 |
|
| Bits 23:17 | Reserved, always read as 0 |
| Bit 16 | OC1M[3]: Output Compare 1 mode - bit 3 |
|
Refer to OC1M description on bits 6:4 |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:12 | OC2M[2:0]: Output compare 2 mode |
|
Refer to OC1M[3:0] for bit description. |
|
| Bit 11 | OC2PE: Output compare 2 preload enable |
| Bit 10 | OC2FE: Output compare 2 fast enable |
| Bits 9:8 | CC2S[1:0]: Capture/Compare 2 selection |
|
This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output
The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
|
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bits 6:4 | OC1M[3:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) |
|
These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas the active level of OC1 depends on the CC1P. In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison |
|
| Bit 3 | OC1PE: Output compare 1 preload enable |
|
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately The PWM mode can be used without validating the preload register only in one-pulse |
|
| Bit 2 | OC1FE: Output compare 1 fast enable |
|
This bit is used to accelerate the effect of an event on the trigger in input on the CC output. |
|
| Bits 1:0 | CC1S[1:0]: Capture/Compare 1 selection |
|
This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). |
Input capture mode
| Bits 15:12 | IC2F: Input capture 2 filter |
| Bits 11:10 | IC2PSC[1:0]: Input capture 2 prescaler |
| Bits 9:8 | CC2S: Capture/compare 2 selection |
|
This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output
The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
|
|
| Bits 7:4 | IC1F: Input capture 1 filter |
|
This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bits 3:2 | IC1PSC: Input capture 1 prescaler |
|
This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). |
|
| Bits 1:0 | CC1S[1:0]: Capture/Compare 1 selection |
|
This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). |
Address offset: 0x20
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC2NP | Res. | CC2P | CC2E | CC1NP | Res. | CC1P | CC1E |
| rw | rw | rw | rw | rw | rw |
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bit 7 | CC2NP: Capture/Compare 2 output Polarity |
|
Refer to CC1NP description |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bit 5 | CC2P: Capture/Compare 2 output Polarity |
|
Refer to CC1P description |
|
| Bit 4 | CC2E: Capture/Compare 2 output enable |
|
Refer to CC1E description |
|
| Bit 3 | CC1NP: Capture/Compare 1 complementary output Polarity |
|
CC1 channel configured as output: CC1NP must be kept cleared |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1P: Capture/Compare 1 output Polarity. |
|
CC1 channel configured as output: |
|
| Bit 0 | CC1E: Capture/Compare 1 output enable. |
|
CC1 channel configured as output: |
| CCxE bit | OCx output state |
|---|---|
| 0 | Output disabled (OCx=’0’, OCx_EN=’0’) |
| 1 | OCx=OCxREF + Polarity, OCx_EN=’1’ |
Note: The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UIF CPY |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CNT[15:0] |
|||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bit 31 | UIFCPY: UIF Copy |
|
This bit is a read-only copy of the UIF bit in the TIMx_ISR register. |
|
| Bits 30:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CNT[15:0]: Counter value |
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PSC[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | PSC[15:0]: Prescaler value |
|
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
Address offset: 0x2C
Reset value: 0xFFFF
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | ARR[15:0]: Auto-reload value |
|
ARR is the value to be loaded into the actual auto-reload register. |
Address offset: 0x34
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR1[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR1[15:0]: Capture/Compare 1 value |
|
If channel CC1 is configured as output: |
Address offset: 0x38
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR2[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR2[15:0]: Capture/Compare 2 value |
|
If channel CC2 is configured as output: |
TIM9/TIM12 registers are mapped as 16-bit addressable registers as described below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIMx_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMA | Res. | CKD [1:0] |
ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x08 |
TIMx_SMCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SMS[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MSM | TS[2:0] |
Res. | SMS[2:0] |
||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x0C |
TIMx_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TIE | Res. | Res. | Res. | CC2IE | CC1IE | UIE |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x10 |
TIMx_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC2OF | CC1OF | Res. | Res. | TIF | Res. | Res. | Res. | CC2IF | CC1IF | UIF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x14 |
TIMx_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TG | Res. | Res. | Res. | CC2G | CC1G | UG |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x18 |
TIMx_CCMR1 Output Compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC2M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] | Res. | OC2M [2:0] |
OC2PE | OC2FE | CC2S [1:0] |
Res. | OC1M [2:0] |
OC1PE | OC1FE | CC1 S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| TIMx_CCMR1 Input Capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC2F[3:0] |
IC2 PSC [1:0] |
CC2S [1:0] | IC1F[3:0] |
IC1 PSC [1:0] |
CC1 S [1:0] |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1C | Reserved | Res. |
|||||||||||||||||||||||||||||||
| 0x20 |
TIMx_CCER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC2NP | Res. | CC2P | CC2E | CC1NP | Res. | CC1P | CC1E |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x24 |
TIMx_CNT
|
UIFCPY | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x28 |
TIMx_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIMx_ARR
|
Reserved |
ARR[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||
| 0x30 | Reserved | Reserved |
|||||||||||||||||||||||||||||||
| 0x34 |
TIMx_CCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x38 |
TIMx_CCR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR2[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | UIFRE MAP |
Res. | CKD[1:0] | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
|
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | UIFREMAP: UIF status bit remapping |
|
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bits 9:8 | CKD[1:0]: Clock division |
|
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), |
|
| Bit 7 | ARPE: Auto-reload preload enable |
|
0: TIMx_ARR register is not buffered |
|
| Bits 6:4 | Reserved, must be kept at reset value. |
| Bit 3 | OPM: One-pulse mode |
|
0: Counter is not stopped on the update event |
|
| Bit 2 | URS: Update request source |
|
This bit is set and cleared by software to select the update interrupt (UEV) sources.
|
|
| Bit 1 | UDIS: Update disable |
|
This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. |
|
| Bit 0 | CEN: Counter enable |
|
0: Counter disabled
External clock and gated mode can work only if the CEN bit has been previously set by
software. However trigger mode can set the CEN bit automatically by hardware. |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1IE | UIE |
| rw | rw |
| Bits 15:2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1IE: Capture/Compare 1 interrupt enable |
|
0: CC1 interrupt disabled |
|
| Bit 0 | UIE: Update interrupt enable |
|
0: Update interrupt disabled |
Address offset: 0x10
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | CC1OF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1IF | UIF |
| rc_w0 | rc_w0 | rc_w0 |
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bit 9 | CC1OF: Capture/Compare 1 overcapture flag |
|
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. |
|
| Bits 8:2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1IF: Capture/compare 1 interrupt flag |
|
If channel CC1 is configured as output: |
|
| Bit 0 | UIF: Update interrupt flag |
|
This bit is set by hardware on an update event. It is cleared by software.
|
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1G | UG |
| w | w |
| Bits 15:2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1G: Capture/compare 1 generation |
|
This bit is set by software in order to generate an event, it is automatically cleared by hardware. |
|
| Bit 0 | UG: Update generation |
|
This bit can be set by software, it is automatically cleared by hardware. |
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OC1M [3] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[2:0] | OC1PE | OC1FE |
CC1S[1:0] |
|||
| Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC1F[3:0] | IC1PSC[1:0] |
|||||||||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||||||||||||
Output compare mode
| Bits 31:17 | Reserved, always read as 0 |
| Bit 16 | OC1M[3]: Output Compare 1 mode - bit 3 |
|
Refer to OC1M description on bits 6:4 |
|
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bits 6:4 | OC1M[3:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) |
|
These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. 0000: Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. In PWM mode 1 or 2, the OCREF level changes when the result of the comparison |
|
| Bit 3 | OC1PE: Output compare 1 preload enable |
|
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. The PWM mode can be used without validating the preload register only in one pulse |
|
| Bit 2 | OC1FE: Output compare 1 fast enable |
|
This bit is used to accelerate the effect of an event on the trigger in input on the CC output. |
|
| Bits 1:0 | CC1S[1:0]: Capture/Compare 1 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). |
Input capture mode
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bits 7:4 | IC1F: Input capture 1 filter |
|
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: |
|
| Bits 3:2 | IC1PSC: Input capture 1 prescaler |
|
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). |
|
| Bits 1:0 | CC1S[1:0]: Capture/Compare 1 selection |
|
This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output
CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
|
Address offset: 0x20
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1NP | Res. | CC1P | CC1E |
| rw | rw | rw |
| Bits 15:4 | Reserved, must be kept at reset value. |
| Bit 3 | CC1NP: Capture/Compare 1 complementary output Polarity. |
|
CC1 channel configured as output: CC1NP must be kept cleared. |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bit 1 | CC1P: Capture/Compare 1 output Polarity. |
|
CC1 channel configured as output: |
|
| Bit 0 | CC1E: Capture/Compare 1 output enable. |
|
CC1 channel configured as output: |
| CCxE bit | OCx output state |
| 0 | Output Disabled (OCx=’0’, OCx_EN=’0’) |
| 1 | OCx=OCxREF + Polarity, OCx_EN=’1’ |
Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UIF CPY |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CNT[15:0] |
|||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||||
| Bit 31 | UIFCPY: UIF Copy |
|
This bit is a read-only copy of the UIF bit in the TIMx_ISR register. |
|
| Bits 30:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CNT[15:0]: Counter value |
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PSC[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | PSC[15:0]: Prescaler value |
|
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). |
Address offset: 0x2C
Reset value: 0xFFFF
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | ARR[15:0]: Auto-reload value |
|
ARR is the value to be loaded in the actual auto-reload register. |
Address offset: 0x34
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CCR1[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CCR1[15:0]: Capture/Compare 1 value |
|
If channel CC1 is configured as output: If channel CC1is configured as input: |
Address offset: 0x50
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI1_RMP[1:0] |
| rw |
| Bits 15:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | TI1_RMP[1:0]: TIM11 Input 1 remapping capability |
|
Set and cleared by software. |
TIMx registers are mapped as 16-bit addressable registers as described in the tables below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIMx_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMA | Res. | CKD [1:0] |
ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x04 to 0x08 |
Reserved | Res. |
|||||||||||||||||||||||||||||||
| 0x0C |
TIMx_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1IE | UIE |
| Reset value | 0 | 0 | |||||||||||||||||||||||||||||||
| 0x10 |
TIMx_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1OF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1IF | UIF |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x14 |
TIMx_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1G | UG |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x18 |
TIMx_CCMR1 Output compare mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M[3] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OC1M [2:0] |
OC1PE | OC1FE | CC1S [1:0] |
|||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| TIMx_CCMR1 Input capture mode |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IC1F[3:0] |
IC1 PSC [1:0] |
CC1S [1:0] |
||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x1C | Reserved | Res. |
|||||||||||||||||||||||||||||||
| 0x20 |
TIMx_CCER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CC1NP | Res. | CC1P | CC1E |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x24 |
TIMx_CNT
|
UIFCPY | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x28 |
TIMx_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIMx_ARR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARR[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x30 | Reserved | Res. |
|||||||||||||||||||||||||||||||
| 0x34 |
TIMx_CCR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CCR1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x38 to 0x4C |
Reserved | Res. |
|||||||||||||||||||||||||||||||
| 0x50 |
TIMx_OR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TI1_RMP | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.
The timers are completely independent, and do not share any resources.
Basic timer (TIM6/TIM7) features include:
| (omitted) |
The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 329 and Figure 330 give some examples of the counter behavior when the prescaler ratio is changed on the fly.
| (omitted) |
| (omitted) |
The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 337 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
| (omitted) |
When the microcontroller enters the debug mode (Cortex®-M7 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 40.16.2: Debug
support for timers, watchdog, bxCAN and I2C.
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | UIFRE MAP |
Res. | Res. | Res. | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
| rw | rw | rw | rw | rw | rw |
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bit 11 | UIFREMAP: UIF status bit remapping |
|
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. |
|
| Bits 10:8 | Reserved, must be kept at reset value. |
| Bit 7 | ARPE: Auto-reload preload enable |
|
0: TIMx_ARR register is not buffered. |
|
| Bits 6:4 | Reserved, must be kept at reset value. |
| Bit 3 | OPM: One-pulse mode |
|
0: Counter is not stopped at update event |
|
| Bit 2 | URS: Update request source |
|
This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
enabled. |
|
| Bit 1 | UDIS: Update disable |
|
This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
|
| Bit 0 | CEN: Counter enable |
|
0: Counter disabled Gated mode can work only if the CEN bit has been previously set by software. CEN is cleared automatically in one-pulse mode, when an update event occurs. |
Address offset: 0x04
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS[2:0] | Res. | Res. | Res. | Res. |
||
| rw | rw | rw |
|||||||||||||
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bits 6:4 | MMS: Master mode selection |
|
These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. The clock of the slave timer or ADC must be enabled prior to receive events from the |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIE |
| rw | rw |
| Bits 15:9 | Reserved, must be kept at reset value. |
| Bit 8 | UDE: Update DMA request enable |
|
0: Update DMA request disabled. |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | UIE: Update interrupt enable |
|
0: Update interrupt disabled. |
Address offset: 0x10
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIF |
| rc_w0 |
| Bits 15:1 | Reserved, must be kept at reset value. |
| Bit 0 | UIF: Update interrupt flag |
|
This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
|
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UG |
| w |
| Bits 15:1 | Reserved, must be kept at reset value. |
| Bit 0 | UG: Update generation |
|
This bit can be set by software, it is automatically cleared by hardware. 0: No action. |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UIF CPY |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CNT[15:0] |
|||||||||||||||
| r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||||
| Bit 31 | UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. |
| Bits 30:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CNT[15:0]: Counter value |
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PSC[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
|
PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). |
Address offset: 0x2C
Reset value: 0xFFFF
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | ARR[15:0]: Prescaler value |
|
ARR is the value to be loaded into the actual auto-reload register. Refer to Section 28.3.1: Time-base unit on page 1081 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. |
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
TIMx_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIFREMA | Res. | Res. | Res. | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x04 |
TIMx_CR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS [2:0] |
Res. | Res. | Res. | Res. | ||
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x08 | Reserved |
||||||||||||||||||||||||||||||||
| 0x0C |
TIMx_DIER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIE |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x10 |
TIMx_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIF |
| Reset value | 0 |
||||||||||||||||||||||||||||||||
| 0x14 |
TIMx_EGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UG |
| Reset value | 0 |
||||||||||||||||||||||||||||||||
| 0x18- 0x20 |
Reserved |
||||||||||||||||||||||||||||||||
| 0x24 |
TIMx_CNT
|
UIFCPY or Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x28 |
TIMx_PSC
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
TIMx_ARR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARR[15:0] |
|||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||||||||||||||||
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter” which can be useful in some applications. Also, the LPTIM capability to wake up the system from low-power modes, makes it suitable to realize “Timeout functions” with extremely low power consumption.
The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance, while minimizing the power consumption.
Table 186 describes LPTIM implementation on STM32F76xxx and STM32F77xxx devices: the full set of features is implemented in LPTIM1.
| LPTIM modes/features(1) |
LPTIM1 |
|---|---|
| Encoder mode | X |
| (omitted) |
The LPTIM external trigger connections are detailed hereafter:
| TRIGSEL | External trigger |
|---|---|
| lptim_ext_trig0 | GPIO |
| lptim_ext_trig1 | RTC_ALARMA |
| lptim_ext_trig2 | RTC_ALARMB |
| lptim_ext_trig3 | RTC_TAMP1_OUT |
| lptim_ext_trig4 | RTC_TAMP2_OUT |
| lptim_ext_trig5 | RTC_TAMP3_OUT |
| lptim_ext_trig6 | Reserved |
| lptim_ext_trig7 | Reserved |
The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be chosen among APB, LSI, LSE or HSI sources through the Reset and Clock controller (RCC). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1. When clocked with an external clock source, the LPTIM may run in one of these two possible configurations:
Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will use an external clock source or an internal one.
When configured to use an external clock source, the CKPOL bits are used to select the external clock signal active edge. If both edges are configured to be active ones, an internal clock signal should also be provided (first configuration). In this case, the internal clock signal frequency should be at least four times higher than the external clock signal frequency.
The LPTIM inputs, either external (mapped to microcontroller GPIOs) or internal (mapped on the chip-level to other embedded peripherals, such as embedded comparators), are protected with digital filters that prevent any glitches and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious counts or triggers.
Before activating the digital filters, an internal clock source should first be provided to the LPTIM. This is necessary to guarantee the proper operation of the filters.
The digital filters are divided into two groups:
Note: The digital filters sensitivity is controlled by groups. It is not possible to configure each digital
filter sensitivity separately inside the same group.
The filter sensitivity acts on the number of consecutive equal samples that should be detected on one of the LPTIM inputs to consider a signal level change as a valid transition. Figure 339 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed.
| (omitted) |
Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting
the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to
protect the LPTIM external inputs against glitches.
The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible division ratios:
| programming | dividing factor |
|---|---|
| 000 | /1 |
| 001 | /2 |
| 010 | /4 |
| 011 | /8 |
| 100 | /16 |
| 101 | /32 |
| 110 | /64 |
| 111 | /128 |
The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs.
TRIGEN[1:0] is used to determine the LPTIM trigger source:
When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8 trigger inputs is used to start the counter.
The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization.
If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled).
Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these
bits when the timer is disabled will be discarded by hardware.
The LPTIM features two operating modes:
One-shot mode
To enable the one-shot counting, the SNGSTRT bit must be set.
A new trigger event will re-start the timer. Any trigger event occurring after the counter starts and before the counter reaches ARR will be discarded.
In case an external trigger is selected, each external trigger event arriving after the SNGSTRT bit is set, and after the counter register has stopped (contains zero value), will start the counter for a new one-shot counting cycle as shown in Figure 340.
| (omitted) |
- Set-once mode activated:
It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set-once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 341.
| (omitted) |
In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one-shot counting.
Continous mode
To enable the continuous counting, the CNTSTRT bit must be set.
In case an external trigger is selected, an external trigger event arriving after CNTSTRT is set will start the counter for continuous counting. Any subsequent external trigger event will be discarded as shown in Figure 342.
In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for continuous counting.
| (omitted) |
SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode.
If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode. The counter (if active) will stop as soon as it reaches ARR.
If the One-shot mode was previously selected, setting CNTSTRT will switch the LPTIM to the Continuous mode. The counter (if active) will restart as soon as it reaches ARR.
The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
A low-power timeout function can be realized. The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Two 16-bit registers, the LPTIM_ARR (autoreload register) and LPTIM_CMP (Compare register), are used to generate several different waveforms on LPTIM output
The timer can generate the following waveforms:
The above described modes require that the LPTIM_ARR register value be strictly greater than the LPTIM_CMP register value.
The LPTIM output waveform can be configured through the WAVE bit as follow:
The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Figure 343 below shows the three possible waveforms that can be generated on the LPTIM output. Also, it shows the effect of the polarity change using the WAVPOL bit.
| (omitted) |
The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started.
The PRELOAD bit controls how the LPTIM_ARR and the LPTIM_CMP registers are updated:
The LPTIM APB interface and the LPTIM kernel logic use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided.
The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.
After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results.
The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter.
In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits.
The count modes below can be selected, depending on CKSEL and COUNTMODE values:
COUNTMODE = 0
The LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated following each internal clock pulse.
COUNTMODE = 1
The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM.
Consequently, in order to not miss any event, the frequency of the changes on the external Input1 signal should never exceed the frequency of the internal clock provided to the LPTIM. Also, the internal clock provided to the LPTIM must not be prescaled (PRESC[2:0] = 000).
CKSEL = 1: the LPTIM is clocked by an external clock source
COUNTMODE value is don’t care.
In this configuration, the LPTIM has no need for an internal clock source (except if the glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as system clock for the LPTIM. This configuration is suitable for operation modes where no embedded oscillator is enabled.
For this configuration, the LPTIM counter can be updated either on rising edges or falling edges of the input1 clock signal but not on both rising and falling edges.
Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM kernel logic, there is some initial latency (after the LPTIM is enabled) before the counter is incremented. More precisely, the first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost.
The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled.
The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled.
This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction). Therefore you must configure LPTIM_ARR before starting. From the two external input signals, Input1 and Input2, a clock signal is generated to clock the LPTIM counter. The phase between those two signals determines the counting direction.
The Encoder mode is only available when the LPTIM is clocked by an internal clock source. The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of the LPTIM.
Direction change is signalized by the two Down and Up flags in the LPTIM_ISR register. Also, an interrupt can be generated for both direction change events if enabled through the LPTIM_IER register.
To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in Continuous mode.
When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. Therefore, its content always represents the encoder’s position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the encoder rotor.
According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting scenarios are possible. The following table summarizes the possible combinations, assuming that Input1 and Input2 do not switch at the same time.
| Active edge |
Level on opposite signal (Input1 for Input2, Input2 for Input1) |
Input1 signal | Input2 signal |
||
|---|---|---|---|---|---|
| Rising | Falling | Rising | Falling |
||
| Rising Edge |
High | Down | No count | Up | No count |
| Low | Up | No count | Down | No count |
|
| Falling Edge |
High | No count | Up | No count | Down |
| Low | No count | Down | No count | Up |
|
| Both Edges |
High | Down | Up | Up | Down |
| Low | Up | Down | Down | Up | |
The following figure shows a counting sequence for Encoder mode where both-edge sensitivity is configured.
Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’).
| (omitted) |
The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register:
Note: If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its
corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not
asserted.
| Interrupt event | Description |
|---|---|
| Compare match | Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the Compare register (LPTIM_CMP). |
| Auto-reload match |
Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the Auto-reload register (LPTIM_ARR). |
| External trigger event | Interrupt flag is raised when an external trigger event is detected |
| Auto-reload register update OK |
Interrupt flag is raised when the write operation to the LPTIM_ARR register is complete. |
| Compare register update OK |
Interrupt flag is raised when the write operation to the LPTIM_CMP register is complete. |
| Direction change |
Used in Encoder mode. Two interrupt flags are embedded to signal direction change:
|
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWN | UP | ARROK | CMPOK | EXTTRIG | ARRM | CMPM |
| r | r | r | r | r | r | r |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | DOWN: Counter direction change up to down |
|
In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. |
|
| Bit 5 | UP: Counter direction change down to up |
|
In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. |
|
| Bit 4 | ARROK: Autoreload register update OK |
|
ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. |
|
| Bit 3 | CMPOK: Compare register update OK |
|
CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. |
|
| Bit 2 | EXTTRIG: External trigger edge event |
|
EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. |
|
| Bit 1 | ARRM: Autoreload match |
|
ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. |
|
| Bit 0 | CMPM: Compare match |
|
The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWN CF |
UPCF | ARRO KCF |
CMPO KCF |
EXTTR IGCF |
ARRM CF |
CMPM CF |
| w | w | w | w | w | w | w |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | DOWNCF: Direction change to down Clear Flag |
|
Writing 1 to this bit clear the DOWN flag in the LPT_ISR register. |
|
| Bit 5 | UPCF: Direction change to UP Clear Flag |
|
Writing 1 to this bit clear the UP flag in the LPT_ISR register. |
|
| Bit 4 | ARROKCF: Autoreload register update OK Clear Flag |
|
Writing 1 to this bit clears the ARROK flag in the LPT_ISR register |
|
| Bit 3 | CMPOKCF: Compare register update OK Clear Flag |
|
Writing 1 to this bit clears the CMPOK flag in the LPT_ISR register |
|
| Bit 2 | EXTTRIGCF: External trigger valid edge Clear Flag |
|
Writing 1 to this bit clears the EXTTRIG flag in the LPT_ISR register |
|
| Bit 1 | ARRMCF: Autoreload match Clear Flag |
|
Writing 1 to this bit clears the ARRM flag in the LPT_ISR register |
|
| Bit 0 | CMPMCF: compare match Clear Flag |
|
Writing 1 to this bit clears the CMP flag in the LPT_ISR register |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWNI E |
UPIE | ARRO KIE |
CMPO KIE |
EXTTR IGIE |
ARRMI E |
CMPMI E |
| rw | rw | rw | rw | rw | rw | rw |
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | DOWNIE: Direction change to down Interrupt Enable |
|
0: DOWN interrupt disabled |
|
| Bit 5 | UPIE: Direction change to UP Interrupt Enable |
|
0: UP interrupt disabled |
|
| Bit 4 | ARROKIE: Autoreload register update OK Interrupt Enable |
|
0: ARROK interrupt disabled |
|
| Bit 3 | CMPOKIE: Compare register update OK Interrupt Enable |
|
0: CMPOK interrupt disabled |
|
| Bit 2 | EXTTRIGIE: External trigger valid edge Interrupt Enable |
|
0: EXTTRIG interrupt disabled |
|
| Bit 1 | ARRMIE: Autoreload match Interrupt Enable |
|
0: ARRM interrupt disabled |
|
| Bit 0 | CMPMIE: Compare match Interrupt Enable |
|
0: CMPM interrupt disabled |
Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’)
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | ENC | COUNT MODE |
PRELOAD | WAVPOL | WAVE | TIMOUT | TRIGEN[1:0] | Res. |
TRIGSEL[2:0] | Res. | PRESC[2:0] | Res. | TRGFLT[1:0] | Res. | CKFLT[1:0] | CKPOL[1:0] | CKSEL |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bit 29 | Reserved, must be kept at reset value. |
| Bits 28:25 | Reserved, must be kept at reset value. |
| Bit 24 | ENC: Encoder mode enable |
|
The ENC bit controls the Encoder mode |
|
| Bit 23 | COUNTMODE: counter mode enabled |
|
The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: |
|
| Bit 22 | PRELOAD: Registers update mode |
|
The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality |
|
| Bit 21 | WAVPOL: Waveform shape polarity |
|
The WAVEPOL bit controls the output polarity |
|
| Bit 20 | WAVE: Waveform shape |
|
The WAVE bit controls the output shape |
|
| Bit 19 | TIMOUT: Timeout enable |
|
The TIMOUT bit controls the Timeout feature |
|
| Bits 18:17 | TRIGEN[1:0]: Trigger enable and polarity |
|
The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bits 15:13 | TRIGSEL[2:0]: Trigger selector |
|
The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bits 11:9 | PRESC[2:0]: Clock prescaler |
|
The PRESC bits configure the prescaler division factor. It can be one among the following division factors: |
|
| Bit 8 | Reserved, must be kept at reset value. |
| Bits 7:6 | TRGFLT[1:0]: Configurable digital filter for trigger |
|
The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bits 4:3 | CKFLT[1:0]: Configurable digital filter for external clock |
|
The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature |
|
| Bits 2:1 | CKPOL[1:0]: Clock Polarity |
|
If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set): 00: the encoder sub-mode 1 is active Refer to Section 29.4.13: Encoder mode for more details about Encoder mode sub-modes. |
|
| Bit 0 | CKSEL: Clock selector |
|
The CKSEL bit selects which clock source the LPTIM will use: The LPTIM_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’). |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT STRT |
SNG STRT |
ENA BLE |
| rw | rw | rw |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | CNTSTRT: Timer start in Continuous mode |
|
This bit is set by software and cleared by hardware. |
|
| Bit 1 | SNGSTRT: LPTIM start in Single mode |
|
This bit is set by software and cleared by hardware. |
|
| Bit 0 | ENABLE: LPTIM enable |
|
The ENABLE bit is set and cleared by software. 0:LPTIM is disabled |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CMP[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CMP[15:0]: Compare value |
|
CMP is the compare value used by the LPTIM. The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit set to ‘1’). |
Address offset: 0x18
Reset value: 0x0000 0001
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
ARR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | ARR[15:0]: Auto reload value |
|
ARR is the autoreload value for the LPTIM. The LPTIM_ARR register must only be modified when the LPTIM is enabled (ENABLE bit set to ‘1’). |
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CNT[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | CNT[15:0]: Counter value |
|
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. |
The following table summarizes the LPTIM registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
LPTIM_ISR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWN | UP | ARROK | CMPOK | EXTTRIG | ARRM | CMPM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x04 |
LPTIM_ICR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWNCF | UPCF | ARROKCF | CMPOKCF | EXTTRIGCF | ARRMCF | CMPMCF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x08 |
LPTIM_IER |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOWNIE | UPIE | ARROKIE | CMPOKIE | EXTTRIGIE | ARRMIE | CMPMIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x0C |
LPTIM_CFGR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | ENC | COUNTMODE | PRELOAD | WAVPOL | WAVE | TIMOUT | TRIGEN | Res. | TRIGSEL[2:0] | Res. | PRESC | Res. | TRGFLT | Res. | CKFLT | CKPOL | CKSEL | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x10 |
LPTIM_CR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RSTARE | Res. | CNTSTRT | SNGSTRT | ENABLE |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x14 |
LPTIM_CMP |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CMP[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x18 |
LPTIM_ARR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARR[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||||||||
| 0x1C |
LPTIM_CNT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CNT[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x20 |
LPTIM1_OR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OR_1 | OR_0 |
| Reset value | 0 | 0 | |||||||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. For further information on the window watchdog, refer to Section 31 on page
1122.
Figure 345 shows the functional blocks of the independent watchdog module.
| (omitted) |
When the independent watchdog is started by writing the value 0x0000 CCCC in the Key
register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the Key register (IWDG_KR), the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
The IWDG can also work as a window watchdog by setting the appropriate window in the Window register (IWDG_WINR).
If the reload operation is performed while the counter is greater than the value stored in the Window register (IWDG_WINR), then a reset is provided.
The default value of the Window register (IWDG_WINR) is 0x0000 0FFF, so if it is not updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset the downcounter to the Reload register (IWDG_RLR) value and ease the cycle number calculation to generate the next reload.
Configuring the IWDG when the window option is enabled
Note: Writing the window value allows to refresh the Counter value by the RLR when Status
register (IWDG_SR)
is set to 0x0000 0000.
Configuring the IWDG when the window option is disabled
When the window option it is not used, the IWDG can be configured as follows:
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register
(IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
Depending on the IWDG_STOP and IWDG_STBY options configuration, the IWDG can continue counting or not during the Stop mode and the Standby mode respectively. If the IWDG is kept running during Stop or Standby modes, it can wake up the device from this mode. Refer to Section : User and read protection option bytes for more details.
Once running, the IWDG cannot be stopped.
Write access to Prescaler register (IWDG_PR), Reload register (IWDG_RLR) and Window
register (IWDG_WINR) is protected. To modify them, the user must first write the code 0x0000 5555 in the Key register (IWDG_KR). A write access to this register with a different value will break the sequence and register access will be protected again. This is the case of the reload operation (writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on going.
When the microcontroller enters Debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module.
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
KEY[15:0] |
|||||||||||||||
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | KEY[15:0]: Key value (write only, read 0x0000) |
|
These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 30.3.6: Register access protection) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR[2:0] |
||
| rw | rw | rw |
|||||||||||||||||||||||||||||
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bits 2:0 | PR[2:0]: Prescaler divider |
|
These bits are write access protected see Section 30.3.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the Status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. 000: divider /4 Reading this register returns the prescaler value from the VDD voltage domain. This |
Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | RL[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | RL[11:0]: Watchdog counter reload value |
|
These bits are write access protected see Register access protection. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the Key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the Status register (IWDG_SR) must be reset to be able to change the reload value. Reading this register returns the reload value from the VDD voltage domain. This value |
Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WVU | RVU | PVU |
| r | r | r |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | WVU: Watchdog counter window value update |
|
This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1 |
|
| Bit 1 | RVU: Watchdog counter reload value update |
|
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. |
|
| Bit 0 | PVU: Watchdog prescaler value update |
|
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. |
Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.
Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | WIN[11:0] |
|||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | WIN[11:0]: Watchdog counter window value |
|
These bits are write access protected, see Section 30.3.6, they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the Status register (IWDG_SR) must be reset in order to be able to change the reload value. Reading this register returns the reload value from the VDD voltage domain. This value |
The following table gives the IWDG register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
IWDG_KR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | KEY[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x04 |
IWDG_PR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PR[2:0] |
||
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x08 |
IWDG_RLR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RL[11:0] |
|||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||
| 0x0C |
IWDG_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WVU | RVU | PVU |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x10 |
IWDG_WINR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WIN[11:0] |
|||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||||||||||||||||||||
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an accurate timing window.
If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value and higher than 0x3F. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 346 for the WWDG block diagram.
| (omitted) |
When the user option WWDG_SW selects “Software window watchdog”, the watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset.
When the user option WWDG_SW selects “Hardware window watchdog”, the watchdog is always enabled after a reset, it cannot be disabled.
This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 347). The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 347 describes the window watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
Use the formula in Figure 347 to calculate the WWDG timeout.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
| (omitted) |
The formula to calculate the timeout value is given by:
t
=t
× 4096× 2WDGTB[1:0] × (T[ 5:0 ] + 1 ) ( ms )WWDG PCLK
where:
tWWDG: WWDG timeout
tPCLK: APB clock period measured in ms
4096: value corresponding to internal divider
As an example, lets assume APB frequency is equal to 48 MHz, WDGTB1:0] is set to 3 and T[5:0] is set to 63:
t
=(1⁄ 48000 ) × 4096× 23 × (63+ 1 ) = 43.69msWWDG
Refer to the datasheet for the minimum and maximum values of the tWWDG.
When the microcontroller enters debug mode (processor halted), the WWDG counter either continues to work normally or stops, depending on the configuration bit in DBG module. For more details refer to Section 40.16.2: Debug support for timers, watchdog, bxCAN and I2C.
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Address offset: 0x000
Reset value: 0x0000 007F
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDGA | T[6:0] |
||||||
| rs | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | WDGA: Activation bit |
|
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled |
|
| Bits 6:0 | T[6:0]: 7-bit counter (MSB to LSB) |
|
These bits contain the value of the watchdog counter, decremented every |
Address offset: 0x004
Reset value: 0x0000 007F
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | EWI | WDGTB[1:0] | W[6:0] |
|||||||
| rs | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||
| Bits 31:10 | Reserved, must be kept at reset value. |
| Bit 9 | EWI: Early wakeup interrupt |
|
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. |
|
| Bits 8:7 | WDGTB[1:0]: Timer base |
|
The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK div 4096) div 1 |
|
| Bits 6:0 | W[6:0]: 7-bit window value |
|
These bits contain the window value to be compared with the downcounter. |
Address offset: 0x008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EWIF |
| rc_w0 |
| Bits 31:1 | Reserved, must be kept at reset value. |
| Bit 0 | EWIF: Early wakeup interrupt flag |
|
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. Writing ‘1’ has no effect. This bit is also set if the interrupt is not enabled. |
The following table gives the WWDG register map and reset values.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 |
WWDG_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDGA | T[6:0] |
||||||
| Reset value | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||||||
| 0x004 |
WWDG_CFR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EWI | WDGTB1 | WDGTB0 | W[6:0] |
||||||
| Reset value | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||||||||
| 0x008 |
WWDG_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | EWIF |
| Reset value | 0 | ||||||||||||||||||||||||||||||||
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.
After Backup domain reset, all RTC registers are protected against possible parasitic write accesses.
As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).
The RTC unit main features are the following (see Figure 348: RTC block diagram):
| (omitted) |
The RTC includes:
RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin configuration is controlled by the RTC, whatever the PC13 GPIO configuration, except for the RTC_ALARM output open-drain mode. The RTC functions mapped on PC13 are available in all low-power modes and in VBAT mode.
The output mechanism follows the priority order shown in Table 194.
| PC13 Pin configuration and function |
OSEL[1:0] bits (RTC_ALARM |
COE bit (RTC_CALIB output enable) |
RTC_ALARM _TYPE bit |
TAMP1E bit (RTC_TAMP1 input enable) |
TSE bit (RTC_TS |
TSINSEL bits |
|---|---|---|---|---|---|---|
| RTC_ALARM output OD | 01 or 10 or 11 | Don’t care | 0 | Don’t care | Don’t care | Don’t care |
| RTC_ALARM output PP | 01 or 10 or 11 | Don’t care | 1 | Don’t care | Don’t care | Don’t care |
| RTC_CALIB output PP | 00 | 1 | Don’t care | Don’t care | Don’t care | Don’t care |
| RTC_TAMP1 input floating |
00 | 0 |
Don’t care | 1 | 0 | Don’t care |
| 00 | 1 | |||||
| 01 or 10 or 11 | 0 |
|||||
| RTC_TS and RTC_TAMP1 input floating |
00 | 0 |
Don’t care | 1 | 1 | 00 |
| 00 | 1 | |||||
| 01 or 10 or 11 | 0 |
|||||
| RTC_TS input floating |
00 | 0 |
Don’t care | 0 | 1 | 00 |
| 00 | 1 | |||||
| 01 or 10 or 11 | 0 |
|||||
| Wakeup pin or Standard GPIO |
00 | 0 | Don’t care | 0 | 0 | Don’t care |
RTC_TAMP2 and RTC_TS are mapped on the same pin (PI8). PI8 configuration is controlled by the RTC, whatever the PI8 GPIO configuration. The RTC functions mapped on PI8 are available in all low-power modes and in VBAT mode.
The output mechanism follows the priority order shown in Table 195.
| PI8 pin configuration and function |
TAMP2E bit (RTC_TAMP2 input enable) |
TSE bit (RTC_TS |
TSINSEL bit (Timestamp |
|---|---|---|---|
| RTC_TAMP2 input floating | 1 | 0 | Don’t care |
| RTC_TS and RTC_TAMP2 input floating |
1 | 1 | 01 |
| RTC_TS input floating | 0 | 1 | 01 |
| Wakeup pin or Stan- dard GPIO |
0 | 0 | Don’t care |
RTC_TAMP3 and RTC_TS are mapped on the same pin (PC1). PC1 configuration is controlled by the RTC, whatever the PC1 GPIO configuration. The RTC functions mapped on PC1 are available in all low-power modes, but are not available in VBAT mode.
| PC2 pin configura- tion and function |
TAMP2E bit (RTC_TAMP3 input enable) |
TSE bit (RTC_TS |
TSINSEL bit (Timestamp |
|---|---|---|---|
| RTC_TAMP3 input floating | 1 | 0 | Don’t care |
| RTC_TS and RTC_TAMP3 input floating |
1 | 1 | 10 or 11 |
| RTC_TS input floating | 0 | 1 | 01 |
| Wakeup pin or Stan- dard GPIO |
0 | 0 | Don’t care |
RTC_REFIN is mapped on PB15. PB15 must be configured in alternate function mode to allow RTC_REFIN function. RTC_REFIN is not available in VBAT and in Standby mode.
The table below summarizes the RTC pins and functions capabilities in all modes.
| Pin | RTC functions |
Functional in all low- power modes except Standby modes |
Functional in Standby mode |
Functional in VBAT mode |
|---|---|---|---|---|
| PC13 |
RTC_TAMP1 RTC_TS RTC_OUT |
YES | YES | YES |
| PI8 |
RTC_TAMP2 RTC_TS |
YES | YES | YES |
| PC1 |
RTC_TAMP3 RTC_TS |
YES | YES | NO |
| PB15 | RTC_REFIN | YES | NO | NO |
The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 5: Reset and clock control (RCC).
A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 348: RTC block diagram):
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.
fck_apre is given by the following formula:
f
= ---------f
--R----T---C----C---L---K-
----------
CK_APRE
PREDIV_A+ 1
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
-------------------------------------f
--R----T---C----C----L--K-
--------------------------------------
The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 32.3.6: Periodic auto-wakeup for details).
The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.
Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 32.6.4: RTC initialization and status
register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK).
The shadow registers are reset by system reset.
The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is given for Alarm A, but can be translated in the same way for Alarm B.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.
Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.
Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the RTC_CR register.
The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input can be:
RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61 µs.
ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts:
The WUTF flag must then be cleared by software.
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.
The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer.
RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0.
RTC register write protection
After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in the PWR_CR1 register (refer to the power control section). DBP bit must be set in order to enable RTC registers write access.
After Backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAMPCR, RTC_BKPxR, RTC_OR and RTC_ISR[13:8].
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Calendar initialization and configuration
To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required:
When the initialization sequence is complete, the calendar starts counting.
Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its Backup domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ISR register.
Daylight saving time
The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.
Programming the alarm
A similar procedure must be followed to program or update the programmable alarms. The procedure below is given for Alarm A but can be translated in the same way for Alarm B.
Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock
cycles due to clock synchronization.
Programming the wakeup timer
The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR):
When BYPSHAD control bit is cleared in the RTC_CR register
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.
If the APB clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB clock frequency must never be lower than the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers.
The RSF bit must be cleared after wakeup and not before entering low-power mode.
After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.
After an initialization (refer to Calendar initialization and configuration on page 1137): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
After synchronization (refer to Section 32.3.10: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (STOP or Standby), since the shadow registers are not updated during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register.
Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB
cycle to complete.
The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources.
On the contrary, the following registers are reset to their default values by a Backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper configuration register (RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR), and the Option register (RTC_OR).
In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one (refer to the RTC clock section of the Reset and clock controller for details on the list of RTC clock sources not
affected by system reset). When a Backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values.
The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the asynchronous prescaler output increases, which may increase the RTC dynamic consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock. If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock.
Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed.
Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON=1.
The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the synchronous prescaler which outputs the ck_spre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values:
Note: RTC_REFIN clock detection is not available in Standby mode.
The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle:
second cycle.
Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1
causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1
causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000);
and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]
Calibration when PREDIV_A<3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz.
Verifying the RTC calibration
RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution).
In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.
Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process:
Time-stamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1.
When TSE is set:
The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a time-stamp event is detected on the RTC_TS pin.
When ITSE is set:
The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when an internal time-stamp event is detected. The internal timestamp event is generated by the switch to the VBAT supply.
When a time-stamp event occurs, due to internal or external event, the time-stamp flag bit (TSF) in RTC_ISR register is set. In case the event is internal, the ITSF flag is also set in RTC_ISR register.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp event occurs.
If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event.
Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two time-stamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.
Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the same moment, the application must not write ‘0’ into TSF bit unless it has already read it to ‘1’.
Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 32.6.16: RTC tamper configuration register
(RTC_TAMPCR).
The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering.
The tamper detection can be configured for the following purposes:
RTC backup registers
The backup registers (RTC_BKPxR) are not reset by system reset or when the device wakes up from Standby mode.
The backup registers are reset when a tamper detection event occurs (see Section 32.6.20:
RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 1144) except if the TAMPxNOERASE bit is set, or if TAMPxMF is set in the RTC_TAMPCR register.
Tamper detection initialization
Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the RTC_TAMPCR register.
Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR register.
When TAMPxMF is cleared:
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below:
A new tamper occurring on the same pin during this period and as long as TAMPxF is set cannot be detected.
When TAMPxMF is set:
A new tamper occurring on the same pin cannot be detected during the latency described above and 2.5 ck_rtc additional cycles.
By setting the TAMPIE bit in the RTC_TAMPCR register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set). Setting TAMPIE is not allowed when one or more TAMPxMF is set.
When TAMPIE is cleared, each tamper pin event interrupt can be individually enabled by setting the corresponding TAMPxIE bit in the RTC_TAMPCR register. Setting TAMPxIE is not allowed when the corresponding TAMPxMF is set.
Trigger output generation on tamper event
The tamper event detection can be used as trigger input by the low-power timers.
When TAMPxMF bit in cleared in RTC_TAMPCR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin.
When TAMPxMF bit is set, the TAMPxF flag is masked, and kept cleared in RTC_ISR register. This configuration allows to trig automatically the low-power timers in Stop mode, without requiring the system wakeup to perform the TAMPxF clearing. In this case, the backup registers are not cleared.
Timestamp on tamper event
With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time that TSF or TSOVF is set.
Edge detection on tamper inputs
If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when either a rising edge or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated when edge detection is selected.
Caution: When using the edge detection, it is recommended to check by software the tamper pin level just after enabling the tamper detection (by reading the GPIO registers), and before writing sensitive values in the backup registers, to ensure that an active edge did not occur before enabling the tamper event detection.
When TAMPFLT="00" and TAMPxTRG = 0 (rising edge detection), a tamper event may be detected by hardware if the tamper input is already at high level before enabling the tamper detection.
After a tamper event has been detected and cleared, the RTC_TAMPx should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the RTC_TAMPx input value still indicates a tamper detection. This is equivalent to a level detection on the RTC_TAMPx input.
Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting
of the backup registers, the pin to which the RTC_TAMPx is mapped should be externally
tied to the correct level.
Level detection with filtering on RTC_TAMPx inputs
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits.
The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.
When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift operation is on going and may toggle during the shift operation (SHPF=1).
Note: When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
automatically configured as output.
When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the
asynchronous prescaler.
When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the
synchronous prescaler.
The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output RTC_ALARM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_ISR register.
The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1.
Alarm output
The RTC_ALARM pin can be configured in output open drain or output push-pull using the control bit RTC_ALARM_TYPE in the RTC_OR register.
Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't
care and must be kept cleared).
When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
automatically configured as output.
| Mode | Description |
|---|---|
| Sleep | No effect RTC interrupts cause the device to exit the Sleep mode. |
| Stop |
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop mode. |
| Standby |
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Standby mode. |
All RTC interrupts are connected to the EXTI controller. Refer to Section 11: Extended
interrupts and events controller (EXTI).
To enable the RTC Alarm interrupt, the following sequence is required:
To enable the RTC Tamper interrupt, the following sequence is required:
To enable the RTC TimeStamp interrupt, the following sequence is required:
To enable the Wakeup timer interrupt, the following sequence is required:
| Interrupt event | Event flag |
Enable control bit |
Exit from Sleep mode |
Exit from Stop mode |
Exit from Standby mode |
|---|---|---|---|---|---|
| Alarm A | ALRAF | ALRAIE | yes | yes(1) |
yes(1) |
| Alarm B | ALRBF | ALRBIE | yes | yes(1) | yes(1) |
| RTC_TS input (timestamp) | TSF | TSIE | yes | yes(1) | yes(1) |
| RTC_TAMP1 input detection | TAMP1F | TAMPIE | yes | yes(1) | yes(1) |
| RTC_TAMP2 input detection | TAMP2F | TAMPIE | yes | yes(1) | yes(1) |
| RTC_TAMP3 input detection | TAMP3F | TAMPIE | yes | yes(1) | yes(1) |
| Wakeup timer interrupt | WUTF | WUTIE | yes | yes(1) | yes(1) |
Refer to Section 1.2 on page 69 of the reference manual for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by words (32-bit).
The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1137 and Reading the calendar on page 1138.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x00
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | HT[1:0] | HU[3:0] |
Res. | MNT[2:0] | MNU[3:0] | Res. | ST[2:0] | SU[3:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||
Bits 31-23 Reserved, must be kept at reset value
| Bit 22 | PM: AM/PM notation |
|
0: AM or 24-hour format |
|
| Bits 21:20 | HT[1:0]: Hour tens in BCD format |
| Bits 19:16 | HU[3:0]: Hour units in BCD format |
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:12 | MNT[2:0]: Minute tens in BCD format |
| Bits 11:8 | MNU[3:0]: Minute units in BCD format |
| Bit 7 | Reserved, must be kept at reset value. |
| Bits 6:4 | ST[2:0]: Second tens in BCD format |
| Bits 3:0 | SU[3:0]: Second units in BCD format |
The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1137 and Reading the calendar on page 1138.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x04
Backup domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | YT[3:0] | YU[3:0] |
WDU[2:0] | MT | MU[3:0] | Res. | Res. | DT[1:0] | DU[3:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:24 | Reserved, must be kept at reset value |
| Bits 23:20 | YT[3:0]: Year tens in BCD format |
| Bits 19:16 | YU[3:0]: Year units in BCD format |
| Bits 15:13 | WDU[2:0]: Week day units |
|
000: forbidden |
|
| Bit 12 | MT: Month tens in BCD format |
| Bits 11:8 | MU: Month units in BCD format |
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bits 5:4 | DT[1:0]: Date tens in BCD format |
| Bits 3:0 | DU[3:0]: Date units in BCD format |
Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | ITSE | COE | OSEL[1:0] | POL | COSEL | BKP | SUB1H | ADD1H |
TSIE | WUTIE | ALRBIE | ALRAIE | TSE | WUTE | ALRBE | ALRAE | Res. | FMT | BYPS HAD |
REFCKON | TSEDGE | WUCKSEL[2:0] |
|||
| rw | rw | rw | rw | rw | rw | rw | w | w |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | ITSE: timestamp on internal event enable |
|
0: internal event timestamp disabled |
|
| Bit 23 | COE: Calibration output enable |
|
This bit enables the RTC_CALIB output 0: Calibration output disabled |
|
| Bits 22:21 | OSEL[1:0]: Output selection |
|
These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled |
|
| Bit 20 | POL: Output polarity |
|
This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) |
|
| Bit 19 | COSEL: Calibration output selection |
|
When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz (with default prescaler setting) These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 32.3.15: Calibration clock output |
|
| Bit 18 | BKP: Backup |
|
This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. |
|
| Bit 17 | SUB1H: Subtract 1 hour (winter time change) |
|
When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect |
|
| Bit 16 | ADD1H: Add 1 hour (summer time change) |
|
When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect |
|
| Bit 15 | TSIE: Time-stamp interrupt enable |
|
0: Time-stamp Interrupt disable |
|
| Bit 14 | WUTIE: Wakeup timer interrupt enable |
|
0: Wakeup timer interrupt disabled |
|
| Bit 13 | ALRBIE: Alarm B interrupt enable |
|
0: Alarm B Interrupt disable |
|
| Bit 12 | ALRAIE: Alarm A interrupt enable |
|
0: Alarm A interrupt disabled |
|
| Bit 11 | TSE: timestamp enable |
|
0: timestamp disable |
|
| Bit 10 | WUTE: Wakeup timer enable |
|
0: Wakeup timer disabled
When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
|
|
| Bit 9 | ALRBE: Alarm B enable |
|
0: Alarm B disabled |
|
| Bit 8 | ALRAE: Alarm A enable |
|
0: Alarm A disabled |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | FMT: Hour format |
|
0: 24 hour/day format |
|
| Bit 5 | BYPSHAD: Bypass the shadow registers |
|
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. If the frequency of the APB clock is less than seven times the frequency of RTCCLK, |
|
| Bit 4 | REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) |
|
0: RTC_REFIN detection disabled
PREDIV_S must be 0x00FF.
|
|
| Bit 3 | TSEDGE: Time-stamp event active edge |
|
0: RTC_TS input rising edge generates a time-stamp event |
|
| Bits 2:0 | WUCKSEL[2:0]: Wakeup clock selection |
|
000: RTC/16 clock is selected |
Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137
.
Caution: TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF.
This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 1137.
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ITSF | RECALPF |
TAMP3F | TAMP2F | TAMP1F | TSOVF | TSF | WUTF | ALRBF | ALRAF | INIT | INITF | RSF | INITS | SHPF | WUTWF | ALRB WF |
ALRAWF |
| rc_w0 | r |
rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rc_w0 | rw | r | rc_w0 | r | r | r | r | r |
| Bits 31:18 | Reserved, must be kept at reset value |
| Bit 17 | ITSF: Internal tTime-stamp flag |
|
This flag is set by hardware when a time-stamp on the internal event occurs. |
|
| Bit 16 | RECALPF: Recalibration pending Flag |
|
The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly. |
|
| Bit 15 | TAMP3F: RTC_TAMP3 detection flag |
|
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. |
|
| Bit 14 | TAMP2F: RTC_TAMP2 detection flag |
|
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0 |
|
| Bit 13 | TAMP1F: RTC_TAMP1 detection flag |
|
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0 |
|
| Bit 12 | TSOVF: Time-stamp overflow flag |
|
This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time- |
|
| Bit 11 | TSF: Time-stamp flag |
|
This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. |
|
| Bit 10 | WUTF: Wakeup timer flag |
|
This flag is set by hardware when the wakeup auto-reload counter reaches 0. |
|
| Bit 9 | ALRBF: Alarm B flag |
|
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). |
|
| Bit 8 | ALRAF: Alarm A flag |
|
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. |
|
| Bit 7 | INIT: Initialization mode |
|
0: Free running mode |
|
| Bit 6 | INITF: Initialization flag |
|
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed |
|
| Bit 5 | RSF: Registers synchronization flag |
|
This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized |
|
| Bit 4 | INITS: Initialization status flag |
|
This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 0: Calendar has not been initialized |
|
| Bit 3 | SHPF: Shift operation pending |
|
0: No shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. |
|
| Bit 2 | WUTWF: Wakeup timer write flag |
|
This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set. 0: Wakeup timer configuration update not allowed |
|
| Bit 1 | ALRBWF: Alarm B write flag |
|
This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. |
|
| Bit 0 | ALRAWF: Alarm A write flag |
|
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed |
Note: The bits ALRAF, ALRBF, WUTF and TSF are cleared 2 APB clock cycles after programming
them to 0.
This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on
page 1137.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PREDIV_A[6:0] |
Res. | PREDIV_S[14:0] |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:23 | Reserved, must be kept at reset value |
| Bits 22:16 | PREDIV_A[6:0]: Asynchronous prescaler factor |
|
This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:0 | PREDIV_S[14:0]: Synchronous prescaler factor |
|
This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) |
This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
WUT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bits 15:0 | WUT[15:0]: Wakeup auto-reload value bits |
|
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register |
This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x1C
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK4 | WDSEL | DT[1:0] | DU[3:0] | MSK3 | PM | HT[1:0] | HU[3:0] |
MSK2 | MNT[2:0] | MNU[3:0] | MSK1 | ST[2:0] | SU[3:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | MSK4: Alarm A date mask |
|
0: Alarm A set if the date/day match |
|
| Bit 30 | WDSEL: Week day selection |
|
0: DU[3:0] represents the date units |
|
| Bits 29:28 | DT[1:0]: Date tens in BCD format. |
| Bits 27:24 | DU[3:0]: Date units or day in BCD format. |
| Bit 23 | MSK3: Alarm A hours mask |
|
0: Alarm A set if the hours match |
|
| Bit 22 | PM: AM/PM notation |
|
0: AM or 24-hour format |
|
| Bits 21:20 | HT[1:0]: Hour tens in BCD format. |
| Bits 19:16 | HU[3:0]: Hour units in BCD format. |
| Bit 15 | MSK2: Alarm A minutes mask |
|
0: Alarm A set if the minutes match |
|
| Bits 14:12 | MNT[2:0]: Minute tens in BCD format. |
| Bits 11:8 | MNU[3:0]: Minute units in BCD format. |
| Bit 7 | MSK1: Alarm A seconds mask |
|
0: Alarm A set if the seconds match |
|
| Bits 6:4 | ST[2:0]: Second tens in BCD format. |
| Bits 3:0 | SU[3:0]: Second units in BCD format. |
This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x20
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSK4 | WDSEL | DT[1:0] | DU[3:0] | MSK3 | PM | HT[1:0] | HU[3:0] |
MSK2 | MNT[2:0] | MNU[3:0] | MSK1 | ST[2:0] | SU[3:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | MSK4: Alarm B date mask |
|
0: Alarm B set if the date and day match |
|
| Bit 30 | WDSEL: Week day selection |
|
0: DU[3:0] represents the date units |
|
| Bits 29:28 | DT[1:0]: Date tens in BCD format |
| Bits 27:24 | DU[3:0]: Date units or day in BCD format |
| Bit 23 | MSK3: Alarm B hours mask |
|
0: Alarm B set if the hours match |
|
| Bit 22 | PM: AM/PM notation |
|
0: AM or 24-hour format |
|
| Bits 21:20 | HT[1:0]: Hour tens in BCD format |
| Bits 19:16 | HU[3:0]: Hour units in BCD format |
| Bit 15 | MSK2: Alarm B minutes mask |
|
0: Alarm B set if the minutes match |
|
| Bits 14:12 | MNT[2:0]: Minute tens in BCD format |
| Bits 11:8 | MNU[3:0]: Minute units in BCD format |
| Bit 7 | MSK1: Alarm B seconds mask |
|
0: Alarm B set if the seconds match |
|
| Bits 6:4 | ST[2:0]: Second tens in BCD format |
| Bits 3:0 | SU[3:0]: Second units in BCD format |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | KEY |
|||||||
| w | w | w | w | w | w | w | w |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | KEY: Write protection key |
|
This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. |
Address offset: 0x28
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
SS[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bits 15:0 | SS: Sub second value |
|
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) SS can be larger than PREDIV_S only after a shift operation. In that case, the correct |
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADD1S | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | SUBFS[14:0] |
||||||||||||||
| w |
w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
||||||||||||||||
| Bit 31 | ADD1S: Add one second |
|
0: No effect This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. |
|
| Bits 30:15 | Reserved, must be kept at reset value |
| Bits 14:0 | SUBFS: Subtract a fraction of a second |
|
These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be |
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | HT[1:0] | HU[3:0] |
Res. | MNT[2:0] | MNU[3:0] | Res. | ST[2:0] | SU[3:0] |
||||||||||||||
| r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r |
|||||||||||
| Bits 31:23 | Reserved, must be kept at reset value |
| Bit 22 | PM: AM/PM notation |
|
0: AM or 24-hour format |
|
| Bits 21:20 | HT[1:0]: Hour tens in BCD format. |
| Bits 19:16 | HU[3:0]: Hour units in BCD format. |
| Bit 15 | Reserved, must be kept at reset value |
| Bits 14:12 | MNT[2:0]: Minute tens in BCD format. |
| Bits 11:8 | MNU[3:0]: Minute units in BCD format. |
| Bit 7 | Reserved, must be kept at reset value |
| Bits 6:4 | ST[2:0]: Second tens in BCD format. |
| Bits 3:0 | SU[3:0]: Second units in BCD format. |
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
WDU[1:0] | MT | MU[3:0] | Res. | Res. | DT[1:0] | DU[3:0] |
|||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bits 15:13 | WDU[1:0]: Week day units |
| Bit 12 | MT: Month tens in BCD format |
| Bits 11:8 | MU[3:0]: Month units in BCD format |
| Bits 7:6 | Reserved, must be kept at reset value |
| Bits 5:4 | DT[1:0]: Date tens in BCD format |
| Bits 3:0 | DU[3:0]: Date units in BCD format |
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
SS[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bits 15:0 | SS: Sub second value |
|
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. |
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137.
Address offset: 0x3C
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
CALP | CALW8 | CALW 16 |
Res. | Res. | Res. | Res. | CALM[8:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value |
| Bit 15 | CALP: Increase frequency of RTC by 488.5 ppm |
|
0: No RTCCLK pulses are added. This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section 32.3.12: RTC smooth digital calibration. |
|
| Bit 14 | CALW8: Use an 8-second calibration cycle period |
|
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 32.3.12: RTC smooth
|
|
| Bit 13 | CALW16: Use a 16-second calibration cycle period |
|
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1.
CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 32.3.12: RTC smooth
|
|
| Bits 12:9 | Reserved, must be kept at reset value |
| Bits 8:0 | CALM[8:0]: Calibration minus |
|
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 32.3.12: RTC smooth digital calibration on page 1141. |
Address offset: 0x40
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TAMP3 MF |
TAMP3 NO ERASE |
TAMP3 IE |
TAMP2 MF |
TAMP2 NO ERASE |
TAMP2 IE |
TAMP1 MF |
TAMP1 NO ERASE |
TAMP1 IE |
TAMP PUDIS |
TAMPPRCH [1:0] |
TAMPFLT[1:0] | TAMPFREQ[2:0] | TAMP TS |
TAMP3 TRG |
TAMP3 E |
TAMP2 TRG |
TAMP2 E |
TAMPI E |
TAMP1 TRG |
TAMP1 E |
||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | TAMP3MF: Tamper 3 mask flag |
|
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection.
The Tamper 3 interrupt must not be enabled when TAMP3MF is set.
|
|
| Bit 23 | TAMP3NOERASE: Tamper 3 no erase |
|
0: Tamper 3 event erases the backup registers. |
|
| Bit 22 | TAMP3IE: Tamper 3 interrupt enable |
|
0: Tamper 3 interrupt is disabled if TAMPIE = 0. |
|
| Bit 21 | TAMP2MF: Tamper 2 mask flag |
|
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection.
The Tamper 2 interrupt must not be enabled when TAMP2MF is set.
|
|
| Bit 20 | TAMP2NOERASE: Tamper 2 no erase |
|
0: Tamper 2 event erases the backup registers. |
|
| Bit 19 | TAMP2IE: Tamper 2 interrupt enable |
|
0: Tamper 2 interrupt is disabled if TAMPIE = 0. |
|
| Bit 18 | TAMP1MF: Tamper 1 mask flag |
|
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. The Tamper 1 interrupt must not be enabled when TAMP1MF is set. |
|
| Bit 17 | TAMP1NOERASE: Tamper 1 no erase |
|
0: Tamper 1 event erases the backup registers. |
|
| Bit 16 | TAMP1IE: Tamper 1 interrupt enable |
|
0: Tamper 1 interrupt is disabled if TAMPIE = 0. 1: Tamper 1 interrupt enabled. |
|
| Bit 15 | TAMPPUDIS: RTC_TAMPx pull-up disable |
|
This bit determines if each of the RTC_TAMPx pins are precharged before each sample. 0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) |
|
| Bits 14:13 | TAMPPRCH[1:0]: RTC_TAMPx precharge duration |
|
These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle |
|
| Bits 12:11 | TAMPFLT[1:0]: RTC_TAMPx filter count |
|
These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). |
|
| Bits 10:8 | TAMPFREQ[2:0]: Tamper sampling frequency |
|
Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) |
|
| Bit 7 | TAMPTS: Activate timestamp on tamper detection event |
|
0: Tamper detection event does not cause a timestamp to be saved TAMPTS is valid even if TSE=0 in the RTC_CR register. |
|
| Bit 6 | TAMP3TRG: Active level for RTC_TAMP3 input |
|
if TAMPFLT ≠ 00: |
Note: The Tamper 3 falling edge detection is not allowed when switch to VBAT is used,
otherwise a detection would always occurs when entering in Vbat mode.
| Bit 5 | TAMP3E: RTC_TAMP3 detection enable |
|
0: RTC_TAMP3 input detection disabled |
|
| Bit 4 | TAMP2TRG: Active level for RTC_TAMP2 input |
|
if TAMPFLT != 00: |
|
| Bit 3 | TAMP2E: RTC_TAMP2 input detection enable |
|
0: RTC_TAMP2 detection disabled |
|
| Bit 2 | TAMPIE: Tamper interrupt enable |
|
0: Tamper interrupt disabled This bit enables the interrupt for all tamper pins events, whatever TAMPxIE level. If this |
|
| Bit 1 | TAMP1TRG: Active level for RTC_TAMP1 input |
|
If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP1 input rising edge triggers a tamper detection event. |
|
| Bit 0 | TAMP1E: RTC_TAMP1 input detection enable |
|
0: RTC_TAMP1 detection disabled |
Caution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid spuriously setting TAMPxF.
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1137
Address offset: 0x44
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | MASKSS[3:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | SS[14:0] |
|||||||||||||||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w | rw | rw |
|||||||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:24 | MASKSS[3:0]: Mask the most-significant bits starting at this bit |
|
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). |
|
| Bits 23:15 | Reserved, must be kept at reset value. |
| Bits 14:0 | SS[14:0]: Sub seconds value |
|
This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. |
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
This register is write protected.The write access procedure is described in Section : RTC
register write protection.
Address offset: 0x48
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | MASKSS[3:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | SS[14:0] |
|||||||||||||||||
| rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w | rw | rw |
|||||||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:24 | MASKSS[3:0]: Mask the most-significant bits starting at this bit |
|
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). |
|
| Bits 23:15 | Reserved, must be kept at reset value. |
| Bits 14:0 | SS[14:0]: Sub seconds value |
|
This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. |
Address offset: 0x4C
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
RTC_ ALARM _TYPE |
TSINSEL[1:0] | Res. |
|
| rw | rw | rw |
|||||||||||||||||||||||||||||
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bit 3 | RTC_ALARM_TYPE: RTC_ALARM on PC13 output type |
|
0: RTC_ALARM, when mapped on PC13, is open-drain output |
|
| Bits 2:1 | TSINSEL[1:0]: TIMESTAMP mapping |
|
00: TIMESTAMP is mapped on PC13 |
|
| Bit 0 | Reserved, must be kept at reset value. |
Address offset: 0x50 to 0xCC
Backup domain reset value: 0x0000 0000
System reset: not affected
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BKP[31:16] |
BKP[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w | rw | rw |
| Bits 31:0 | BKP[31:0] |
|
The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. |
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
RTC_TR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | HT[1:0] | HU[3:0] |
Res. | MNT[2:0] | MNU[3:0] |
Res. | ST[2:0] | SU[3:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x04 |
RTC_DR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | YT[3:0] | YU[3:0] | WDU[2:0] |
MT | MU[3:0] |
Res. | Res. | DT[1:0] | DU[3:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
|||||||||||
| 0x08 |
RTC_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | ITSE | COE | OSEL[1:0] | POL | COSEL | BKP | SUB1H | ADD1H | TSIE | WUTIE | ALRBIE | ALRAIE | TSE | WUTE | ALRBE | ALRAE | Res. | FMT | BYPSHAD | REFCKON | TSEDGE | WUCKSEL[2:0] | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x0C |
RTC_ISR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ITSF | RECALPF | TAMP3F | .TAMP2F | TAMP1F | TSOVF | TSF | WUTF | ALRBF | ALRAF | INIT | INITF | RSF | INITS | SHPF | WUT WF | ALRBWF | ALRAWF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
||||||||||||||||
| 0x10 |
RTC_PRER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PREDIV_A[6:0] | PREDIV_S[14:0] |
|||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
||||||||||
| 0x14 |
RTC_WUTR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WUT[15:0] |
|||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||||||||||
| 0x1C |
RTC_ALRMAR
|
MSK4 | WDSEL | DT[1:0] | DU[3:0] |
MSK3 | PM | HT[1:0] | HU[3:0] |
MSK2 | MNT[2:0] | MNU[3:0] |
MSK1 | ST[2:0] | SU[3:0] |
||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x20 |
RTC_ALRMBR
|
MSK4 | WDSEL | DT[1:0] | DU[3:0] |
MSK3 | PM | HT[1:0] | HU[3:0] |
MSK2 | MNT[2:0] | MNU[3:0] |
MSK2 | ST[2:0] | SU[3:0] |
||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x24 |
RTC_WPR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | KEY |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x28 |
RTC_SSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SS[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x2C |
RTC_SHIFTR
|
ADD1S | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SUBFS[14:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x30 |
RTC_TSTR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PM | HT[1:0] | HU[3:0] |
Res. | MNT[2:0] | MNU[3:0] |
Res. | ST[2:0] | SU[3:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||
| 0x34 |
RTC_TSDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WDU[1:0] |
MT | MU[3:0] |
Res. | Res. | DT[1:0] | DU[3:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x38 |
RTC_TSSSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SS[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x3C |
RTC_ CALR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CALP | CALW8 | CALW16 | Res. | Res. | Res. | Res. | CALM[8:0] |
||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x40 |
RTC_TAMPCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TAMP3MF | TAMP3NOERASE | TAMP3IE | TAMP2MF | TAMP2NOERASE | TAMP2IE | TAMP1MF | TAMP1NOERASE | TAMP1IE | TAMPPUDIS | TAMPPRCH[1:0] | TAMPFLT[1:0] | TAMPFREQ[2:0] | TAMPTS | TAMP3TRG | TAMP3E | TAMP2TRG | .TAMP2E | .TAMPIE | TAMP1TRG | TAMP1E | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x44 |
RTC_ ALRMASSR |
Res. | Res. | Res. | Res. | MASKSS [3:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SS[14:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x48 |
RTC_ ALRMBSSR |
Res. | Res. | Res. | Res. | MASKSS [3:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SS[14:0] |
|||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x4C |
RTC_ OR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RTC_ALARM_TYPE | TSINSEL[1:0] | Res. | |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x50 to 0xCC |
RTC_BKP0R | BKP[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| to RTC_BKP31R | BKP[31:0] |
||||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus (power management bus) compatible.
DMA can be used to reduce CPU overload.
The following additional features are also available depending on the product implementation (see Section 33.3: I2C implementation):
This manual describes the full set of features implemented in I2C1, I2C2, I2C3 and I2C4. I2C1, I2C2, I2C3 and I2C4are identical and implement the full set of features as shown in the following table.
| I2C features(1) | I2C1 | I2C2 | I2C3 | I2C4 |
|---|---|---|---|---|
| 7-bit addressing mode | X | X | X | X |
| 10-bit addressing mode | X | X | X | X |
| Standard-mode (up to 100 kbit/s) | X | X | X | X |
| Fast-mode (up to 400 kbit/s) | X | X | X | X |
| Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) | X | X | X | X |
| Independent clock | X | X | X | X |
| Wakeup from Stop mode | - | - | - | - |
| SMBus/PMBus | X | X | X | X |
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to 1 MHz) I2C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL).
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available.
The block diagram of the I2C interface is shown in Figure 349.
| (omitted) |
The I2C is clocked by an independent clock source which allows to the I2C to operate independently from the PCLK frequency.
This independent clock source can be selected from the following three clock sources:
Refer to Section 5: Reset and clock control (RCC) for more details.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 33.3: I2C implementation.
The I2C kernel is clocked by I2CCLK.
The I2CCLK period tI2CCLK must respect the following conditions:
tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH
with:
tLOW: SCL low time and tHIGH: SCL high time
tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK.
The PCLK clock period tPCLK must respect the following condition:
tPCLK < 4/3 tSCL
with tSCL: SCL period
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for tI2CCLK.
The interface can operate in one of the four following modes:
By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a START condition and ends with a STOP condition. Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection can be enabled or disabled by software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to the following figure.
| (omitted) |
Acknowledge can be enabled or disabled by software. The I2C interface addresses can be selected by software.
Enabling and disabling the peripheral
The I2C peripheral clock must be configured and enabled in the clock controller (refer to Section 5: Reset and clock control (RCC)).
Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register.
When the I2C is disabled (PE=0), the I2C performs a software reset. Refer to Section 33.4.5: Software reset for more details.
Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must configure the noise filters, if needed. By default, an analog noise filter is present on the SDA and SCL inputs. This analog filter is compliant with the I2C specification which requires the suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods. This allows to suppress spikes with a programmable length of 1 to 15 I2CCLK periods.
| - | Analog filter | Digital filter |
|---|---|---|
| Pulse width of suppressed spikes | ≥ 50 ns | Programmable length from 1 to 15 I2C peripheral clocks |
| Benefits | Available in Stop mode |
|
| Drawbacks | Variation vs. temperature, voltage, process |
Wakeup from Stop mode on address match is not available when digital filter is enabled |
Caution: Changing the filter configuration is not allowed when the I2C is enabled.
I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window
| (omitted) |
When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1) x tI2CCLK.
TSDADEL impacts the hold time tHD;DAT.
The total SDA output delay is:
tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK }
tSYNC1 duration depends on these parameters:
In order to bridge the undefined region of the SCL falling edge, the user must program SDADEL in such a way that:
{tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL
SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }
Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to
device datasheet for tAF values.
The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation becomes:
SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }.
Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to Table 203: I2C-SMBUS specification data setup and hold times for tf
, tr, tHD;DAT and tVD;DAT standard values.
After tSDADEL delay, or after sending SDA output in case the slave had to stretch the clock because the data was not yet written in I2C_TXDR register, SCL line is kept at low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK.
tSCLDEL impacts the setup time tSU;DAT .
In order to bridge the undefined region of the SDA transition (rising edge usually worst case), the user must program SCLDEL in such a way that:
{[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL
Refer to Table 203: I2C-SMBUS specification data setup and hold times for tr and tSU;DAT standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application.
Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK, in both transmission
and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR
when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data
is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH=1 in slave mode, the SCL is not stretched. Consequently the SDADEL must be programmed in such a way to guarantee also a sufficient setup time.
| Symbol | Parameter |
Standard-mode (Sm) |
Fast-mode (Fm) |
Fast-mode Plus (Fm+) | SMBUS |
Unit |
||||
|---|---|---|---|---|---|---|---|---|---|---|
| Min. | Max | Min. | Max | Min. | Max | Min. | Max |
|||
| tHD;DAT | Data hold time | 0 | - | 0 | - | 0 | - | 0.3 | - |
µs |
| tVD;DAT | Data valid time | - | 3.45 | - | 0.9 | - | 0.45 | - | - |
|
| tSU;DAT | Data setup time | 250 | - | 100 | - | 50 | - | 250 | - |
ns |
|
tr
|
Rise time of both SDA and SCL signals |
- | 1000 | - | 300 | - | 120 | - | 1000 |
|
|
tf
|
Fall time of both SDA and SCL signals |
- | 300 | - | 300 | - | 120 | - | 300 | |
Additionally, in master mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.
When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK.
tSCLL impacts the SCL low time tLOW .
Refer to I2C master initialization for more details.
Caution: Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral. Refer to I2C slave initialization for more details.
Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.
| (omitted) |
A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value. The configuration registers are not impacted.
Here is the list of impacted register bits:
and in addition when the SMBus feature is supported:
PE must be kept low during at least 3 APB clock cycles in order to perform the software reset. This is ensured by writing the following software sequence: - Write PE=0 - Check PE=0 - Write PE=1.
The data transfer is managed through transmit and receive data registers and a shift register.
Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th SCL pulse (before the Acknowledge pulse).
| (omitted) |
Transmission
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written. The stretch is done after the 9th SCL pulse.
| (omitted) |
Hardware transfer management
The I2C has a byte counter embedded in hardware in order to manage byte transfer and to close the communication in various modes such as:
The byte counter is always used in master mode. By default it is disabled in slave mode, but it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2 register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or if a receiver wants to control the acknowledge value of a received data byte, the reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode, TCR flag is set when the number of bytes programmed in NBYTES has been transferred, and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be cleared.
When RELOAD=0 in master mode, the counter can be used in 2 modes:
Caution: The AUTOEND bit has no effect when the RELOAD bit is set.
| Function | SBC bit | RELOAD bit | AUTOEND bit |
|---|---|---|---|
| Master Tx/Rx NBYTES + STOP | x | 0 | 1 |
| Master Tx/Rx + NBYTES + RESTART | x | 0 | 0 |
|
Slave Tx/Rx all received bytes ACKed |
0 | x | x |
| Slave Rx with ACK control | 1 | 1 | x |
I2C slave initialization
In order to work in slave mode, the user must enable at least one slave address. Two registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own addresses OA1 and OA2.
OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by setting the OA1MODE bit in the I2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.
If additional slave addresses are required, the 2nd slave address OA2 can be configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received address. As soon as OA2MSK is not equal to 0, the address comparator for OA2 excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with OA2MSK=0.
OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.
When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an interrupt is generated if the ADDRIE bit is set.
By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register.
After receiving an ADDR interrupt, if several addresses are enabled the user must read the ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR flag must also be checked in order to know the transfer direction.
Slave clock stretching (NOSTRETCH = 0)
In default mode, the I2C slave stretches the SCL clock in the following situations:
Slave without clock stretching (NOSTRETCH = 1)
When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL signal.
Slave Byte Control mode
In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.
Reload mode must be selected in order to allow byte ACK control in slave reception mode (RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL pulses. The user can read the data from the I2C_RXDR register, and then decide to acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is released by programming NBYTES to a non-zero value: the acknowledge or not-acknowledge is sent and next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is continuous during NBYTES data reception.
Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not
addressed, or when ADDR=1.
The RELOAD bit value can be changed when ADDR=1, or when TCR=1.
Caution: Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when NOSTRETCH=1 is not allowed.
| (omitted) |
Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.
The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is received (ADDR=1), the user can choose either to send the content of the I2C_TXDR register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in order to program a new data byte.
In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case, the number of TXIS events during the transfer corresponds to the value programmed in NBYTES.
Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to program the first data byte. The first data byte to be sent must be previously programmed in the I2C_TXDR register:
If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by setting the TXE bit in order to program a new data byte. The STOPF bit must be cleared only after these actions, in order to guarantee that they are executed before the first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error will be generated (the OVR flag is set).
If a TXIS event is needed, (Transmit Interrupt or Transmit DMA request), the user must set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.
| (omitted) |
| (omitted) |
| (omitted) |
Slave receiver
RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.
When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.
| (omitted) |
| (omitted) |
| (omitted) |
I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master environment and slave clock stretching.
In order to allow clock synchronization:
The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK clock. The I2C releases SCL to high level once the SCLL counter reaches the value programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.
The I2C detects its own SCL high level after a tSYNC2 delay depending on the SCL rising edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock. The I2C ties SCL to low level once the SCLH counter is reached reaches the value programmed in the SCLH[7:0] bits in the I2C_TIMINGR register.
Consequently the master clock period is:
tSCL = tSYNC1 + tSYNC2 + {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x tI2CCLK}
The duration of tSYNC1 depends on these parameters:
The duration of tSYNC2 depends on these parameters:
| (omitted) |
Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given below:
| Symbol | Parameter |
Standard- mode (Sm) |
Fast-mode (Fm) |
Fast-mode Plus (Fm+) | SMBUS |
Unit |
||||
|---|---|---|---|---|---|---|---|---|---|---|
| Min | Max | Min | Max | Min | Max | Min | Max |
|||
| fSCL | SCL clock frequency | - | 100 | - | 400 | - | 1000 | - | 100 | kHz |
| tHD:STA | Hold time (repeated) START condition | 4.0 | - | 0.6 | - | 0.26 | - | 4.0 | - | µs |
| tSU:STA | Set-up time for a repeated START condition | 4.7 | - | 0.6 | - | 0.26 | - | 4.7 | - | µs |
| tSU:STO | Set-up time for STOP condition | 4.0 | - | 0.6 | - | 0.26 | - | 4.0 | - | µs |
| tBUF |
Bus free time between a STOP and START condition | 4.7 | - | 1.3 | - | 0.5 | - | 4.7 | - | µs |
| tLOW | Low period of the SCL clock | 4.7 | - | 1.3 | - | 0.5 | - | 4.7 | - | µs |
| tHIGH | Period of the SCL clock | 4.0 | - | 0.6 | - | 0.26 | - | 4.0 | 50 | µs |
| tr | Rise time of both SDA and SCL signals | - | 1000 | - | 300 | - | 120 | - | 1000 | ns |
| tf | Fall time of both SDA and SCL signals | - | 300 | - | 300 | - | 120 | - | 300 | ns |
Note: SCLL is also used to generate the tBUF and tSU:STA timings.
SCLH is also used to generate the tHD:STA and tSU:STO timings.
Refer to Section 33.4.9: I2C_TIMINGR register configuration examples for examples of I2C_TIMINGR settings vs. I2CCLK frequency.
Master communication initialization (address phase)
In order to initiate the communication, the user must program the following parameters for the addressed slave in the I2C_CR2 register:
The user must then set the START bit in I2C_CR2 register. Changing all the above bits is not allowed when START bit is set.
Then the master automatically sends the START condition followed by the slave address as soon as it detects that the bus is free (BUSY = 0) and after a delay of tBUF.
In case of an arbitration loss, the master automatically switches back to slave mode and can acknowledge its own address if it is addressed as a slave.
Note: The START bit is reset by hardware when the slave address has been sent on the bus,
whatever the received acknowledge value. The START bit is also reset by hardware if an
arbitration loss occurs.
In 10-bit addressing mode, when the Slave Address first 7 bits is NACKed by the slave, the
master will re-launch automatically the slave address transmission until ACK is received. In
this case ADDRCF must be set if a NACK is received from the slave, in order to stop
sending the slave address.
If the I2C is addressed as a slave (ADDR=1) while the START bit is set, the I2C switches to
slave mode and the START bit is cleared when the ADDRCF bit is set.
Note: The same procedure is applied for a Repeated Start condition. In this case BUSY=1.
| (omitted) |
Initialization of a master receiver addressing a 10-bit address slave
| (omitted) |
| (omitted) |
Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the I2C_CR1 register. The flag is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
In software end mode (AUTOEND=0), the TC flag is set and the SCL line is stretched low in order to perform software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2 register with the proper slave address configuration, and number of bytes to be transferred. Setting the START bit clears the TC flag and the START condition is sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2 register. Setting the STOP bit clears the TC flag and the STOP condition is sent on the bus.
| (omitted) |
| (omitted) |
| (omitted) |
Master receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register. The flag is cleared when I2C_RXDR is read.
If the total number of data bytes to be received is greater than 255, reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched low until NBYTES[7:0] is written to a non-zero value.
In software end mode (AUTOEND=0), a NACK is automatically sent after the last received byte, the TC flag is set and the SCL line is stretched low in order to allow software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2 register with the proper slave address configuration, and number of bytes to be transferred. Setting the START bit clears the TC flag and the START condition, followed by slave address, are sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2 register. Setting the STOP bit clears the TC flag and the STOP condition is sent on the bus.
| (omitted) |
| (omitted) |
| (omitted) |
The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I2C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) should be used.
| Parameter |
Standard-mode (Sm) | Fast-mode (Fm) | Fast-mode Plus (Fm+) |
|
|---|---|---|---|---|
| 10 kHz | 100 kHz | 400 kHz | 500 kHz |
|
| PRESC | 1 | 1 | 0 | 0 |
| SCLL | 0xC7 | 0x13 | 0x9 | 0x6 |
| tSCLL | 200x250 ns = 50 µs | 20x250 ns = 5.0 µs | 10x125 ns = 1250 ns | 7x125 ns = 875 ns |
| SCLH | 0xC3 | 0xF | 0x3 | 0x3 |
| tSCLH | 196x250 ns = 49 µs | 16x250 ns = 4.0µs | 4x125ns = 500ns | 4x125 ns = 500 ns |
| tSCL(1) | ~100 µs(2) | ~10 µs(2) | ~2500 ns(3) | ~2000 ns(4) |
| SDADEL | 0x2 | 0x2 | 0x1 | 0x0 |
| tSDADEL | 2x250 ns = 500 ns | 2x250 ns = 500 ns | 1x125 ns = 125 ns | 0 ns |
| SCLDEL | 0x4 | 0x4 | 0x3 | 0x1 |
| tSCLDEL | 5x250 ns = 1250 ns | 5x250 ns = 1250 ns | 4x125 ns = 500 ns | 2x125 ns = 250 ns |
| Parameter |
Standard-mode (Sm) | Fast-mode (Fm) | Fast-mode Plus (Fm+) |
|
|---|---|---|---|---|
| 10 kHz | 100 kHz | 400 kHz | 1000 kHz |
|
| PRESC | 3 | 3 | 1 | 0 |
| SCLL | 0xC7 | 0x13 | 0x9 | 0x4 |
| tSCLL | 200 x 250 ns = 50 µs | 20 x 250 ns = 5.0 µs | 10 x 125 ns = 1250 ns | 5 x 62.5 ns = 312.5 ns |
| SCLH | 0xC3 | 0xF | 0x3 | 0x2 |
| tSCLH | 196 x 250 ns = 49 µs | 16 x 250 ns = 4.0 µs | 4 x 125ns = 500 ns | 3 x 62.5 ns = 187.5 ns |
| tSCL(1) | ~100 µs(2) | ~10 µs(2) | ~2500 ns(3) | ~1000 ns(4) |
| SDADEL | 0x2 | 0x2 | 0x2 | 0x0 |
| tSDADEL | 2 x 250 ns = 500 ns | 2 x 250 ns = 500 ns | 2 x 125 ns = 250 ns | 0 ns |
| SCLDEL | 0x4 | 0x4 | 0x3 | 0x2 |
| tSCLDEL | 5 x 250 ns = 1250 ns | 5 x 250 ns = 1250 ns | 4 x 125 ns = 500 ns | 3 x 62.5 ns = 187.5 ns |
| Parameter |
Standard-mode (Sm) | Fast-mode (Fm) | Fast-mode Plus (Fm+) |
|
|---|---|---|---|---|
| 10 kHz | 100 kHz | 400 kHz | 1000 kHz |
|
| PRESC | 0xB | 0xB | 5 | 5 |
| SCLL | 0xC7 | 0x13 | 0x9 | 0x3 |
| tSCLL | 200 x 250 ns = 50 µs | 20 x 250 ns = 5.0 µs | 10 x 125 ns = 1250 ns | 4 x 125 ns = 500 ns |
| SCLH | 0xC3 | 0xF | 0x3 | 0x1 |
| tSCLH | 196 x 250 ns = 49 µs | 16 x 250 ns = 4.0 µs | 4 x 125 ns = 500 ns | 2 x 125 ns = 250 ns |
| tSCL(1) | ~100 µs(2) | ~10 µs(2) | ~2500 ns(3) | ~875 ns(4) |
| SDADEL | 0x2 | 0x2 | 0x3 | 0x0 |
| tSDADEL | 2 x 250 ns = 500 ns | 2 x 250 ns = 500 ns | 3 x 125 ns = 375 ns | 0 ns |
| SCLDEL | 0x4 | 0x4 | 0x3 | 0x1 |
| tSCLDEL | 5 x 250 ns = 1250 ns | 5 x 250 ns = 1250 ns | 4 x 125 ns = 500 ns | 2 x 125 ns = 250 ns |
This section is relevant only when SMBus feature is supported. Refer to Section 33.3: I2C
implementation.
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I2C principles of operation. SMBus provides a control bus for system and power management related tasks.
This peripheral is compatible with the SMBUS specification (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
This peripheral can be configured as master or slave device, and also as a host.
Bus protocols
There are eleven possible command protocols for any given device. A device may use any or all of the eleven protocols to communicate. The protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read Process Call. These protocols should be implemented by the user software.
For more details of these protocols, refer to SMBus specification (http://smbus.org).
Address resolution protocol (ARP)
SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device. In order to provide a mechanism to isolate each device for the purpose of address assignment each device must implement a unique device identifier (UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device Default Address (0b1100 001) is enabled by setting SMBDEN bit in I2C_CR1 register. The ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus Address Resolution Protocol, refer to SMBus specification (http://smbus.org).
Received Command and Data acknowledge control
A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2C_CR1 register. Refer to Slave Byte Control mode on page 1187 for more details.
Host Notify protocol
This peripheral supports the Host Notify protocol by setting the SMBHEN bit in the I2C_CR1 register. In this case the host will acknowledge the SMBus Host address (0b0001 000).
When this protocol is used, the device acts as a master and the host as a slave.
SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host through the SMBALERT# pin that it wants to talk. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through the Alert Response Address (0b0001 100). Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response Address.
When configured as a slave device(SMBHEN=0), the SMBA pin is pulled low by setting the ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same time.
When configured as a host (SMBHEN=1), the ALERT flag is set in the I2C_ISR register when a falling edge is detected on the SMBA pin and ALERTEN=1. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN=0, the ALERT line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN=0.
Packet error checking
A packet error checking mechanism has been introduced in the SMBus specification to improve reliability and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code (PEC) at the end of each message transfer. The PEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial on all the message bytes (including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows to send a Not Acknowledge automatically when the received byte does not match with the hardware calculated PEC.
Timeouts
This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification.
| Symbol | Parameter |
Limits |
Unit |
|
|---|---|---|---|---|
| Min | Max |
|||
| tTIMEOUT | Detect clock low timeout | 25 | 35 | ms |
| tLOW:SEXT(1) |
Cumulative clock low extend time (slave device) | - | 25 | ms |
| tLOW:MEXT(2) |
Cumulative clock low extend time (master device) | - | 10 | ms |
| (omitted) |
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have been high for tIDLE greater than tHIGH,MAX. (refer to Table 203: I2C-SMBUS specification data
setup and hold times)
This timing parameter covers the condition where a master has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the master must wait long enough to ensure that a transfer is not currently in progress. The peripheral supports a hardware bus idle detection.
This section is relevant only when SMBus feature is supported. Refer to Section 33.3: I2C
implementation.
In addition to I2C initialization, some other specific initialization must be done in order to perform SMBus communication:
Received Command and Data Acknowledge control (Slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow ACK control in slave mode, the Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. Refer to Slave Byte Control mode on page 1187 for more details.
Specific address (Slave mode)
The specific SMBus addresses should be enabled if needed. Refer to Bus idle detection on
page 1210 for more details.
Packet error checking
PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the I2C_CR2 register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.
| Mode | SBC bit | RELOAD bit | AUTOEND bit | PECBYTE bit |
|---|---|---|---|---|
| Master Tx/Rx NBYTES + PEC+ STOP | x | 0 | 1 | 1 |
| Master Tx/Rx NBYTES + PEC + ReSTART | x | 0 | 0 | 1 |
| Slave Tx/Rx with PEC | 1 | 0 | x | 1 |
Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a timeout before the maximum time given in the SMBus specification.
tTIMEOUT check
In order to enable the tTIMEOUT check, the 12-bit TIMEOUTA[11:0] bits must be programmed with the timer reload value in order to check the tTIMEOUT parameter. The TIDLE bit must be configured to ‘0’ in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x tI2CCLK, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 211: Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms).
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the TIMEOUTEN bit is set.
tLOW:SEXT and tLOW:MEXT check
Depending on if the peripheral is configured as a master or as a slave, The 12-bit TIMEOUTB timer must be configured in order to check tLOW:SEXT for a slave and tLOW:MEXT for a master. As the standard specifies only a maximum, the user can choose the same value for the both.
Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than (TIMEOUTB+1) x 2048 x tI2CCLK, and in the timeout interval described in Bus idle
detection on page 1210 section, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 212: Examples of TIMEOUTB settings for various I2CCLK frequencies
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.
Bus Idle detection
In order to enable the tIDLE check, the 12-bit TIMEOUTA[11:0] field must be programmed with the timer reload value in order to obtain the tIDLE parameter. The TIDLE bit must be configured to ‘1 in order to detect both SCL and SDA high level timeout.
Then the timer is enabled by setting the TIMOUTEN bit in the I2C_TIMEOUTR register.
If both the SCL and SDA lines remain high for a time greater than (TIMEOUTA+1) x 4 x tI2CCLK, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 213: Examples of TIMEOUTA settings for various I2CCLK frequencies (max
tIDLE = 50 µs)
Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set.
This section is relevant only when SMBus feature is supported. Refer to Section 33.3: I2C
implementation.
| fI2CCLK | TIMEOUTA[11:0] bits | TIDLE bit | TIMEOUTEN bit | tTIMEOUT |
|---|---|---|---|---|
| 8 MHz | 0x61 | 0 | 1 | 98 x 2048 x 125 ns = 25 ms |
| 16 MHz | 0xC3 | 0 | 1 | 196 x 2048 x 62.5 ns = 25 ms |
| 32 MHz | 0x186 | 0 | 1 | 391 x 2048 x 31.25 ns = 25 ms |
| fI2CCLK | TIMEOUTB[11:0] bits | TEXTEN bit | tLOW:EXT |
|---|---|---|---|
| 8 MHz | 0x1F | 1 | 32 x 2048 x 125 ns = 8 ms |
| 16 MHz | 0x3F | 1 | 64 x 2048 x 62.5 ns = 8 ms |
| 32 MHz | 0x7C | 1 | 125 x 2048 x 31.25 ns = 8 ms |
| fI2CCLK | TIMEOUTA[11:0] bits | TIDLE bit | TIMEOUTEN bit | tTIDLE |
|---|---|---|---|---|
| 8 MHz | 0x63 | 1 | 1 | 100 x 4 x 125 ns = 50 µs |
| 16 MHz | 0xC7 | 1 | 1 | 200 x 4 x 62.5 ns = 50 µs |
| 32 MHz | 0x18F | 1 | 1 | 400 x 4 x 31.25 ns = 50 µs |
This section is relevant only when SMBus feature is supported. Refer to Section 33.3: I2C
implementation.
In addition to I2C slave transfer management (refer to Section 33.4.7: I2C slave mode) some additional software flowcharts are provided to support SMBus.
SMBus Slave transmitter
When the IP is used in SMBus, SBC must be programmed to ‘1’ in order to allow the PEC transmission at the end of the programmed number of data bytes. When the PECBYTE bit is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In
that case the total number of TXIS interrupts will be NBYTES-1 and the content of the I2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.
| (omitted) |
| (omitted) |
SMBus Slave receiver
When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1). Refer to Slave
Byte Control mode on page 1187 for more details.
In order to check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit must be set. In this case, after NBYTES-1 data have been received, the next received byte is compared with the internal I2C_PECR register content. A NACK is automatically generated if the comparison does not match, and an ACK is automatically generated if the comparison matches, whatever the ACK bit value. Once the PEC byte is received, it is copied into the I2C_RXDR register like any other data, and the RXNE flag is set.
In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
If no ACK software control is needed, the user can program PECBYTE=1 and, in the same write operation, program NBYTES with the number of bytes to be received in a continuous flow. After NBYTES-1 are received, the next received byte is checked as being the PEC.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.
| (omitted) |
| (omitted) |
This section is relevant only when SMBus feature is supported. Refer to Section 33.3: I2C
implementation.
In addition to I2C master transfer management (refer to Section 33.4.8: I2C master mode) some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the number of bytes must be programmed in the NBYTES[7:0] field, before setting the START bit. In this case the total number of TXIS interrupts will be NBYTES-1. So if the PECBYTE bit is set when NBYTES=0x1, the content of the I2C_PECR register is automatically transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode should be selected (AUTOEND=1). In this case, the STOP condition automatically follows the PEC transmission.
When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low. The RESTART condition must be programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.
| (omitted) |
SMBus Master receiver
When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content. A NACK response is given to the PEC byte, followed by a STOP condition.
When the SMBus master receiver wants to receive the PEC byte followed by a RESTART condition at the end of the transfer, software mode must be selected (AUTOEND=0). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content. The TC flag is set after the PEC byte reception, stretching the SCL line low. The RESTART condition can be programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.
| (omitted) |
The following are the error conditions which may cause communication to fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C is involved in the transfer as master or addressed slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the I2C enters address recognition state like for a correct START condition.
When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Arbitration lost (ARLO)
An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge.
When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Overrun/underrun error (OVR)
An overrun or underrun error is detected in slave mode when NOSTRETCH=1 and:
When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Packet Error Checking Error (PECERR)
This section is relevant only when the SMBus feature is supported. Refer to Section 33.3:
I2C implementation.
A PEC error is detected when the received PEC byte does not match with the I2C_PECR register content. A NACK is automatically sent after the wrong PEC reception.
When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Timeout Error (TIMEOUT)
This section is relevant only when the SMBus feature is supported. Refer to Section 33.3:
I2C implementation.
A timeout error occurs for any of these conditions:
When a timeout violation is detected in master mode, a STOP condition is automatically sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Refer to Section 33.3:
I2C implementation.
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Transmission using DMA
DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA peripheral (see Section 8: Direct memory access controller (DMA) on page 245) to the I2C_TXDR register whenever the TXIS bit is set.
Only the data are transferred with DMA.
initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. Refer to Master transmitter on page 1198.
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area configured using the DMA peripheral (refer to Section 8: Direct memory access controller
(DMA)) whenever the RXNE bit is set. Only the data (including PEC) are transferred with DMA.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
When the microcontroller enters debug mode (core halted), the SMBus timeout either continues to work normally or stops, depending on the DBG_I2Cx_STOP configuration bits in the DBG module.
| Mode | Description |
|---|---|
| Sleep | No effect I2C interrupts cause the device to exit the Sleep mode. |
| Stop | The contents of I2C registers are kept. |
| Standby | The I2C peripheral is powered down and must be reinitialized after exiting Standby. |
The table below gives the list of I2C interrupt requests.
| Interrupt event | Event flag | Event flag/Interrupt clearing method |
Interrupt enable control bit |
|---|---|---|---|
| Receive buffer not empty | RXNE | Read I2C_RXDR register | RXIE |
| Transmit buffer interrupt status | TXIS | Write I2C_TXDR register | TXIE |
| Stop detection interrupt flag | STOPF | Write STOPCF=1 | STOPIE |
| Transfer Complete Reload | TCR | Write I2C_CR2 with NBYTES[7:0] ≠ 0 | TCIE |
| Transfer complete | TC | Write START=1 or STOP=1 |
|
| Address matched | ADDR | Write ADDRCF=1 | ADDRIE |
| NACK reception | NACKF | Write NACKCF=1 | NACKIE |
| Bus error | BERR | Write BERRCF=1 |
ERRIE |
| Arbitration loss | ARLO | Write ARLOCF=1 |
|
| Overrun/Underrun | OVR | Write OVRCF=1 |
|
| PEC error | PECERR | Write PECERRCF=1 |
|
| Timeout/tLOW error | TIMEOUT | Write TIMEOUTCF=1 |
|
| SMBus Alert | ALERT | Write ALERTCF=1 |
Depending on the product implementation, all these interrupts events can either share the same interrupt vector (I2C global interrupt), or be grouped into 2 interrupt vectors (I2C event interrupt and I2C error interrupt). Refer to Table 46: STM32F76xxx and STM32F77xxx
vector table for details.
| (omitted) |
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
The peripheral registers are accessed by words (32-bit).
Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PECEN | ALERT EN |
SMBD EN |
SMBH EN |
GCEN | Res. | NOSTR ETCH |
SBC |
RXDMA EN |
TXDMA EN |
Res. | ANF OFF |
DNF | ERRIE | TCIE | STOP IE |
NACK IE |
ADDR IE |
RXIE | TXIE | PE |
|||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bit 23 | PECEN: PEC enable |
|
0: PEC calculation disabled
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 22 | ALERTEN: SMBus alert enable |
|
Device mode (SMBHEN=0): 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. Host mode (SMBHEN=1): 0: SMBus Alert pin (SMBA) not supported. 1: SMBus Alert pin (SMBA) supported.
When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 21 | SMBDEN: SMBus Device Default address enable |
|
0: Device default address disabled. Address 0b1100001x is NACKed.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 20 | SMBHEN: SMBus Host address enable |
|
0: Host address disabled. Address 0b0001000x is NACKed.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 19 | GCEN: General call enable |
|
0: General call disabled. Address 0b00000000 is NACKed. |
|
| Bit 18 | Reserved, must be kept at reset value. |
| Bit 17 | NOSTRETCH: Clock stretching disable |
|
This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. 0: Clock stretching enabled
This bit can only be programmed when the I2C is disabled (PE = 0).
|
|
| Bit 16 | SBC: Slave byte control |
|
This bit is used to enable hardware byte control in slave mode. 0: Slave byte control disabled |
|
| Bit 15 | RXDMAEN: DMA reception requests enable |
|
0: DMA mode disabled for reception |
|
| Bit 14 | TXDMAEN: DMA transmission requests enable |
|
0: DMA mode disabled for transmission |
|
| Bit 13 | Reserved, must be kept at reset value. |
| Bit 12 | ANFOFF: Analog noise filter OFF |
|
0: Analog noise filter enabled
This bit can only be programmed when the I2C is disabled (PE = 0).
|
|
| Bits 11:8 | DNF[3:0]: Digital noise filter |
|
These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK 0000: Digital filter disabled 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK ...
If the analog filter is also enabled, the digital filter is added to the analog filter.
This filter can only be programmed when the I2C is disabled (PE = 0). |
|
| Bit 7 | ERRIE: Error interrupts enable |
|
0: Error detection interrupts disabled
Any of these errors generate an interrupt:
Arbitration Loss (ARLO)
Bus Error detection (BERR)
Overrun/Underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)
|
|
| Bit 6 | TCIE: Transfer Complete interrupt enable |
|
0: Transfer Complete interrupt disabled
Any of these events will generate an interrupt:
Transfer Complete (TC)
Transfer Complete Reload (TCR)
|
|
| Bit 5 | STOPIE: STOP detection Interrupt enable |
|
0: Stop detection (STOPF) interrupt disabled |
|
| Bit 4 | NACKIE: Not acknowledge received Interrupt enable |
|
0: Not acknowledge (NACKF) received interrupts disabled |
|
| Bit 3 | ADDRIE: Address match Interrupt enable (slave only) |
|
0: Address match (ADDR) interrupts disabled |
|
| Bit 2 | RXIE: RX Interrupt enable |
|
0: Receive (RXNE) interrupt disabled |
|
| Bit 1 | TXIE: TX Interrupt enable |
|
0: Transmit (TXIS) interrupt disabled |
|
| Bit 0 | PE: Peripheral enable |
|
0: Peripheral disable When PE=0, the I2C SCL and SDA lines are released. Internal state machines and |
Address offset: 0x04
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | PEC BYTE |
AUTO END |
RE LOAD |
NBYTES[7:0] |
NACK | STOP | START | HEAD 10R |
ADD10 | RD_ WRN |
SADD[9:0] |
||||||||||||||||
| rs | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rs | rs | rs | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | PECBYTE: Packet error checking byte |
|
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. 0: No PEC transfer.
Writing ‘0’ to this bit has no effect.
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 25 | AUTOEND: Automatic end mode (master mode) |
|
This bit is set and cleared by software. 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
This bit has no effect in slave mode or when the RELOAD bit is set.
|
|
| Bit 24 | RELOAD: NBYTES reload mode |
|
This bit is set and cleared by software. 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). |
|
| Bits 23:16 | NBYTES[7:0]: Number of bytes |
|
The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Changing these bits when the START bit is set is not allowed. |
|
| Bit 15 | NACK: NACK generation (slave mode) |
|
The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Writing ‘0’ to this bit has no effect.
This bit is used in slave mode only: in master receiver mode, NACK is automatically When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value |
|
| Bit 14 | STOP: Stop generation (master mode) |
|
The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0.
In Master Mode:
0: No Stop generation.
Writing ‘0’ to this bit has no effect.
|
|
| Bit 13 | START: Start generation |
|
This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ‘1’ to the ADDRCF bit in the I2C_ICR register. 0: No Start generation.
|
|
| Bit 12 | HEAD10R: 10-bit address header only read direction (master receiver mode) |
|
0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
Changing this bit when the START bit is set is not allowed.
|
|
| Bit 11 | ADD10: 10-bit addressing mode (master mode) |
|
0: The master operates in 7-bit addressing mode,
Changing this bit when the START bit is set is not allowed.
|
|
| Bit 10 | RD_WRN: Transfer direction (master mode) |
|
0: Master requests a write transfer. Changing this bit when the START bit is set is not allowed. |
|
| Bits 9:8 | SADD[9:8]: Slave address bit 9:8 (master mode) |
|
In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent
Changing these bits when the START bit is set is not allowed.
|
|
| Bits 7:1 | SADD[7:1]: Slave address bit 7:1 (master mode) |
|
In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent
In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 7:1 of the slave address to be sent.
Changing these bits when the START bit is set is not allowed.
|
|
| Bit 0 | SADD0: Slave address bit 0 (master mode) |
|
In 7-bit addressing mode (ADD10 = 0): This bit is don’t care
In 10-bit addressing mode (ADD10 = 1):
This bit should be written with bit 0 of the slave address to be sent Changing these bits when the START bit is set is not allowed. |
Address offset: 0x08
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OA1EN | Res. | Res. | Res. | Res. | OA1 MODE |
OA1[9:8] | OA1[7:1] | OA1[0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bit 15 | OA1EN: Own Address 1 enable |
|
0: Own address 1 disabled. The received slave address OA1 is NACKed. |
|
| Bits 14:11 | Reserved, must be kept at reset value. |
| Bit 10 | OA1MODE: Own Address 1 10-bit mode |
|
0: Own address 1 is a 7-bit address.
This bit can be written only when OA1EN=0.
|
|
| Bits 9:8 | OA1[9:8]: Interface address |
|
7-bit addressing mode: do not care
These bits can be written only when OA1EN=0.
|
|
| Bits 7:1 | OA1[7:1]: Interface address |
|
7-bit addressing mode: 7-bit address
These bits can be written only when OA1EN=0.
|
|
| Bit 0 | OA1[0]: Interface address |
|
7-bit addressing mode: do not care This bit can be written only when OA1EN=0. |
Address offset: 0x0C
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
OA2EN | Res. | Res. | Res. | Res. | OA2MSK[2:0] | OA2[7:1] | Res. |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bit 15 | OA2EN: Own Address 2 enable |
|
0: Own address 2 disabled. The received slave address OA2 is NACKed. |
|
| Bits 14:11 | Reserved, must be kept at reset value. |
| Bits 10:8 | OA2MSK[2:0]: Own Address 2 masks |
|
000: No mask
These bits can be written only when OA2EN=0.
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and |
|
| Bits 7:1 | OA2[7:1]: Interface address |
|
7-bit addressing mode: 7-bit address
These bits can be written only when OA2EN=0.
|
|
| Bit 0 | Reserved, must be kept at reset value. |
Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRESC[3:0] | Res. | Res. | Res. | Res. | SCLDEL[3:0] | SDADEL[3:0] |
SCLH[7:0] | SCLL[7:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 31:28 | PRESC[3:0]: Timing prescaler |
|
This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page 1179) and for SCL high and low level counters (refer to I2C master initialization on page 1194). tPRESC = (PRESC+1) x tI2CCLK |
|
| Bits 27:24 | Reserved, must be kept at reset value. |
| Bits 23:20 | SCLDEL[3:0]: Data setup time |
|
This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC
tSCLDEL is used to generate tSU:DAT timing.
|
|
| Bits 19:16 | SDADEL[3:0]: Data hold time |
|
This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC
SDADEL is used to generate tHD:DAT timing.
|
|
| Bits 15:8 | SCLH[7:0]: SCL high period (master mode) |
|
This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC
SCLH is also used to generate tSU:STO and tHD:STA
timing.
|
|
| Bits 7:0 | SCLL[7:0]: SCL low period (master mode) |
|
This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC SCLL is also used to generate tBUF and tSU:STA timings. |
Note: This register must be configured when the I2C is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
Address offset: 0x14
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TEXTEN | Res. | Res. | Res. | TIMEOUTB[11:0] |
TIMOUTEN | Res. | Res. | TIDLE | TIMEOUTA[11:0] |
||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bit 31 | TEXTEN: Extended clock timeout enable |
|
0: Extended clock timeout detection is disabled |
|
| Bits 30:28 | Reserved, must be kept at reset value. |
| Bits 27:16 | TIMEOUTB[11:0]: Bus timeout B |
|
This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
These bits can be written only when TEXTEN=0.
|
|
| Bit 15 | TIMOUTEN: Clock timeout enable |
|
0: SCL timeout detection is disabled |
|
| Bits 14:13 | Reserved, must be kept at reset value. |
| Bit 12 | TIDLE: Idle clock timeout detection |
|
0: TIMEOUTA is used to detect SCL low timeout
This bit can be written only when TIMOUTEN=0.
|
|
| Bits 11:0 | TIMEOUTA[11:0]: Bus Timeout A |
|
This field is used to configure:
|
Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 33.3: I2C implementation.
Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADDCODE[6:0] | DIR |
BUSY | Res. | ALERT | TIME OUT |
PEC ERR |
OVR | ARLO | BERR | TCR | TC | STOPF | NACKF | ADDR | RXNE | TXIS | TXE |
||||||
| r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | rs | rs |
|||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:17 | ADDCODE[6:0]: Address match code (Slave mode) |
|
These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. |
|
| Bit 16 | DIR: Transfer direction (Slave mode) |
|
This flag is updated when an address match event occurs (ADDR=1). 0: Write transfer, slave enters receiver mode. |
|
| Bit 15 | BUSY: Bus busy |
|
This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. |
|
| Bit 14 | Reserved, must be kept at reset value. |
| Bit 13 | ALERT: SMBus alert |
|
This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit.
This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 12 | TIMEOUT: Timeout or tLOW detection flag |
|
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit.
This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 11 | PECERR: PEC Error in reception |
|
This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
This bit is cleared by hardware when PE=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 10 | OVR: Overrun/Underrun (slave mode) |
|
This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.
This bit is cleared by hardware when PE=0.
|
|
| Bit 9 | ARLO: Arbitration lost |
|
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit.
This bit is cleared by hardware when PE=0.
|
|
| Bit 8 | BERR: Bus error |
|
This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit.
This bit is cleared by hardware when PE=0.
|
|
| Bit 7 | TCR: Transfer Complete Reload |
|
This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value.
This bit is cleared by hardware when PE=0.
This flag is only for master mode, or for slave mode when the SBC bit is set.
|
|
| Bit 6 | TC: Transfer Complete (master mode) |
|
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set.
This bit is cleared by hardware when PE=0.
|
|
| Bit 5 | STOPF: Stop detection flag |
|
This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer:
It is cleared by software by setting the STOPCF bit.
This bit is cleared by hardware when PE=0.
|
|
| Bit 4 | NACKF: Not Acknowledge received flag |
|
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit.
This bit is cleared by hardware when PE=0.
|
|
| Bit 3 | ADDR: Address matched (slave mode) |
|
This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. This bit is cleared by hardware when PE=0. |
|
| Bit 2 | RXNE: Receive data register not empty (receivers) |
|
This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read.
This bit is cleared by hardware when PE=0.
|
|
| Bit 1 | TXIS: Transmit interrupt status (transmitters) |
|
This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
This bit is cleared by hardware when PE=0.
|
|
| Bit 0 | TXE: Transmit data register empty (transmitters) |
|
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to ‘1’ by software in order to flush the transmit data register I2C_TXDR.
This bit is set by hardware when PE=0.
|
Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | ALERT CF |
TIM OUTCF |
PECCF | OVRCF | ARLO CF |
BERR CF |
Res. | Res. | STOP CF |
NACK CF |
ADDR CF |
Res. | Res. | Res. |
| w | w | w | w | w | w | w | w | w |
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | ALERTCF: Alert flag clear |
|
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 12 | TIMOUTCF: Timeout detection flag clear |
|
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 11 | PECCF: PEC Error flag clear |
|
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 33.3: I2C implementation. |
|
| Bit 10 | OVRCF: Overrun/Underrun flag clear |
|
Writing 1 to this bit clears the OVR flag in the I2C_ISR register. |
|
| Bit 9 | ARLOCF: Arbitration Lost flag clear |
|
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. |
|
| Bit 8 | BERRCF: Bus error flag clear |
|
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bit 5 | STOPCF: Stop detection flag clear |
|
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. |
|
| Bit 4 | NACKCF: Not Acknowledge flag clear |
|
Writing 1 to this bit clears the NACKF flag in I2C_ISR register. |
|
| Bit 3 | ADDRCF: Address matched flag clear |
|
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. |
|
| Bits 2:0 | Reserved, must be kept at reset value. |
Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PEC[7:0] |
|||||||
| r | r | r | r | r | r | r | r |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | PEC[7:0] Packet error checking register |
|
This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0. |
Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 33.3: I2C implementation.
Address offset: 0x24
Reset value: 0x0000 0000
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RXDATA[7:0] |
|||||||
| r | r | r | r | r | r | r | r |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | RXDATA[7:0] 8-bit receive data |
|
Data byte received from the I2C bus. |
Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXDATA[7:0] |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | TXDATA[7:0] 8-bit transmit data |
|
Data byte to be transmitted to the I2C bus. These bits can be written only when TXE=1. |
The table below provides the I2C register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 |
I2C_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PECEN | ALERTEN | SMBDEN | SMBHEN | GCEN | Res | NOSTRETCH | SBC | RXDMAEN | TXDMAEN | Res. | ANFOFF | DNF[3:0] |
ERRIE | TCIE | STOPIE | NACKIE | ADDRIE | RXIE | TXIE | PE | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x4 |
I2C_CR2
|
Res. | Res. | Res. | Res. | Res. | PECBYTE | AUTOEND | RELOAD | NBYTES[7:0] |
NACK | STOP | START | HEAD10R | ADD10 | RD_WRN | SADD[9:0] |
||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x8 |
I2C_OAR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OA1EN | Res. | Res. | Res. | Res. | OA1MODE | OA1[9:0] |
|||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xC |
I2C_OAR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OA2EN | Res. | Res. | Res. | Res. | OA2MS K [2:0] |
OA2[7:1] |
Res. | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x10 |
I2C_TIMINGR | PRESC[3:0] |
Res. | Res. | Res. | Res. | SCLDEL[3:0 ] |
SDADEL[3: 0] |
SCLH[7:0] | SCLL[7:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x14 |
I2C_ TIMEOUTR |
TEXTEN | Res. | Res. | Res. | TIMEOUTB[11:0] |
TIMOUTEN | Res. | TIDLE | TIMEOUTA[11:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x18 |
I2C_ISR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADDCODE[6:0] |
DIR | BUSY | Res. | ALERT | TIMEOUT | PECERR | OVR | ARLO | BERR | TCR | TC | STOPF | NACKF | ADDR | RXNE | TXIS | TXE | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
||||||||||
| 0x1C |
I2C_ICR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ALERTCF | TIMOUTCF | PECCF | OVRCF | ARLOCF | BERRCF | Res. | Res. | STOPCF | NACKCF | ADDRCF | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x20 |
I2C_PECR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PEC[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x24 |
I2C_RXDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RXDATA[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||
| 0x28 |
I2C_TXDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXDATA[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of Full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a programmable baud rate generator.
It supports synchronous one-way communication and Half-duplex Single-wire communication, as well as multiprocessor communications. It also supports the LIN (Local Interconnect Network), Smartcard protocol and IrDA (Infrared Data Association) SIR ENDEC specifications and Modem operations (CTS/RTS).
High speed data communication is possible by using the DMA (direct memory access) for multibuffer configuration.
Multiprocessor communications
The USART enters mute mode if the address does not match.
| USART modes/features(1) |
USART1/USART2/ USART3/USART6 |
UART4/UART5/ UART7/UART8 |
|---|---|---|
| Hardware flow control for modem | X | X |
| Continuous communication using DMA | X | X |
| Multiprocessor communication | X | X |
| Synchronous mode | X | - |
| Smartcard mode | X | - |
| Single-wire Half-duplex communication | X | X |
| IrDA SIR ENDEC block | X | X |
| LIN mode | X | X |
| Dual clock domain | X | X |
| Receiver timeout interrupt | X | X |
| Modbus communication | X | X |
| Auto baud rate detection | X | X |
| Driver Enable | X | X |
| USART data length | 7(2), 8 and 9 bits |
|
Any USART bidirectional communication requires a minimum of two pins: Receive data In (RX) and Transmit data Out (TX):
RX: Receive data Input.
This is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
TX: Transmit data Output.
When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In Single-wire and Smartcard modes, this I/O is used to transmit and receive the data.
Serial data are transmitted and received through these pins in normal USART mode. The frames are comprised of:
Refer to Section 34.8: USART registers on page 1285 for the definitions of each bit.
The following pin is required to interface in synchronous mode and Smartcard mode:
The following pins are required in RS232 Hardware flow control mode:
The following pin is required in RS485 Hardware control mode:
Note: DE and RTS share the same pin.
| (omitted) |
The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the USART_CR1 register (see Figure 381).
Note: The 7-bit mode is supported only on some USARTs. In addition, not all modes are
supported in 7-bit data length mode. Refer to Section 34.4: USART implementation for
additional information.
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit.
These values can be inverted, separately for each signal, through polarity configuration control.
An Idle character is interpreted as an entire frame of “1”s (the number of “1”s includes the number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.
| (omitted) |
The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Character transmission
During an USART transmission, data shifts out least significant bit first (default configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 380).
Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.
Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in Control register 2, bits 13,12.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01) or 9 low bits (when M[1:0] = 10) followed by 2 stop bits (see Figure 382). It is not possible to transmit long breaks (break of length greater than 9/10/11 low bits).
| (omitted) |
Character transmission procedure
Single byte communication
Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the USART_TDR register stores the data in the TDR register; next, the data is copied in the shift register at the end of the currently ongoing transmission.
When no transmission is taking place, a write instruction to the USART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data in the USART_TDR register, it is mandatory to wait for TC=1 before disabling the USART or causing the microcontroller to enter the low-power mode (see Figure 383: TC/TXE behavior when transmitting).
| (omitted) |
Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bits (see Figure 381).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
The USART can receive data words of either 7, 8 or 9 bits depending on the M bits in the USART_CR1 register.
Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.
| (omitted) |
Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise flag is set if,
or
If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the idle state (no flag is set).
Character reception
During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR) between the internal bus and the receive shift register.
Character reception procedure
When a character is received:
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as for a received data character plus an interrupt if the IDLEIE bit is set.
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs:
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.
Selecting the clock source and the proper oversampling method
The choice of the clock source is done through the Clock Control system (see Section Reset and clock control (RCC))). The clock source must be chosen before enabling the USART (by setting the UE bit).
The clock source frequency is fCK.
When the dual clock domain with the wakeup from Stop mode is supported, the clock source can be one of the following sources: PCLK (default), LSE, HSI or SYSCLK. Otherwise, the USART clock source is PCLK.
Choosing LSE or HSI as clock source may allow the USART to receive data while the MCU is in low-power mode. Depending on the received data and wakeup mode selection, the USART wakes up the MCU, when needed, in order to transfer the received data by software reading the USART_RDR register or by DMA.
For the other clock sources, the system must be active in order to allow USART communication.
The communication speed range (specially the maximum communication speed) is also determined by the clock source.
The receiver implements different user-configurable oversampling techniques for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 385 and Figure 386).
Depending on the application:
Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options:
A single sample in the center of the received bit
Depending on the application:
When noise is detected in a frame:
The NF bit is reset by setting NFCF bit in ICR register.
Note: Oversampling by 8 is not available in LIN, Smartcard and IrDA modes. In those modes, the
OVER8 bit is forced to ‘0’ by hardware.
| (omitted) |
| (omitted) |
| Sampled value | NE status | Received bit value |
|---|---|---|
| 000 | 0 | 0 |
| 001 | 1 | 0 |
| 010 | 1 | 0 |
| 011 | 1 | 1 |
| 100 | 1 | 0 |
| 101 | 1 | 1 |
| 110 | 1 | 1 |
| 111 | 0 | 1 |
Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.
When the framing error is detected:
The FE bit is reset by writing 1 to the FECF in the USART_ICR register.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the USART_BRR register.
Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1)
In case of oversampling by 16, the equation is:
-------------f-C----K-
-------------
Tx/Rx baud
= USARTDIV
In case of oversampling by 8, the equation is:
-------2-----×
------ f--C---K- --------
Tx/Rx baud
= USARTDIV
Equation 2: Baud rate in Smartcard, LIN and IrDA modes (OVER8 = 0)
In Smartcard, LIN and IrDA modes, only Oversampling by 16 is supported:
Tx/Rx baud
= -------------f
-C----K-
-------------
USARTDIV
USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
Note: The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
In case of oversampling by 16 or 8, USARTDIV must be greater than or equal to 16d.
How to derive USARTDIV from USART_BRR register values
Example 1
To obtain 9600 baud with fCK = 8 MHz.
In case of oversampling by 16:
USARTDIV = 8 000 000/9600
BRR = USARTDIV = 833d = 0341h
In case of oversampling by 8:
USARTDIV = 2 * 8 000 000/9600
USARTDIV = 1666,66 (1667d = 683h)
BRR[3:0] = 3h >> 1 = 1h
BRR = 0x681
Example 2
To obtain 921.6 Kbaud with fCK = 48 MHz.
In case of oversampling by 16:
USARTDIV = 48 000 000/921 600
BRR = USARTDIV = 52d = 34h
In case of oversampling by 8:
USARTDIV = 2 * 48 000 000/921 600
USARTDIV = 104 (104d = 68h)
BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h
BRR = 0x64
| Desired baud rate (Bps) | Actual baud rate (Bps) | BRR | Error |
|---|---|---|---|
| 9600 | 9600 | AFC4 | 0.00000000 |
| 19200 | 19200 | 57E2 | 0.00000000 |
| 38400 | 38400 | 2BF1 | 0.00000000 |
| 57600 | 57600 | 1D46 | 0.00000000 |
| 115200 | 115200 | EA3 | 0.00000000 |
| 230400 | 230400 | 751 | 0.00000000 |
| 460800 | 461538.461 | 3A4 | 0.160256293 |
| 921600 | 923076.923 | 1D2 | 0.001602564 |
| 13500000 | 13500000.000 | 20 | 0.00000000 |
| 27000000 | 27000000.000 | 10 | 0.00000000 |
| Desired baud rate (Bps) | Actual baud rate (Bps) | BRR | Error |
|---|---|---|---|
| 9600 | 9600.000 | 57E4 | 0.00000000 |
| 19200 | 19200.000 | 2BF2 | 0.00000000 |
| 38400 | 38400.000 | 15F9 | 0.00000000 |
| 57600 | 57600.000 | EA6 | 0.00000000 |
| 115200 | 115200.000 | 753 | 0.00000000 |
| 230400 | 230522.946 | 3A9 | 0.05336179 |
| 460800 | 461538.462 | 1D4 | 0.16025641 |
| 921600 | 923076.923 | EA | 0.16025641 |
| 4000000 | 4000000.000 | 36 | 0.00000000 |
| 6000000 | 6000000.000 | 24 | 0.00000000 |
| 10000000 | 10285714.286 | 15 | 2.85714286 |
| 13500000 | 13500000.000 | 10 | 0.00000000 |
The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are:
DTRA+ DQUANT + DREC + DTCL+ DWU < USART receiver′ s tolerance
where
DWU is the error due to sampling point deviation when the wakeup from Stop mode is used.
when M[1:0] = 01:
-t
-W-----U----U----S---A----R---T-
-
DWU
= 11× Tbit
when M[1:0] = 00:
-t
-W-----U----U----S---A----R---T-
-
DWU
= 10× Tbit
when M[1:0] = 10:
-t
-W-----U----U----S---A----R---T-
-DWU
= 9× Tbit
tWUUSART is the time between:
The instant when clock (requested by the peripheral) is ready and reaching the peripheral and regulator is ready.
The USART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 221 and Table 221 depending on the following choices:
| M bits |
OVER8 bit = 0 | OVER8 bit = 1 |
||
|---|---|---|---|---|
| ONEBIT=0 | ONEBIT=1 | ONEBIT=0 | ONEBIT=1 |
|
| 00 | 3.75% | 4.375% | 2.50% | 3.75% |
| 01 | 3.41% | 3.97% | 2.27% | 3.41% |
| 10 | 4.16% | 4.86% | 2.77% | 4.16% |
| M bits |
OVER8 bit = 0 | OVER8 bit = 1 |
||
|---|---|---|---|---|
| ONEBIT=0 | ONEBIT=1 | ONEBIT=0 | ONEBIT=1 |
|
| 00 | 3.33% | 3.88% | 2% | 3% |
| 01 | 3.03% | 3.53% | 1.82% | 2.73% |
| 10 | 3.7% | 4.31% | 2.22% | 3.33% |
Note: The data specified in Table 221 and Table 222 may slightly differ in the special case when
the received frames contain some Idle frames of exactly 10-bit durations when M bits = 00
(11-bit durations when M bits =01 or 9- bit durations when M bits = 10).
The USART is able to detect and automatically set the USART_BRR register value based on the reception of one character. Automatic baud rate detection is useful under two circumstances:
The clock source frequency must be compatible with the expected communication speed (when oversampling by 16, the baud rate is between fCK/65535 and fCK/16. when oversampling by 8, the baud rate is between fCK/65535 and fCK/8).
Before activating the auto baud rate detection, the auto baud rate detection mode must be chosen. There are various modes based on different character patterns.
They can be chosen through the ABRMOD[1:0] field in the USART_CR2 register. In these auto baud rate modes, the baud rate is measured several times during the synchronization data reception and each measurement is compared to the previous one.
These modes are:
start bit (BRs), then at the end of bit 6 (based on the measurement done from falling edge to falling edge: BR6). Bit 0 to bit 6 are sampled at BRs while further bits of the character are sampled at BR6.
Mode 3: A 0x55 character frame. In this case, the baud rate is updated first at the end of the start bit (BRs), then at the end of bit 0 (based on the measurement done from falling edge to falling edge: BR0), and finally at the end of bit 6 (BR6). Bit 0 is sampled at BRs, bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled at BR6.
In parallel, another check is performed for each intermediate transition of RX line. An error is generated if the transitions on RX are not sufficiently synchronized with the receiver (the receiver being based on the baud rate calculated on bit 0).
Prior to activating auto baud rate detection, the USART_BRR register must be initialized by writing a non-zero baud rate value.
The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2 register. The USART will then wait for the first character on the RX line. The auto baud rate operation completion is indicated by the setting of the ABRF flag in the USART_ISR register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this case the BRR value may be corrupted and the ABRE error flag will be set. This also happens if the communication speed is not compatible with the automatic baud rate detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between 8 and 65536 clock periods (oversampling by 8)).
The RXNE interrupt will signal the end of the operation.
At any later time, the auto baud rate detection may be relaunched by resetting the ABRF flag (by writing a 0).
Note: If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be
corrupted.
In multiprocessor communication, the following bits are to be kept cleared:
It is possible to perform multiprocessor communication with the USART (with several USARTs connected in a network). For instance one of the USARTs can be the master, its TX output connected to the RX inputs of the other USARTs. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.
In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant USART service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function. In order to use the mute mode feature, the MME bit must be set in the USART_CR1 register.
In mute mode:
The USART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the USART_CR1 register:
Idle line detection (WAKE=0)
The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_ISR register. An example of mute mode behavior using Idle line detection is given in Figure 387.
| (omitted) |
Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be
entered (RWU is not set).
If the USART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).
4-bit/7-bit address mark detection (WAKE=1)
In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4-bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The USART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the USART enters mute mode.
The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case.
The USART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared.
An example of mute mode behavior using address mark detection is given in Figure 388.
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The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII protocols. Modbus/RTU is a half duplex, block transfer protocol. The control part of the protocol (address recognition, block integrity control and command interpretation) must be implemented in software.
The USART offers basic support for the end of the block detection, without software overhead or other resources.
Modbus/RTU
In this mode, the end of one block is recognized by a “silence” (idle line) for more than 2 character times. This function is implemented through the programmable timeout function.
The timeout function and interrupt must be activated, through the RTOEN bit in the USART_CR2 register and the RTOIE in the USART_CR1 register. The value corresponding to a timeout of 2 character times (for example 22 x bit duration) must be programmed in the RTO register. when the receive line is idle for this duration, after the last stop bit is received, an interrupt is generated, informing the software that the current block reception is completed.
Modbus/ASCII
In this mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function.
By programming the LF ASCII code in the ADD[7:0] field and by activating the character match interrupt (CMIE=1), the software is informed when a LF has been received and can check the CR/LF in the DMA buffer.
Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bits, the possible USART frame formats are as listed in Table 223.
| M bits | PCE bit | USART frame(1) |
|---|---|---|
| 00 | 0 | | SB | 8-bit data | STB | |
| 00 | 1 | | SB | 7-bit data | PB | STB | |
| 01 | 0 | | SB | 9-bit data | STB | |
| 01 | 1 | | SB | 8-bit data | PB | STB | |
| 10 | 0 | | SB | 7-bit data | STB | |
| 10 | 1 | | SB | 6-bit data | PB | STB | |
Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even parity is selected (PS bit in USART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is selected (PS bit in USART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the USART_ICR register.
Parity generation in transmission
If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).
This section is relevant only when LIN mode is supported. Please refer to Section 34.4:
USART implementation on page 1243.
The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared:
LIN transmission
The procedure explained in Section 34.5.2: USART transmitter has to be applied for LIN Master transmission. It must be the same as for normal USART transmission with the following differences:
LIN reception
When LIN mode is enabled, the break detection circuit is activated. The detection is totally independent from the normal USART receiver. A break can be detected whenever it occurs, during Idle state or during a frame.
When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break characters or data. After a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0, and are followed by a delimiter character, the LBDF flag is set in USART_ISR. If the LBDIE bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it signifies that the RX line has returned to a high level.
If a ‘1’ is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again.
If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART, without taking into account the break detection.
If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit detected at ‘0’, which will be the case for any break frame), the receiver stops until the break detection circuit receives either a ‘1’, if the break word was not complete, or a delimiter character if a break has been detected.
The behavior of the break detector state machine and the break flag is shown on the Figure 389: Break detection in LIN mode (11-bit break length - LBDL bit is set) on
page 1266.
Examples of break frames are given on Figure 390: Break detection in LIN mode vs.
Framing error detection on page 1267.
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The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
In this mode, the USART can be used to control bidirectional synchronous serial communications in master mode. The CK pin is the output of the USART transmitter clock. No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the phase of the external clock (see Figure 391, Figure 392 and Figure 393).
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is synchronous.
In this mode the USART receiver works in a different manner compared to the asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending on CPOL and CPHA), without any oversampling. A setup and a hold time must be respected (which depends on the baud rate: 1/16 bit duration).
Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.
| (omitted) |
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Note: The function of CK is different in Smartcard mode. Refer to Section 34.5.13: USART
Smartcard mode
for more details.
Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared:
The USART can be configured to follow a Single-wire Half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and Full-duplex communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to 1:
Apart from this, the communication protocol is similar to normal USART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set.
This section is relevant only when Smartcard mode is supported. Please refer to Section 34.4: USART implementation on page 1243.
Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In Smartcard mode, the following bits must be kept cleared:
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The smartcard interface is designed to support asynchronous protocol for smartcards as defined in the ISO 7816-3 standard. Both T=0 (character mode) and T=1 (block mode) are supported.
The USART should be configured as:
In T=0 (character) mode, the parity error is indicated at the end of each character during the guard time period.
Figure 395 shows examples of what can be seen on the data line with and without parity error.
| (omitted) |
When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard. The TX pin must be configured as open drain.
Smartcard mode implements a single wire half duplex communication protocol.
Note: A break character is not significant in Smartcard mode. A 0x00 data with a framing error is
treated as data and not as a break.
No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the
other configurations) is not defined by the ISO protocol.
Figure 396 details how the NACK signal is sampled by the USART. In this example the USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the USART is enabled in order to check the integrity of the data and the NACK signal.
| (omitted) |
The USART can provide a clock to the smartcard through the CK output. In Smartcard mode, CK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the prescaler register USART_GTPR. CK frequency can be programmed from fCK/2 to fCK/62, where fCK is the peripheral input clock.
Block mode (T=1)
In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in the UART_CR3 register.
When requesting a read from the smartcard, in block mode, the software must enable the receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value. If no answer is received from the card before the expiration of this period, the RTOF flag will be set and a timeout interrupt will be generated (if RTOIE bit in the USART_CR1 register is set). If the first character is received before the expiration of the period, it is signaled by the RXNE interrupt.
Note: The RXNE interrupt must be enabled even when using the USART in DMA mode to read
from the smartcard in block mode. In parallel, the DMA must be enabled only after the first
received byte.
After the reception of the first character (RXNE interrupt), the RTO bit fields in the RTOR register must be programmed to the CWT (character wait time) - 11 value, in order to allow the automatic check of the maximum wait time between two consecutive characters. This time is expressed in baudtime units. If the smartcard does not send a new character in less than the CWT period after the end of the previous character, the USART signals this to the software through the RTOF flag and interrupt (when RTOIE bit is set).
Note: The RTO counter starts counting:
- From the end of the stop bit in case STOP = 00.
- From the end of the second stop bit in case of STOP = 10.
- 1 bit duration after the beginning of the STOP bit in case STOP = 11.
- From the beginning of the STOP bit in case STOP = 01.
As in the Smartcard protocol definition, the BWT/CWT values are defined from the
beginning (start bit) of the last character. The RTO register must be programmed to BWT -
11 or CWT -11, respectively, taking into account the length of the last character itself.
A block length counter is used to count all the characters received by the USART. This counter is reset when the USART is transmitting (TXE=0). The length of the block is communicated by the smartcard in the third byte of the block (prologue field). This value must be programmed to the BLEN field in the USART_RTOR register. when using DMA mode, before the start of the block, this register field must be programmed to the minimum value (0x0). with this value, an interrupt is generated after the 4th received character. The software must read the LEN field (third byte), its value must be read from the receive buffer.
In interrupt driven receive mode, the length of the block may be checked by software or by programming the BLEN value. However, before the start of the block, the maximum value of BLEN (0xFF) may be programmed. The real value will be programmed after the reception of the third character.
If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the BLEN=LEN. If the block is using the CRC mechanism (2 epilogue bytes), BLEN=LEN+1 must be programmed. The total block length (including prologue, epilogue and information fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF flag and interrupt (when EOBIE bit is set).
In case of an error in the block length, the end of the block is signaled by the RTO interrupt (Character wait Time overflow).
Note: The error checking code (LRC/CRC) must be computed/verified by software.
Direct and inverse convention
The Smartcard protocol defines two conventions: direct and inverse.
The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=0, DATAINV=0 (default values).
The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state on the signal line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=1, DATAINV=1.
Note: When logical data values are inverted (0=H, 1=L), the parity bit is also inverted in the same
way.
In order to recognize the card convention, the card sends the initial character, TS, as the first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS are: LHHL LLL LLH and LHHL HHH LLH.
Character parity is correct when there is an even number of bits set to 1 in the nine moments 2 to 10.
As the USART does not know which convention is used by the card, it needs to be able to recognize either pattern and act accordingly. The pattern recognition is not done in hardware, but through a software sequence. Moreover, supposing that the USART is configured in direct convention (default) and the card answers with the inverse convention, TS = LHHL LLL LLH => the USART received character will be ‘03’ and the parity will be odd.
Therefore, two methods are available for TS pattern recognition:
Method 1
The USART is programmed in standard Smartcard mode/direct convention. In this case, the TS pattern reception generates a parity error interrupt and error signal to the card.
Alternatively, in answer to the parity error interrupt, the software may decide to reprogram the USART and to also generate a new reset command to the card, then wait again for the TS.
Method 2
The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as:
(H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen
(H) LHHL HHH LLH = 0x13B -> direct convention to be chosen
The software checks the received character against these two patterns and, if any of them match, then programs the USART accordingly for the next character reception.
If none of the two is recognized, a card reset may be generated in order to restart the negotiation.
This section is relevant only when IrDA mode is supported. Please refer to Section 34.4:
USART implementation on page 1243.
IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared:
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse (see Figure 397).
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream output from USART. The output pulse stream is transmitted to an external output driver and infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In normal mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The decoder input is normally high (marking state) in the Idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is detected when the decoder input is low.
IrDA low-power mode
Transmitter
In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.
Generally, this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value.
Receiver
Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1 PSC period. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in the USART_GTPR).
Note: A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).
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The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently.
Note: Please refer to Section 34.4: USART implementation on page 1243 to determine if the DMA
mode is supported. If DMA is not supported, use the USART as explained in Section 34.5.2:
USART transmitter or Section 34.5.3: USART receiver. To perform continuous
communication, the user can clear the TXE/ RXNE flags In the USART_ISR register.
Transmission using DMA
DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to Section 8: Direct memory access controller (DMA) on page 242) to the USART_TDR register whenever the TXE bit is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the channel number):
When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART
communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame.
| (omitted) |
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_RDR register to a SRAM area configured using the DMA peripheral (refer to Section 8: Direct memory access controller (DMA)) whenever a data byte is received. To map a DMA channel for USART reception, use the following procedure:
When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.
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Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur.
It is possible to control the serial data flow between 2 devices by using the CTS input and the RTS output. The Figure 401 shows how to connect 2 devices in this mode:
| (omitted) |
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the USART_CR3 register).
RS232 RTS flow control
If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, RTS is de-asserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 402 shows an example of communication with RTS flow control enabled.
| (omitted) |
RS232 CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input before transmitting the next frame. If CTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the transmission does not occur. when CTS is de-asserted during a transmission, the current transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 403
shows an example of communication with CTS flow control enabled.
| (omitted) |
Note: For correct behavior, CTS must be asserted at least 3 USART clock source periods before
the end of the current character. In addition it should be noted that the CTSCF flag may not
be set for pulses shorter than 2 x PCLK periods.
RS485 Driver Enable
The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register. This allows the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the USART_CR1 control register. The de-assertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bit fields in the USART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
The USART is able to wake up the MCU from Stopmode when the UESM bit is set and the USART clock is set to HSI or LSE (refer to Section Reset and clock control (RCC)).
USART source clock is HSI
If during stop mode the HSI clock is switched OFF, when a falling edge on the USART receive line is detected, the USART interface requests the HSI clock to be switched ON. The HSI clock is then used for the frame reception.
USART source clock is LSE
Same principle as described in case of USART source clock is HSI with the difference that the LSE is ON in stop mode, but the LSE clock is not propagated to USART if the
USART is not requesting it. The LSE clock is not OFF but there is a clock gating to avoid useless consumption.
When the USART clock source is configured to be fLSE or fHSI, it is possible to keep enabled this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this case, the RXNEIE bit must be set before entering Stop mode.
Alternatively, a specific interrupt may be selected through the WUS bit fields.
In order to be able to wake up the MCU from Stop mode, the UESM bit in the USART_CR1 control register must be set prior to entering Stop mode.
When the wakeup event is detected, the WUF flag is set by hardware and a wakeup interrupt is generated if the WUFIE bit is set.
Note: Before entering Stop mode, the user must ensure that the USART is not performing a
transfer. BUSY flag cannot ensure that Stop mode is never entered during a running
reception.
The WUF flag is set when a wakeup event is detected, independently of whether the MCU is
in Stop or in an active mode.
When entering Stop mode just after having initialized and enabled the receiver, the REACK
bit must be checked to ensure the USART is actually enabled.
When DMA is used for reception, it must be disabled before entering Stop mode and re-enabled upon exit from Stop mode.
The wakeup from Stop mode feature is not available for all modes. For example it doesn’t
work in SPI mode because the SPI operates in master mode only.
Using Mute mode with Stop mode
If the USART is put into Mute mode before entering Stop mode:
Determining the maximum USART baud rate allowing to wakeup correctly
from Stop mode when the USART clock source is the HSI clock
The maximum baud rate allowing to wakeup correctly from stop mode depends on:
DTRA + DQUANT + DREC + DTCL + DWU < USART receiver's tolerance
DWU max = tWUUSART / ( x Tbit Min)
Tbit Min = tWUUSART / (9 x DWU max)
If we consider an ideal case where the parameters DTRA, DQUANT, DREC and DTCL are at 0%, the DWU max is %. In reality, we need to consider at least the HSI inaccuracy.
| Mode | Description |
|---|---|
| Sleep | No effect. USART interrupt causes the device to exit Sleep mode. |
| Low-power run | No effect. |
| Low-power sleep | No effect. USART interrupt causes the device to exit Low-power sleep mode. |
| Stop 0 / Stop 1 |
The USART registers content is kept. The USART is able to wake up the MCU from Stop 0 and Stop 1 modes when the UESM bit is set and the USART clock is set to HSI16 or LSE. The MCU wakeup from Stop 0 and Stop 1 modes can be done using either a standard RXNE or a WUF interrupt. |
| Stop 2 | The USART registers content is kept. The USART must either be disabled or put in reset state. |
| Standby | The USART is powered down and must be reinitialized when the device has exited from Standby or Shutdown mode. |
| Shutdown |
| Interrupt event | Event flag | Enable Control bit |
|---|---|---|
| Transmit data register empty | TXE | TXEIE |
| CTS interrupt | CTSIF | CTSIE |
| Transmission Complete | TC | TCIE |
| Receive data register not empty (data ready to be read) | RXNE |
RXNEIE |
| Overrun error detected | ORE |
|
| Idle line detected | IDLE | IDLEIE |
| Parity error | PE | PEIE |
| LIN break | LBDF | LBDIE |
| Noise Flag, Overrun error and Framing Error in multibuffer communication. | NF or ORE or FE | EIE |
| Character match | CMF | CMIE |
| Receiver timeout | RTOF | RTOIE |
| End of Block | EOBF | EOBIE |
| Wakeup from Stop mode | WUF(1) | WUFIE |
| Transmission complete before guard time | TCBGT | TCBGTIE |
The USART interrupt events are connected to the same interrupt vector (see Figure 404).
These events generate an interrupt if the corresponding Enable Control Bit is set.
| (omitted) |
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | M1 | EOBIE | RTOIE | DEAT[4:0] | DEDT[4:0] |
OVER8 | CMIE | MME | M0 | WAKE | PCE | PS | PEIE | TXEIE | TCIE | RXNEIE | IDLEIE | TE | RE | UESM | UE |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bit 28 | M1: Word length |
|
This bit, with bit 12 (M0), determines the word length. It is set or cleared by software.
Not all modes are supported In 7-bit data length mode. Refer to Section 34.4: USART
|
|
| Bit 27 | EOBIE: End of Block interrupt enable |
|
This bit is set and cleared by software. If the USART does not support Smartcard mode, this bit is reserved and must be kept |
|
| Bit 26 | RTOIE: Receiver timeout interrupt enable |
|
This bit is set and cleared by software. If the USART does not support the Receiver timeout feature, this bit is reserved and |
|
| Bits 25:21 | DEAT[4:0]: Driver Enable assertion time |
|
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0). If the Driver Enable feature is not supported, this bit is reserved and must be kept at |
|
| Bits 20:16 | DEDT[4:0]: Driver Enable de-assertion time |
|
This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate). If the Driver Enable feature is not supported, this bit is reserved and must be kept at |
|
| Bit 15 | OVER8: Oversampling mode |
|
0: Oversampling by 16
In LIN, IrDA and modes, this bit must be kept at reset value.
|
|
| Bit 14 | CMIE: Character match interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 13 | MME: Mute mode enable |
|
This bit activates the mute mode function of the USART. when set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. |
|
| Bit 12 | M0: Word length |
|
This bit, with bit 28 (M1), determines the word length. It is set or cleared by software. See Bit 28 (M1) description. |
|
| Bit 11 | WAKE: Receiver wakeup method |
|
This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. |
|
| Bit 10 | PCE: Parity control enable |
|
This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). |
|
| Bit 9 | PS: Parity selection |
|
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. |
|
| Bit 8 | PEIE: PE interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 7 | TXEIE: interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 6 | TCIE: Transmission complete interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 5 | RXNEIE: RXNE interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 4 | IDLEIE: IDLE interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 3 | TE: Transmitter enable |
|
This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble In Smartcard mode, when TE is set there is a 1 bit-time delay before the transmission |
|
| Bit 2 | RE: Receiver enable |
|
This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled |
|
| Bit 1 | UESM: USART enable in Stop mode |
|
When this bit is cleared, the USART is not able to wake up the MCU from Stop mode. When this bit is set, the USART is able to wake up the MCU from Stop mode, provided that the USART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software.
It is recommended to set the UESM bit just before entering Stop mode and clear it on If the USART does not support the wakeup from Stop feature, this bit is reserved and |
|
| Bit 0 | UE: USART enable |
|
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USART_ISR are set to their default values. This bit is set and cleared by software.
In order to go into low-power mode without generating errors on the line, the TE bit The DMA requests are also reset when UE = 0 so the DMA channel must be disabled |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADD[7:4] | ADD[3:0] | RTOEN | ABRMOD[1:0] | ABREN | MSBFI RST |
DATAINV | TXINV | RXINV |
SWAP | LINEN | STOP[1:0] | CLKEN | CPOL | CPHA | LBCL | Res. | LBDIE | LBDL | ADDM7 | Res. | Res. | Res. | Res. |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||
| Bits 31:28 | ADD[7:4]: Address of the USART node |
|
This bit-field gives the address of the USART node or a character code to be recognized. |
|
| Bits 27:24 | ADD[3:0]: Address of the USART node |
|
This bit-field gives the address of the USART node or a character code to be recognized. |
|
| Bit 23 | RTOEN: Receiver timeout enable |
|
This bit is set and cleared by software. If the USART does not support the Receiver timeout feature, this bit is reserved and must be |
|
| Bits 22:21 | ABRMOD[1:0]: Auto baud rate mode |
|
These bits are set and cleared by software.
If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example If the USART does not support the auto baud rate feature, this bit is reserved and must be kept |
|
| Bit 20 | ABREN: Auto baud rate enable |
|
This bit is set and cleared by software. If the USART does not support the auto baud rate feature, this bit is reserved and must be kept |
|
| Bit 19 | MSBFIRST: Most significant bit first |
|
This bit is set and cleared by software. |
|
| Bit 18 | DATAINV: Binary data inversion |
|
This bit is set and cleared by software. |
|
| Bit 17 | TXINV: TX pin active level inversion |
|
This bit is set and cleared by software. |
|
| Bit 16 | RXINV: RX pin active level inversion |
|
This bit is set and cleared by software. |
|
| Bit 15 | SWAP: Swap TX/RX pins |
|
This bit is set and cleared by software. |
|
| Bit 14 | LINEN: LIN mode enable |
|
This bit is set and cleared by software. If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. |
|
| Bits 13:12 | STOP[1:0]: STOP bits |
|
These bits are used for programming the stop bits. |
|
| Bit 11 | CLKEN: Clock enable |
|
This bit allows the user to enable the CK pin.
If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must In order to provide correctly the CK clock to the Smartcard when CK is always available When |
|
| Bit 10 | CPOL: Clock polarity |
|
This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship 0: Steady low value on CK pin outside transmission window If synchronous mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 9 | CPHA: Clock phase |
|
This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 392 and Figure 393) If synchronous mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 8 | LBCL: Last bit clock pulse |
|
This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the CK pin The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bits in the USART_CR1 register. If synchronous mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | LBDIE: LIN break detection interrupt enable |
|
Break interrupt mask (break detection using break delimiter). If LIN mode is not supported, this bit is reserved and must be kept at reset value. Please refer |
|
| Bit 5 | LBDL: LIN break detection length |
|
This bit is for selection between 11 bit or 10 bit break detection. If LIN mode is not supported, this bit is reserved and must be kept at reset value. Please refer |
|
| Bit 4 | ADDM7:7-bit Address Detection/4-bit Address Detection |
|
This bit is for selection between 4-bit address detection or 7-bit address detection. 0: 4-bit address detection In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address |
|
| Bits 3:0 | Reserved, must be kept at reset value. |
|
The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
|
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TCBGT IE |
UCESM | WUFIE | WUS1 | WUS0 | SCARC NT2 |
SCARC NT1 |
SCARC NT0 |
Res. |
DEP | DEM | DDRE | OVRDI S |
ONEBI T |
CTSIE | CTSE | RTSE | DMAT | DMAR | SCEN | NACK | HDSEL | IRLP | IREN | EIE |
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | TCBGTIE: Transmission complete before guard time interrupt enable |
|
This bit is set and cleared by software. If Smartcard mode is not supported, this bit is reserved and must be kept at reset value |
|
| Bit 23 | UCESM: USART Clock Enable in Stop mode. |
|
This bit is set and cleared by software. |
|
| Bit 22 | WUFIE: Wakeup from Stop mode interrupt enable |
|
This bit is set and cleared by software.
WUFIE must be set before entering in Stop mode.
The WUF interrupt is active only in Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and |
|
| Bits 21:20 | WUS[1:0]: Wakeup from Stop mode interrupt flag selection |
|
This bit-field specify the event which activates the WUF (wakeup from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) If the USART does not support the wakeup from Stop feature, this bit is reserved and |
|
| Bits 19:17 | SCARCNT[2:0]: Smartcard auto-retry count |
|
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. If Smartcard mode is not supported, this bit is reserved and must be kept at reset |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bit 15 | DEP: Driver enable polarity selection |
|
0: DE signal is active high. 1: DE signal is active low. If the Driver Enable feature is not supported, this bit is reserved and must be kept at |
|
| Bit 14 | DEM: Driver enable mode |
|
This bit allows the user to activate the external transceiver control, through the DE signal. 0: DE function is disabled. 1: DE function is enabled. The DE signal is output on the RTS pin. If the Driver Enable feature is not supported, this bit is reserved and must be kept at |
|
| Bit 13 | DDRE: DMA Disable on Reception Error |
|
0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred (used for Smartcard mode).
The reception errors are: parity error, framing error or noise error.
|
|
| Bit 12 | OVRDIS: Overrun Disable |
|
This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
This control bit allows checking the communication flow without reading the data.
|
|
| Bit 11 | ONEBIT: One sample bit method enable |
|
This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled.
ONEBIT feature applies only to data bits, It does not apply to Start bit.
|
|
| Bit 10 | CTSIE: CTS interrupt enable |
|
0: Interrupt is inhibited If the hardware flow control feature is not supported, this bit is reserved and must be |
|
| Bit 9 | CTSE: CTS enable |
|
0: CTS hardware flow control disabled If the hardware flow control feature is not supported, this bit is reserved and must be |
|
| Bit 8 | RTSE: RTS enable |
|
0: RTS hardware flow control disabled If the hardware flow control feature is not supported, this bit is reserved and must be |
|
| Bit 7 | DMAT: DMA enable transmitter |
|
This bit is set/reset by software |
|
| Bit 6 | DMAR: DMA enable receiver |
|
This bit is set/reset by software |
|
| Bit 5 | SCEN: Smartcard mode enable |
|
This bit is used for enabling Smartcard mode. If the USART does not support Smartcard mode, this bit is reserved and must be kept |
|
| Bit 4 | NACK: Smartcard NACK enable |
|
0: NACK transmission in case of parity error is disabled If the USART does not support Smartcard mode, this bit is reserved and must be kept |
|
| Bit 3 | HDSEL: Half-duplex selection |
|
Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected |
|
| Bit 2 | IRLP: IrDA low-power |
|
This bit is used for selecting between normal and low-power IrDA modes If IrDA mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 1 | IREN: IrDA mode enable |
|
This bit is set and cleared by software. If IrDA mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 0 | EIE: Error interrupt enable |
|
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_ISR register). |
This register can only be written when the USART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
BRR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:4 |
BRR[15:4]
|
|
BRR[15:4] = USARTDIV[15:4] |
|
| Bits 3:0 |
BRR[3:0]
|
|
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
GT[7:0] | PSC[7:0] |
||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:8 | GT[7:0]: Guard time value |
|
This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bits 7:0 | PSC[7:0]: Prescaler value |
|
In IrDA Low-power and normal IrDA mode:
Bits [7:5] must be kept at reset value if Smartcard mode is used.
This bit field is reserved and must be kept at reset value when the Smartcard and IrDA |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BLEN[7:0] | RTO[23:16] |
RTO[15:0] |
|||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | BLEN[7:0]: Block Length |
|
This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. This value can be programmed after the start of the block reception (using the data |
|
| Bits 23:0 | RTO[23:0]: Receiver timeout value |
|
This bit-field gives the Receiver timeout value in terms of number of bit duration. This value must only be programmed once per received character. |
Note: RTOR can be written on the fly. If the new value is lower than or equal to the counter, the
RTOF flag is set.
This register is reserved and forced by hardware to “0x00000000” when the Receiver
timeout feature is not supported. Please refer to Section 34.4: USART implementation on
page 1243.
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXFRQ | RXFRQ | MMRQ | SBKRQ | ABRRQ |
| w | w | w | w | w |
| Bits 31:5 | Reserved, must be kept at reset value. |
| Bit 4 | TXFRQ: Transmit data flush request |
|
Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. |
|
| Bit 3 | RXFRQ: Receive data flush request |
|
Writing 1 to this bit clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition. |
|
| Bit 2 | MMRQ: Mute mode request |
|
Writing 1 to this bit puts the USART in mute mode and sets the RWU flag. |
|
| Bit 1 | SBKRQ: Send break request |
|
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. In the case the application needs to send the break character following all previously |
|
| Bit 0 | ABRRQ: Auto baud rate request |
|
Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. If the USART does not support the auto baud rate feature, this bit is reserved and must |
Address offset: 0x1C
Reset value: 0x0200 00C0
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | TCBGT | Res. | Res. | REACK | TEACK | WUF | RWU | SBKF | CMF | BUSY |
ABRF | ABRE | Res. | EOBF | RTOF | CTS | CTSIF | LBDF | TXE | TC | RXNE | IDLE | ORE | NF | FE | PE |
| r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:26 | Reserved, must be kept at reset value. |
| Bit 25 | TCBGT: Transmission complete before guard time completion. |
|
This bit is used in Smartcard mode. It is set by hardware if the transmission of a frame containing data has completed successfully (no NACK received from the card) and before the guard time has elapsed (contrary to the TC flag which is set when the guard time has elapsed). If the USART does not support the Smartcard mode, this bit is reserved and must be |
|
| Bits 24:23 | Reserved, must be kept at reset value. |
| Bit 22 | REACK: Receive enable acknowledge flag |
|
This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. When the wakeup from Stop mode is supported, the REACK flag can be used to verify that the USART is ready for reception before entering Stop mode. |
|
| Bit 21 | TEACK: Transmit enable acknowledge flag |
|
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. |
|
| Bit 20 | WUF: Wakeup from Stop mode flag |
|
This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register.
When UESM is cleared, WUF flag is also cleared.
The WUF interrupt is active only in Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and |
|
| Bit 19 | RWU: Receiver wakeup from Mute mode |
|
This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. |
|
| Bit 18 | SBKF: Send break flag |
|
This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_RQR register. It is automatically reset by hardware during the stop bit of break transmission. |
|
| Bit 17 | CMF: Character match flag |
|
This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register. 0: No Character match detected |
|
| Bit 16 | BUSY: Busy flag |
|
This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 0: USART is idle (no reception) |
|
| Bit 15 | ABRF: Auto baud rate flag |
|
This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) If the USART does not support the auto baud rate feature, this bit is reserved and kept |
|
| Bit 14 | ABRE: Auto baud rate error |
|
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) If the USART does not support the auto baud rate feature, this bit is reserved and kept |
|
| Bit 13 | Reserved, must be kept at reset value. |
| Bit 12 | EOBF: End of block flag |
|
This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. If Smartcard mode is not supported, this bit is reserved and kept at reset value. Please |
|
| Bit 11 | RTOF: Receiver timeout |
|
This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR1 register.
If a time equal to the value programmed in RTOR register separates 2 characters, The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has If the USART does not support the Receiver timeout feature, this bit is reserved and |
|
| Bit 10 | CTS: CTS flag |
|
This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. 0: CTS line set If the hardware flow control feature is not supported, this bit is reserved and kept at |
|
| Bit 9 | CTSIF: CTS interrupt flag |
|
This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. If the hardware flow control feature is not supported, this bit is reserved and kept at |
|
| Bit 8 | LBDF: LIN break detection flag |
|
This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. If the USART does not support LIN mode, this bit is reserved and kept at reset value. |
|
| Bit 7 | TXE: Transmit data register empty |
|
This bit is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by a write to the USART_TDR register.
This bit is used during single buffer transmission.
|
|
| Bit 6 | TC: Transmission complete |
|
This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register.
If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
|
|
| Bit 5 | RXNE: Read data register not empty |
|
This bit is set by hardware when the content of the RDR shift register has been transferred to the USART_RDR register. It is cleared by a read to the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 register. |
|
| Bit 4 | IDLE: Idle line detected |
|
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. 0: No Idle line is detected
The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line If mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), |
|
| Bit 3 | ORE: Overrun error |
|
This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register.
When this bit is set, the RDR register content is not lost but the shift register is This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in |
|
| Bit 2 | NF: START bit Noise detection flag |
|
This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. This bit does not generate an interrupt as it appears at the same time as the RXNE bit When the line is noise-free, the NF flag can be disabled by programming the ONEBIT |
|
| Bit 1 | FE: Framing error |
|
This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. |
|
| Bit 0 | PE: Parity error |
|
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. |
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WUCF | Res. | Res. | CMCF | Res. |
Res. | Res. | Res. | EOBCF | RTOCF | Res. | CTSCF | LBDCF | TCBGT CF |
TCCF | Res. | IDLECF | ORECF | NCF | FECF | PECF |
| rc_w1 | rc_w1 |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | WUCF: Wakeup from Stop mode clear flag |
|
Writing 1 to this bit clears the WUF flag in the USART_ISR register. If the USART does not support the wakeup from Stop feature, this bit is reserved and |
|
| Bits 19:18 | Reserved, must be kept at reset value. |
| Bit 17 | CMCF: Character match clear flag |
|
Writing 1 to this bit clears the CMF flag in the USART_ISR register. |
|
| Bits 16:13 | Reserved, must be kept at reset value. |
| Bit 12 | EOBCF: End of block clear flag |
|
Writing 1 to this bit clears the EOBF flag in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept |
|
| Bit 11 | RTOCF: Receiver timeout clear flag |
|
Writing 1 to this bit clears the RTOF flag in the USART_ISR register. If the USART does not support the Receiver timeout feature, this bit is reserved and |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bit 9 | CTSCF: CTS clear flag |
|
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. If the hardware flow control feature is not supported, this bit is reserved and must be |
|
| Bit 8 | LBDCF: LIN break detection clear flag |
|
Writing 1 to this bit clears the LBDF flag in the USART_ISR register. If LIN mode is not supported, this bit is reserved and must be kept at reset value. |
|
| Bit 7 | TCBGTCF: Transmission completed before guard time clear flag |
|
Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. If the USART does not support SmartCard mode, this bit is reserved and forced by |
|
| Bit 6 | TCCF: Transmission complete clear flag |
|
Writing 1 to this bit clears the TC flag in the USART_ISR register. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | IDLECF: Idle line detected clear flag |
|
Writing 1 to this bit clears the IDLE flag in the USART_ISR register. |
|
| Bit 3 | ORECF: Overrun error clear flag |
|
Writing 1 to this bit clears the ORE flag in the USART_ISR register. |
|
| Bit 2 | NCF: Noise detected clear flag |
|
Writing 1 to this bit clears the NF flag in the USART_ISR register. |
|
| Bit 1 | FECF: Framing error clear flag |
|
Writing 1 to this bit clears the FE flag in the USART_ISR register. |
|
| Bit 0 | PECF: Parity error clear flag |
|
Writing 1 to this bit clears the PE flag in the USART_ISR register. |
Address offset: 0x24
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | RDR[8:0] |
||||||||
| r | r | r | r | r | r | r | r | r |
|||||||||||||||||||||||
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bits 8:0 | RDR[8:0]: Receive data value |
|
Contains the received data character. |
Address offset: 0x28
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TDR[8:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||||
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bits 8:0 | TDR[8:0]: Transmit data value |
|
Contains the data character to be transmitted. This register must be written only when TXE=1. |
The table below gives the USART register map and reset values.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
USART_CR1
|
Res. | Res. | Res. | M1 | EOBIE | RTOIE | DEAT4 | DEAT3 | DEAT2 | DEAT1 | DEAT0 | DEDT4 | DEDT3 | DEDT2 | DEDT1 | DEDT0 | OVER8 | CMIE | MME | M0 | WAKE | PCE | PS | PEIE | TXEIE | TCIE | RXNEIE | IDLEIE | TE | RE | UESM | UE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x04 |
USART_CR2 | ADD[7:4] | ADD[3:0] |
RTOEN | ABRMOD1 | ABRMOD0 | ABREN | MSBFIRST | DATAINV | TXINV | RXINV | SWAP | LINEN | STOP [1:0] |
CLKEN | CPOL | CPHA | LBCL | Res. | LBDIE | LBDL | ADDM7 | Res. | Res. | Res. | Res. | |||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x08 |
USART_CR3
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TCBGTIE | UCESM | WUFIE | WUS | SCARCNT2:0] | Res. | DEP | DEM | DDRE | OVRDIS | ONEBIT | CTSIE | CTSE | RTSE | DMAT | DMAR | SCEN | NACK | HDSEL | IRLP | IREN | EIE | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0C |
USART_BRR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BRR[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x10 |
USART_GTPR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GT[7:0] | PSC[7:0] |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x14 |
USART_RTOR | BLEN[7:0] | RTO[23:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x18 |
USART_RQR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXFRQ | RXFRQ | MMRQ | SBKRQ | ABRRQ |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x1C |
USART_ISR
|
Res. | Res. | Res. | Res. | Res. | Res. | TCBGT | Res. | Res. | REACK | TEACK | WUF | RWU | SBKF | CMF | BUSY | ABRF | ABRE | Res. | EOBF | RTOF | CTS | CTSIF | LBDF | TXE | TC | RXNE | IDLE | ORE | NF | FE | PE |
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x20 |
USART_ICR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | WUCF | Res. | Res. | CMCF | Res. | Res. | Res. | Res. | EOBCF | RTOCF | Res. | CTSCF | LBDCF | TCBGTCF | TCCF | Res. | IDLECF | ORECF | NCF | FECF | PECF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x24 |
USART_RDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RDR[8:0] |
||||||||
| Reset value | X | X | X | X | X | X | X | X | X | ||||||||||||||||||||||||
| 0x28 |
USART_TDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TDR[8:0] |
||||||||
| Reset value | X | X | X | X | X | X | X | X | X |
||||||||||||||||||||||||
Refer to Section 2.2 on page 75 for the register boundary addresses.
The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I2S audio protocol. SPI or I2S mode is selectable by software. SPI Motorola mode is selected by default after a device reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration.
The Inter-IC sound (I2S) protocol is also a synchronous serial communication interface.It can operate in slave or master mode with half-duplex communication. Full-duplex operations are possible by combining two I2S blocks. It can address four different audio standards including the Philips I2S standard, the MSB- and LSB-justified standards and the PCM standard.
This manual describes the SPI/I2S implementation in STM32F76xxx and STM32F77xxx devices.
| SPI Features(1) |
SPI1 | SPI2 | SPI3 | SPI4 | SPI5 | SPI6 |
|---|---|---|---|---|---|---|
| Hardware CRC calculation | X | X | X | X | X | X |
| Rx/Tx FIFO | X | X | X | X | X | X |
| NSS pulse mode | X | X | X | X | X | X |
| I2S mode | X | X | X | - | - | - |
| TI mode | X | X | X | X | X | X |
The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 405.
| (omitted) |
Four I/O pins are dedicated to SPI communication with external devices.
NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to either:
See Section 35.5.5: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave devices. The bus consists of at least two wires - one for the clock signal and the other for synchronous data transfer. Other signals can be added depending on the data exchange between SPI nodes and their slave select signal management.
The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management). Communication is always initiated by the master.
Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the shift registers of the master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the SCK clock edges provided by the master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line. When the data frame transfer is complete (all the bits are shifted) the information between the master and slave is exchanged.
| (omitted) |
Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the SPIx_CR1 register. In this configuration, one single cross connection line is used to link the shift registers of the master and slave together. During this communication, the data is synchronously shifted between the shift registers on the SCK clock edge in the transfer direction selected reciprocally by both master and slave with the BDIOE bit in their SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin are free for other application uses and act as GPIOs.
| (omitted) |
Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive-only using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is used for the transfer between the shift registers of the master and slave. The remaining MISO and MOSI pins pair is not used for communication and can be used as standard GPIOs.
| (omitted) |
Note: Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).
In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 409.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input. When this is done, a standard master and dedicated slave communication is established.
| (omitted) |
Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to overtake control on the bus, it switches itself into master mode and applies active level on the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus temporary returns back to passive slave mode waiting for next session start.
If potentially both nodes raised their mastering request at the same time a bus conflict event appears (see mode fault MODF event). Then the user can apply some simple arbitration process (e.g. to postpone next attempt by predefined different time-outs applied at both nodes).
| (omitted) |
In slave mode, the NSS works as a standard “chip select” input and lets the slave communicate with the master. In master mode, NSS can be used either as output or input. As an input it can prevent multimaster bus collision, and as an output it can drive a slave select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register:
| (omitted) |
During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format. To be able to communicate together, the master and slaves devices must follow the same communication format.
Clock phase and polarity controls
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of the clock when no data is being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state.
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge.
Figure 412, shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
| (omitted) |
Data frame format
The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set from 4-bit up to 16-bit length and the setting applies for both transmission and reception. Whatever the selected data frame size, read access to the FIFO must be aligned with the FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned into either a byte (if the data fits into a byte) or a half-word (see Figure 413). During communication, only bits within the data frame are clocked and transferred.
| (omitted) |
Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.
The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated sections. When a standard communication is to be initialized, perform these steps:
Note: (1) Step is not required in slave mode.
(2) Step is not required in TI mode.
(3) Step is not required in NSSP mode.
(4) The step is not required in slave mode except slave working at TI mode
It is recommended to enable the SPI slave before the master sends the clock. If not, undesired data transmission might occur. The data register of the slave must already contain data to be sent before starting communication with the master (either on the first edge of the communication clock, or before the end of the ongoing communication if the clock signal is continuous). The SCK signal must be settled at an idle state level corresponding to the selected polarity before the SPI slave is enabled.
The master at full-duplex (or in any transmit-only mode) starts to communicate when the SPI is enabled and TXFIFO is not empty, or with the next write to TXFIFO.
In any master receive only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), master starts to communicate and the clock starts running immediately after SPI is enabled.
For handling DMA, follow the dedicated section.
RXFIFO and TXFIFO
All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to work in a continuous flow, and prevents overruns when the data frame size is short. Each direction has its own FIFO called TXFIFO and RXFIFO. These FIFOs are used in all SPI modes except for receiver-only mode (slave or master) with CRC calculation enabled (see Section 35.5.14: CRC calculation).
The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame format (number of bits in the frame), access size performed on the FIFO data registers (8-bit or 16-bit), and whether or not data packing is used when accessing the FIFOs (see Section 35.5.13: TI mode).
A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has not been read yet. A write access to the SPIx_DR stores the written data in the TXFIFO at the end of a send queue. The read access must be always aligned with the RXFIFO threshold configured by the FRXTH bit in SPIx_CR2 register. FTLVL[1:0] and FRLVL[1:0] bits indicate the current occupancy level of both FIFOs.
A read access to the SPIx_DR register must be managed by the RXNE event. This event is triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is reached. When RXNE is cleared, RXFIFO is considered to be empty. In a similar way, write access of a data frame to be transmitted is managed by the TXE event. This event is triggered when the TXFIFO level is less than or equal to half of its capacity. Otherwise TXE is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up to four data frames, whereas TXFIFO can only store up to three when the data frame format is not greater than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames already stored in the TXFIFO when software tries to write more data in 16-bit mode into TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See Figure 415 through Figure 418.
Another way to manage the data exchange is to use DMA (see Communication using DMA
(direct memory addressing)).
If the next data is received when the RXFIFO is full, an overrun event occurs (see description of OVR flag at Section 35.5.10: SPI status flags). An overrun event can be polled or handled by an interrupt.
The BSY bit being set indicates ongoing transaction of a current data frame. When the clock signal runs continuously, the BSY flag stays set between data frames at master but becomes low for a minimum duration of one SPI clock at slave between each data frame transfer.
Sequence handling
A few data frames can be passed at single sequence to complete a message. When transmission is enabled, a sequence begins and continues while any data is present in the TXFIFO of the master. The clock signal is provided continuously by the master until TXFIFO becomes empty, then it stops waiting for additional data.
In receive-only modes, half-duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0, RXONLY=1) the master starts the sequence immediately when both SPI is enabled and receive-only mode is activated. The clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled by the master. The master receives data frames continuously up to this moment.
While the master can provide all the transactions in continuous mode (SCK signal is continuous) it has to respect slave capability to handle data flow and its content at anytime. When necessary, the master must slow down the communication and provide either a slower clock or separate frames or data sessions with sufficient delays. Be aware there is no underflow error signal for master or slave in SPI mode, and data from the slave is always transacted and processed by the master even if the slave could not prepare it correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to select just one of the slaves for communication. In a single slave system it is not necessary to control the slave with NSS, but it is often better to provide the pulse here too, to synchronize the slave with the beginning of each data sequence. NSS can be managed by both software and hardware (see Section 35.5.5: Slave select (NSS) pin management).
When the BSY bit is set it signifies an ongoing data frame transaction. When the dedicated frame transaction is finished, the RXNE flag is raised. The last bit is just sampled and the complete data frame is stored in the RXFIFO.
Procedure for disabling the SPI
When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops providing data for transmission. In this case, the clock stops after the last data transaction. Special care must be taken in packing mode when an odd number of data frames are transacted to prevent some dummy byte exchange (refer to Data packing section). Before the SPI is disabled in these modes, the user must follow standard disable procedure. When
the SPI is disabled at the master transmitter while a frame transaction is ongoing or next data frame is stored in TXFIFO, the SPI behavior is not guaranteed.
When the master is in any receive only mode, the only way to stop the continuous clock is to disable the peripheral by SPE=0. This must occur in specific time window within last data frame transaction just between the sampling time of its first bit and before its last bit transfer starts (in order to receive a complete number of expected data frames and to prevent any additional “dummy” data reading after the last valid data frame). Specific procedure must be followed when disabling SPI in this mode.
Data received but not read remains stored in RXFIFO when the SPI is disabled, and must be processed the next time the SPI is enabled, before starting a new sequence. To prevent having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the correct disabling procedure, or by initializing all the SPI registers with a software reset via the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the RCC_APBiRSTR registers).
Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to check if a transmission session is fully completed. This check can be done in specific cases, too, when it is necessary to identify the end of ongoing transactions, for example:
The correct disable procedure is (except when receive only mode is used):
The correct disable procedure for certain receive only modes is:
Note: If packing mode is used and an odd number of data frames with a format less than or equal
to 8 bits (fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] =
01, in order to generate the RXNE event to read the last odd data frame and to keep good
FIFO pointer alignment.
Data packing
When the data frame size fits into one byte (less than or equal to 8 bits), data packing is used automatically when any read or write 16-bit access is performed on the SPIx_DR register. The double data frame pattern is handled in parallel in this case. At first, the SPI operates using the pattern stored in the LSB of the accessed word, then with the other half stored in the MSB. Figure 414 provides an example of data packing mode sequence handling. Two data frames are sent after the single 16-bit access the SPIx_DR register of the transmitter. This sequence can generate just one RXNE event in the receiver if the RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The
RxFIFO threshold setting and the following read access must be always kept aligned at the receiver side, as data can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be handled. On the transmitter side, writing the last data frame of any odd sequence with an 8-
bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level for the last data frame received in the odd sequence of frames in order to generate the RXNE event.
| (omitted) |
Communication using DMA (direct memory addressing)
To operate at its maximum speed and to facilitate the data register read/write process required to avoid overrun, the SPI features a DMA capability, which implements a simple request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is set. Separate requests must be issued to the Tx and Rx buffers.
See Figure 415 through Figure 418.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA channel. In this case, the OVR flag is set because the data received is not read. When the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI communication is complete. This is required to avoid corrupting the last transmission before disabling the SPI or entering the Stop mode. The software must first wait until FTLVL[1:0]=00 and then until BSY=0.
When starting communication using DMA, to prevent DMA channel management raising error events, these steps must be followed in order:
To close communication it is mandatory to follow these steps in order:
Packing with DMA
If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2 register) packing mode is enabled/disabled automatically depending on the PSIZE value configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is equal to 16-bit and SPI data size is less than or equal to 8-bit, then packing mode is enabled. The DMA then automatically manages the write operations to the SPIx_DR register.
If data packing mode is used and the number of data to transfer is not a multiple of two, the LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the transmission or reception to serve the last DMA transfer (for more details refer to Data
packing on page 1322.)
Communication diagrams
Some typical timing schemes are explained in this section. These schemes are valid no matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No complete configuration of DMA streams is provided.
The following numbered notes are common for Figure 415 on page 1326 through Figure 418 on page 1329.
| (omitted) |
Assumptions for master full-duplex communication example:
If DMA is used:
See also : Communication diagrams on page 1325 for details about common assumptions and notes.
| (omitted) |
Assumptions for slave full-duplex communication example:
If DMA is used:
See also : Communication diagrams on page 1325 for details about common assumptions and notes.
| (omitted) |
Assumptions for master full-duplex communication with CRC example:
If DMA is used:
See also : Communication diagrams on page 1325 for details about common assumptions and notes.
| (omitted) |
Assumptions for master full-duplex communication in packed mode example:
If DMA is used:
See also : Communication diagrams on page 1325 for details about common assumptions and notes.
Three status flags are provided for the application to completely monitor the state of the SPI bus.
Tx buffer empty flag (TXE)
The TXE flag is set when transmission TXFIFO has enough space to store data to send. TXE flag is linked to the TXFIFO level. The flag goes high and stays high until the TXFIFO level is lower or equal to 1/2 of the FIFO depth. An interrupt can be generated if the TXEIE bit in the SPIx_CR2 register is set. The bit is cleared automatically when the TXFIFO level becomes greater than 1/2.
Rx buffer not empty (RXNE)
The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.
The RXNE is cleared by hardware automatically when the above conditions are no longer true.
Busy flag (BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the software can disable the SPI or its peripheral clock before entering a low-power mode which does not provide a clock for the peripheral. This avoids corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions:
Note: When the next transmission can be handled immediately by the master (e.g. if the master is
in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and
the BSY flag remains set to '1' between transfers on the master side. Although this is not the
case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the
BSY flags) to handle data transmission or reception operations.
An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the ERRIE bit.
Overrun flag (OVR)
An overrun condition occurs when data is received by a master or slave and the RXFIFO has not enough space to store this received data. This can happen if the software or the DMA did not have enough time to read the previously received data (stored in the RXFIFO) or when space for data storage is limited e.g. the RXFIFO is not available when CRC is enabled in receive only mode so in this case the reception buffer is limited into a single data frame buffer (see Section 35.5.14: CRC calculation).
When an overrun condition occurs, the newly received value does not overwrite the previous one in the RXFIFO. The newly received value is discarded and all data transmitted subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read access to the SPI_SR register.
Mode fault (MODF)
Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the MODF bit. Master mode fault affects the SPI interface in the following ways:
Use the following software sequence to clear the MODF bit:
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can be restored to their original state after this clearing sequence. As a security, hardware does not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the MODF bit cannot be set except as the result of a previous multimaster conflict.
CRC error (CRCERR)
This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRCR value. The flag is cleared by the software.
TI mode frame format error (FRE)
A TI mode frame format error is detected when an NSS pulse occurs during an ongoing communication when the SPI is operating in slave mode and configured to conform to the TI mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the next NSS pulse before starting a new transfer. The data may be corrupted since the error detection may result in the loss of two data bytes.
The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt is generated on the NSS error detection. In this case, the SPI should be disabled because data consistency is no longer guaranteed and communications should be reinitiated by the master when the slave SPI is enabled again.
This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is generated between two consecutive data frame transfers when NSS stays at high level for the duration of one clock period at least. This mode allows the slave to latch data. NSSP pulse mode is designed for applications with a single master-slave pair.
Figure 419 illustrates NSS pin management when NSSP pulse mode is enabled.
| (omitted) |
Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising
edge of SCK, and NSS assertion and deassertion refer to this sampling edge.
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2 registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO pin state changes to HiZ when the current transaction finishes (see Figure 420). Any baud rate can be used, making it possible to determine this moment with optimal flexibility. However, the baud rate is generally set to the external master clock baud rate. The delay for the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the
baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the formula:
t--b---a--u---d--_---r-a---t-e
- t--b---a--u---d--_---r-a---t-e
- 2 + 4× tpclk <trelease
< 2 + 6×
tpclk
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is set.
If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only mode uses a protocol with one more dummy data bit added after LSB. TI NSS pulse is generated above this dummy bit clock cycle instead of the LSB in each period.
This feature is not available for Motorola SPI communications (FRF bit set to 0).
Figure 420: TI mode transfer shows the SPI communication waveforms when TI mode is selected.
| (omitted) |
Two separate CRC calculators are implemented in order to check the reliability of transmitted and received data. The SPI offers CRC8 or CRC16 calculation independently of the frame data length, which can be fixed to 8-bit or 16-bit. For all the other data frame lengths, no CRC is available.
CRC principle
CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable polynomial on each bit. The calculation is processed on the sampling clock edge defined by the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked automatically at the end of the data block as well as for transfer managed by CPU or by the DMA. When a mismatch is detected between the CRC calculated internally on the received data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption error. The right procedure for handling the CRC calculation depends on the SPI configuration and the chosen transfer management.
Note: The polynomial value should only be odd. No even values are supported.
CRC transfer managed by CPU
Communication starts and continues normally until the last data frame has to be sent or received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1 register to indicate that the CRC frame transaction will follow after the transaction of the currently processed data frame. The CRCNEXT bit must be set before the end of the last data frame transaction. CRC calculation is frozen during CRC transaction.
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC mode only, the reception buffer has to be considered as a single 16-bit buffer used to receive only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two more frames are necessary to send the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register. Software has to check the CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the SPIx_DR register in order to clear the RXNE flag.
CRC transfer managed by DMA
When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication is automatic (with the exception of reading CRC data in receive only mode). The CRCNEXT bit does not have to be handled by the software. The counter for the SPI transmission DMA channel has to be set to the number of data frames to transmit excluding the CRC frame. On the receiver side, the received CRC value is handled automatically by DMA at the end of the transaction but user must take care to flush out received CRC information from RXFIFO as it is always loaded into it. In full-duplex mode, the counter of the reception DMA channel can be set to the number of data frames to receive including the CRC, which means, for example, in the specific case of an 8-bit data frame checked by 16-bit CRC:
DMA_RX = Numb_of_data + 2
In receive only mode, the DMA reception channel counter should contain only the amount of data transferred, excluding the CRC calculation. Then based on the complete transfer from DMA, all the CRC values must be read back by software from FIFO as it works as a single buffer in this mode.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if corruption occurred during the transfer.
If packing mode is used, the LDMA_RX bit needs managing if the number of data is odd.
Resetting the SPIx_TXCRC and SPIx_RXCRC values
The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is sampled after a CRC phase. This allows the use of DMA circular mode (not available in receive-only mode) in order to transfer data without any interruption, (several data blocks covered by intermediate CRC checking phases).
If the SPI is disabled during a communication the following sequence must be followed:
Note: When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released. That is why
the CRC calculation can’t be used at NSS Pulse mode when NSS hardware mode should
be applied at slave normally (see more details at the product errata sheet).
At TI mode, despite the fact that clock phase and clock polarity setting is fixed and
independent on SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to be
kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by SPI disable sequence with re-enable the CRCEN bit
described above at both master and slave side, else CRC calculation can be corrupted at
this specific mode.
During SPI communication an interrupts can be generated by the following events:
Interrupts can be enabled and disabled separately.
| Interrupt event | Event flag | Enable Control bit |
|---|---|---|
| Transmit TXFIFO ready to be loaded | TXE | TXEIE |
| Data received in RXFIFO | RXNE | RXNEIE |
| Master Mode fault event | MODF |
ERRIE |
| Overrun error | OVR |
|
| TI frame format error | FRE |
|
| CRC protocol error | CRCERR |
The block diagram of the I2S is shown in Figure 421.
| (omitted) |
The SPI can function as an audio I2S interface when the I2S capability is enabled (by setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins, flags and interrupts as the SPI.
The I2S shares three common pins with the SPI:
An additional pin can be used when a master clock output is needed for some external audio devices:
The I2S uses its own clock generator to produce the communication clock when it is set in master mode. This clock generator is also the source of the master clock output. Two additional registers are available in I2S mode. One is linked to the clock generator configuration SPIx_I2SPR and the other one is a generic I2S configuration register SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I2S mode. Likewise, the SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are not used.
The I2S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.
Figure 422 shows how to perform full-duplex communications using two SPI/I2S instances. In this case, the WS and CK IOs of both SPI/I2S must be connected together.
For the master full-duplex mode, one of the SPI/I2S block must be programmed in master (I2SCFG = ‘10’ or ‘11’), and the other SPI/I2S block must be programmed in slave (I2SCFG = ‘00’ or ‘01’). The MCK can be generated or not, depending on the application needs.
For the slave full-duplex mode, both SPI/I2S blocks must be programmed in slave. One of them in the slave receiver (I2SCFG = ‘01’), and the other in the slave transmitter (I2SCFG = ‘00’). The master external device then provides the bit clock (CK) and the frame synchronization (WS).
Note that the full-duplex mode can be used for all the supported standards: I2S Philips,
MSB-justified, LSB-justified and PCM.
For the full-duplex mode, both SPI/I2S instances must use the same standard, with the same parameters: I2SMOD, I2SSTD, CKPOL, PCMSYNC, DATLEN and CHLEN must contain the same value on both instances.
| (omitted) |
The three-line bus has to handle only audio data generally time-multiplexed on two channels: the right channel and the left channel. However there is only one 16-bit register for transmission or reception. So, it is up to the software to write into the data register the appropriate value corresponding to each channel side, or to read the data from the data register and to identify the corresponding channel by checking the CHSIDE bit in the SPIx_SR register. Channel left is always sent first followed by the channel right (CHSIDE has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only one read/write operation).
The 24-bit and 32-bit data frames need two CPU read or write operations to/from the SPIx_DR register or two DMA operations if the DMA is preferred for the application. For 24-
bit data frame specifically, the 8 non-significant bits are extended to 32 bits with 0-bits (by hardware).
For all data formats and communication standards, the most significant bit is always sent first (MSB first).
The I2S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPIx_I2SCFGR register.
I
2S Philips standard
For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
| (omitted) |
Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver). The WS signal is also latched on the falling edge of CK.
| (omitted) |
This mode needs two write or read operations to/from the SPIx_DR register.
In transmission mode:
If 0x8EAA33 has to be sent (24-bit):
| (omitted) |
In reception mode:
If data 0x8EAA33 is received:
| (omitted) |
| (omitted) |
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S configuration phase, only one access to the SPIx_DR register is required. The 16 remaining bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the operation shown in Figure 428 is required.
| (omitted) |
For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first 16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents underrun or overrun conditions (depending on the direction of the data transfer).
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is the MSBit.
| (omitted) |
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge (for the receiver).
| (omitted) |
| (omitted) |
LSB justified standard
This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).
The sampling of the input and output signals is the same as for the I2S Philips standard.
| (omitted) |
| (omitted) |
In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA. The operations are shown below.
| (omitted) |
In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR register are required on each RXNE event.
| (omitted) |
| (omitted) |
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit), the operation shown in Figure 437 is required.
| (omitted) |
In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun or overrun conditions.
PCM standard
For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPIx_I2SCFGR register.
In PCM mode, the output signals (WS, SD) are sampled on the rising edge of CK signal. The input signals (WS, SD) are captured on the falling edge of CK.
Note that CK and WS are configured as output in MASTER mode.
| (omitted) |
For long frame synchronization, the WS signal assertion time is fixed to 13 bits in master mode.
For short frame synchronization, the WS synchronization signal is only one cycle long.
| (omitted) |
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.
The Figure 440 shows how the serial interface is handled in MASTER mode, when the SPI/I2S is enabled (via I2SE bit). It shows as well the effect of CKPOL on the generated signals.
| (omitted) |
In slave mode, the way the frame synchronization is detected, depends on the value of ASTRTEN bit.
If ASTRTEN = 0, when the audio interface is enabled (I2SE = 1), then the hardware waits for the appropriate transition on the incoming WS signal, using the CK signal.
The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The falling edge is detected by sampling first WS to 1 and then to 0, and vice-versa for the rising edge detection.
If ASTRTEN = 1, the user has to enable the audio interface before the WS becomes active. This means that the I2SE bit must be set to 1 when WS = 1 for I2S Philips standard, or when WS = 0 for other standards.
The I2S bit rate determines the data flow on the I2S data line and the I2S clock signal frequency.
I
2S bit rate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I2S bit rate is calculated as follows:
I
2S bit rate = 16 × 2 × fS
It will be: I2S bit rate = 32 x 2 x fS if the packet length is 32-bit wide.
| (omitted) |
When the master mode is configured, a specific action needs to be taken to properly program the linear divider in order to communicate with the desired audio frequency.
| (omitted) |
Figure 442 presents the communication clock architecture. The I2SxCLK clock is provided by the Reset and Clock Controller (RCC) of the product. The I2SxCLK clock can be asynchronous with respect to the SPI/I2S APB clock.
Warning:
In addition, it is mandatory to keep the I2SxCLK frequency
higher or equal to the APB clock used by the SPI/I2S block. If
this condition is not respected, the SPI/I2S will not work
properly.
The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range).
In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below:
For I2S modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
Fs = ---------------------------------------F-----I--2----S----x---C-----L----K
-----------------------------------------
256× (( 2 × I2SDIV) + ODD)
When the master clock is disabled (MCKOE bit cleared):
Fs = ------------------------------------------------------------------F-----I--2----S----x----C-----L---K-
--------------------------------------------------------------------
32× ( CHLEN+ 1 ) × ((2 × I2SDIV) + ODD)
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
For PCM modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
Fs = ---------------------------------------F-----I--2----S----x---C-----L----K
-----------------------------------------
128× (( 2 × I2SDIV) + ODD)
When the master clock is disabled (MCKOE bit cleared):
Fs = ------------------------------------------------------------------F-----I--2----S----x----C-----L---K-
--------------------------------------------------------------------16× ( CHLEN+ 1 ) × ((2 × I2SDIV) + ODD)
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
Where FS is the audio sampling frequency, and FI2SxCLKis the frequency of the kernel clock provided to the SPI/I2S block.
Note: Note that I2SDIV must be strictly higher than 1.
Table 229provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.
|
SYSCLK (MHz) |
Data length | I2SDIV | I2SODD | MCLK | Target fs (Hz) | Real fs (kHz) | Error |
|---|---|---|---|---|---|---|---|
| 48 | 16 | 8 | 0 | No | 96000 | 93750 | 2.3438% |
| 48 | 32 | 4 | 0 | No | 96000 | 93750 | 2.3438% |
| 48 | 16 | 15 | 1 | No | 48000 | 48387.0968 | 0.8065% |
| 48 | 32 | 8 | 0 | No | 48000 | 46875 | 2.3438% |
| 48 | 16 | 17 | 0 | No | 44100 | 44117.647 | 0.0400% |
| 48 | 32 | 8 | 1 | No | 44100 | 44117.647 | 0.0400% |
| 48 | 16 | 23 | 1 | No | 32000 | 31914.8936 | 0.2660% |
| 48 | 32 | 11 | 1 | No | 32000 | 32608.696 | 1.9022% |
| 48 | 16 | 34 | 0 | No | 22050 | 22058.8235 | 0.0400% |
| 48 | 32 | 17 | 0 | No | 22050 | 22058.8235 | 0.0400% |
| 48 | 16 | 47 | 0 | No | 16000 | 15957.4468 | 0.2660% |
| 48 | 32 | 23 | 1 | No | 16000 | 15957.447 | 0.2660% |
| 48 | 16 | 68 | 0 | No | 11025 | 11029.4118 | 0.0400% |
| 48 | 32 | 34 | 0 | No | 11025 | 11029.412 | 0.0400% |
| 48 | 16 | 94 | 0 | No | 8000 | 7978.7234 | 0.2660% |
| 48 | 32 | 47 | 0 | No | 8000 | 7978.7234 | 0.2660% |
| 48 | 16 | 2 | 0 | Yes | 48000 | 46875 | 2.3430% |
| 48 | 32 | 2 | 0 | Yes | 48000 | 46875 | 2.3430% |
| 48 | 16 | 2 | 0 | Yes | 44100 | 46875 | 6.2925% |
| 48 | 32 | 2 | 0 | Yes | 44100 | 46875 | 6.2925% |
| 48 | 16 | 3 | 0 | Yes | 32000 | 31250 | 2.3438% |
| 48 | 32 | 3 | 0 | Yes | 32000 | 31250 | 2.3438% |
| 48 | 16 | 4 | 1 | Yes | 22050 | 20833.333 | 5.5178% |
| 48 | 32 | 4 | 1 | Yes | 22050 | 20833.333 | 5.5178% |
| 48 | 16 | 6 | 0 | Yes | 16000 | 15625 | 2.3438% |
| 48 | 32 | 6 | 0 | Yes | 16000 | 15625 | 2.3438% |
| 48 | 16 | 8 | 1 | Yes | 11025 | 11029.4118 | 0.0400% |
| 48 | 32 | 8 | 1 | Yes | 11025 | 11029.4118 | 0.0400% |
| 48 | 16 | 11 | 1 | Yes | 8000 | 8152.17391 | 1.9022% |
| 48 | 32 | 11 | 1 | Yes | 8000 | 8152.17391 | 1.9022% |
The I2S can be configured in master mode. This means that the serial clock is generated on the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not, controlled by the MCKOE bit in the SPIx_I2SPR register.
Procedure
WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in SPIx_I2SPR is set.
Transmission sequence
The transmission sequence begins when a half-word is written into the Tx buffer.
Lets assume the first data written into the Tx buffer corresponds to the left channel data. When data are transferred from the Tx buffer to the shift register, TXE is set and data corresponding to the right channel have to be written into the Tx buffer. The CHSIDE flag indicates which channel is to be transmitted. It has a meaning when the TXE flag is set because the CHSIDE flag is updated when TXE goes high.
A full frame has to be considered as a left channel data transmission followed by a right channel data transmission. It is not possible to have a partial frame where only the left channel is sent.
The data half-word is parallel loaded into the 16-bit shift register during the first bit transmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is
set after each transfer from the Tx buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPIx_CR2 register is set.
For more details about the write operations depending on the I2S standard mode selected, refer to Section 35.7.3: Supported audio protocols).
To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission.
To switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.
Reception sequence
The operating mode is the same as for transmission mode except for the point 3 (refer to the procedure described in Section 35.7.6: I2S master mode), where the configuration should set the master reception mode through the I2SCFG[1:0] bits.
Whatever the data or channel length, the audio data are received by 16-bit packets. This means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the I
2S cell.
For more details about the read operations depending on the I2S standard mode selected, refer to Section 35.7.3: Supported audio protocols.
If data are received while the previously received data have not been read yet, an overrun is generated and the OVR flag is set. If the ERRIE bit is set in the SPIx_CR2 register, an interrupt is generated to indicate the error.
To switch off the I2S, specific actions are required to ensure that the I2S completes the transfer cycle properly without initiating a new data transfer. The sequence depends on the configuration of the data and channel lengths, and on the audio protocol mode selected. In the case of:
Note: The BSY flag is kept low during transfers.
For the slave configuration, the I2S can be configured in transmission or reception mode. The operating mode is following mainly the same rules as described for the I2S master configuration. In slave mode, there is no clock to be generated by the I2S interface. The clock and WS signals are input from the external master connected to the I2S interface. There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
Transmission sequence
The transmission sequence begins when the external master device sends the clock and when the NSS_WS signal requests the transfer of data. The slave has to be enabled before the external master starts the communication. The I2S data register has to be loaded before the master initiates the communication.
For the I2S, MSB justified and LSB justified modes, the first data item to be written into the data register corresponds to the data for the left channel. When the communication starts, the data are transferred from the Tx buffer to the shift register. The TXE flag is then set in order to request the right channel data to be written into the I2S data register.
The CHSIDE flag indicates which channel is to be transmitted. Compared to the master transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the external master. This means that the slave needs to be ready to transmit the first data before the clock is generated by the master. WS assertion corresponds to left channel transmitted first.
Note: The I2SE has to be written at least two PCLK cycles before the first clock of the master
comes on the CK line.
The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus) during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first. The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPIx_CR2 register is set.
Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.
For more details about the write operations depending on the I2S standard mode selected, refer to Section 35.7.3: Supported audio protocols.
To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. An underrun flag is set and an interrupt may be generated if the data are not written into the
SPIx_DR register before the first clock edge of the next data communication. This indicates to the software that the transferred data are wrong. If the ERRIE bit is set into the SPIx_CR2 register, an interrupt is generated when the UDR flag in the SPIx_SR register goes high. In this case, it is mandatory to switch off the I2S and to restart a data transfer starting from the left channel.
To switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and BSY = 0.
Reception sequence
The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in Section 35.7.7: I2S slave mode), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
Whatever the data length or the channel length, the audio data are received by 16-bit packets. This means that each time the RX buffer is full, the RXNE flag in the SPIx_SR register is set and an interrupt is generated if the RXNEIE bit is set in the SPIx_CR2 register. Depending on the data length and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the RX buffer.
The CHSIDE flag is updated each time data are received to be read from the SPIx_DR register. It is sensitive to the external WS line managed by the external master component.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
For more details about the read operations depending the I2S standard mode selected, refer to Section 35.7.3: Supported audio protocols.
If data are received while the preceding received data have not yet been read, an overrun is generated and the OVR flag is set. If the bit ERRIE is set in the SPIx_CR2 register, an interrupt is generated to indicate the error.
To switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving the last RXNE = 1.
Note: The external master components should have the capability of sending/receiving data in 16-
bit or 32-bit packets via an audio channel.
Three status flags are provided for the application to fully monitor the state of the I2S bus.
Busy flag (BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates the state of the communication layer of the I2S.
When BSY is set, it indicates that the I2S is busy communicating. There is one exception in master receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.
The BSY flag is useful to detect the end of a transfer if the software needs to disable the I2S. This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.
The BSY flag is set when a transfer starts, except when the I2S is in master receiver mode.
The BSY flag is cleared:
When communication is continuous:
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the
TXE and RXNE flags instead.
Tx buffer empty flag (TXE)
When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to be transmitted. It is also reset when the I2S is disabled (I2SE bit is reset).
RX buffer not empty (RXNE)
When set, this flag indicates that there are valid received data in the RX Buffer. It is reset when SPIx_DR register is read.
Channel Side flag (CHSIDE)
In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel side to which the data to transfer on SD has to belong. In case of an underrun error event in slave transmission mode, this flag is not reliable and I2S needs to be switched off and switched on before resuming the communication.
In reception mode, this flag is refreshed when data are received into SPIx_DR. It indicates from which channel side data have been received. Note that in case of error (like OVR) this flag becomes meaningless and the I2S should be reset by disabling and then enabling it (with configuration if it needs changing).
This flag has no meaning in the PCM standard (for both Short and Long frame modes).
When the OVR or UDR flag in the SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also set, an interrupt is generated. This interrupt can be cleared by reading the SPIx_SR status register (once the interrupt source has been cleared).
There are three error flags for the I2S cell.
Underrun flag (UDR)
In slave transmission mode this flag is set when the first clock for data transmission appears while the software has not yet loaded any value into SPIx_DR. It is available when the I2SMOD bit in the SPIx_I2SCFGR register is set. An interrupt may be generated if the ERRIE bit in the SPIx_CR2 register is set.
The UDR bit is cleared by a read operation on the SPIx_SR register.
Overrun flag (OVR)
This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in the SPIx_CR2 register.
In this case, the receive buffer contents are not updated with the newly received data from the transmitter device. A read operation to the SPIx_DR register returns the previous correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPIx_DR register followed by a read access to the SPIx_SR register.
Frame error flag (FRE)
This flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the external master is changing the WS line while the slave is not expecting this change. If the synchronization is lost, the following steps are required to recover from this state and resynchronize the external master device with the I2S slave device:
Desynchronization between master and slave devices may be due to noisy environment on the CK communication clock or on the WS frame synchronization line. An error interrupt can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by software when the status register is read.
In I2S mode, the DMA works in exactly the same way as it does in SPI mode. There is no difference except that the CRC feature is not available in I2S mode since there is no data transfer protection system.
Table 230 provides the list of I2S interrupts.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Transmit buffer empty flag | TXE | TXEIE |
| Receive buffer not empty flag | RXNE | RXNEIE |
| Overrun error | OVR |
ERRIE |
| Underrun error | UDR | |
| Frame error flag | FRE |
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access.
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BIDI MODE |
BIDI OE |
CRC EN |
CRC NEXT |
CRCL | RX ONLY |
SSM | SSI | LSB FIRST |
SPE | BR [2:0] | MSTR | CPOL | CPHA |
||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 15 | BIDIMODE: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. |
|
0: 2-line unidirectional data mode selected
This bit is not used in I2S mode.
|
|
| Bit 14 | BIDIOE: Output enable in bidirectional mode |
|
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode 0: Output disabled (receive-only mode) 1: Output enabled (transmit-only mode)
In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
This bit is not used in I2S mode.
|
|
| Bit 13 | CRCEN: Hardware CRC calculation enable |
|
0: CRC calculation disabled
This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
This bit is not used in I2S mode.
|
|
| Bit 12 | CRCNEXT: Transmit CRC next |
|
0: Next transmit value is from Tx buffer
This bit has to be written as soon as the last data is written in the SPIx_DR register.
This bit is not used in I2S mode.
|
|
| Bit 11 | CRCL: CRC length |
|
This bit is set and cleared by software to select the CRC length. 0: 8-bit CRC length
This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
This bit is not used in I2S mode. |
|
| Bit 10 | RXONLY: Receive only mode enabled. |
|
This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full-duplex (Transmit and receive)
This bit is not used in I2S mode.
|
|
| Bit 9 | SSM: Software slave management |
|
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. 0: Software slave management disabled This bit is not used in I2S mode and SPI TI mode. |
|
| Bit 8 | SSI: Internal slave select |
|
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. This bit is not used in I2S mode and SPI TI mode. |
|
| Bit 7 | LSBFIRST: Frame format |
|
0: data is transmitted / received with the MSB first
1. This bit should not be changed when communication is ongoing.
|
|
| Bit 6 | SPE: SPI enable |
|
0: Peripheral disabled
When disabling the SPI, follow the procedure described in Procedure for disabling the
This bit is not used in I2S mode.
|
|
| Bits 5:3 | BR[2:0]: Baud rate control |
|
000: fPCLK/2
These bits should not be changed when communication is ongoing.
This bit is not used in I2S mode.
|
|
| Bit 2 | MSTR: Master selection |
|
0: Slave configuration
This bit should not be changed when communication is ongoing.
This bit is not used in I2S mode. |
|
| Bit 1 | CPOL: Clock polarity |
|
0: CK to 0 when idle
This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
|
|
| Bit 0 | CPHA: Clock phase |
|
0: The first clock transition is the first data capture edge
This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
|
Address offset: 0x04
Reset value: 0x0700
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | LDMA _TX |
LDMA _RX |
FRXT H |
DS [3:0] | TXEIE | RXNEIE | ERRIE | FRF | NSSP | SSOE | TXDMAEN | RXDMAEN |
|||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | LDMA_TX: Last DMA transfer for transmission |
|
This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). 0: Number of data to transfer is even
Refer to Procedure for disabling the SPI on page 1321 if the CRCEN bit is set.
This bit is not used in I²S mode.
|
|
| Bit 13 | LDMA_RX: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). |
|
0: Number of data to transfer is even
Refer to Procedure for disabling the SPI on page 1321 if the CRCEN bit is set.
This bit is not used in I²S mode.
|
|
| Bit 12 | FRXTH: FIFO reception threshold |
|
This bit is used to set the threshold of the RXFIFO that triggers an RXNE event 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) This bit is not used in I²S mode. |
|
| Bits 11:8 | DS [3:0]: Data size |
|
These bits configure the data length for SPI transfers: 0000: Not used If software attempts to write one of the “Not used” values, they are forced to the value “0111”(8-
This bit is not used in I²S mode.
|
|
| Bit 7 | TXEIE: Tx buffer empty interrupt enable |
|
0: TXE interrupt masked 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. |
|
| Bit 6 | RXNEIE: RX buffer not empty interrupt enable |
|
0: RXNE interrupt masked 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. |
|
| Bit 5 | ERRIE: Error interrupt enable |
|
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). 0: Error interrupt is masked |
|
| Bit 4 | FRF: Frame format |
|
0: SPI Motorola mode
This bit must be written only when the SPI is disabled (SPE=0).
This bit is not used in I2S mode.
|
|
| Bit 3 | NSSP: NSS pulse management |
|
This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’. 0: No NSS pulse
1. This bit must be written only when the SPI is disabled (SPE=0).
|
|
| Bit 2 | SSOE: SS output enable |
|
0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration This bit is not used in I2S mode and SPI TI mode. |
|
| Bit 1 | TXDMAEN: Tx buffer DMA enable |
|
When this bit is set, a DMA request is generated whenever the TXE flag is set. 0: Tx buffer DMA disabled |
|
| Bit 0 | RXDMAEN: Rx buffer DMA enable |
|
When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0: Rx buffer DMA disabled |
Address offset: 0x08
Reset value: 0x0002
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | FTLVL[1:0] | FRLVL[2:0] | FRE | BSY | OVR | MODF | CRC ERR |
UDR | CHSIDE | TXE | RXNE |
||
| r | r | r | r | r | r | r | r | rc_w0 | r | r |
|||||
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:11 | FTLVL[1:0]: FIFO Transmission Level |
|
These bits are set and cleared by hardware. 00: FIFO empty
These bits are not used in I²S mode.
|
|
| Bits 10:9 | FRLVL[1:0]: FIFO reception level |
|
These bits are set and cleared by hardware. 00: FIFO empty These bits are not used in I²S mode and in SPI receive-only mode while CRC |
|
| Bit 8 | FRE: Frame format error |
|
This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 35.5.11: SPI This flag is set by hardware and reset when SPIx_SR is read by software. 0: No frame format error |
|
| Bit 7 | BSY: Busy flag |
|
0: SPI (or I2S) not busy The BSY flag must be used with caution: refer to Section 35.5.10: SPI status flags and |
|
| Bit 6 | OVR: Overrun flag |
|
0: No overrun occurred |
|
| Bit 5 | MODF: Mode fault |
|
0: No mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault This bit is not used in I2S mode. |
|
| Bit 4 | CRCERR: CRC error flag |
|
0: CRC value received matches the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0.
This bit is not used in I2S mode.
|
|
| Bit 3 | UDR: Underrun flag |
|
0: No underrun occurred This flag is set by hardware and reset by a software sequence. Refer to I
This bit is not used in SPI mode.
|
|
| Bit 2 | CHSIDE: Channel side |
|
0: Channel Left has to be transmitted or has been received
This bit is not used in SPI mode. It has no significance in PCM mode.
|
|
| Bit 1 | TXE: Transmit buffer empty |
|
0: Tx buffer not empty |
|
| Bit 0 | RXNE: Receive buffer not empty |
|
0: Rx buffer empty |
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DR[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | DR[15:0]: Data register |
|
Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 35.5.9: Data transmission and reception procedures). Data is always right-aligned. Unused bits are ignored when writing to the register, and |
Address offset: 0x10
Reset value: 0x0007
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CRCPOLY[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 15:0 | CRCPOLY[15:0]: CRC polynomial register |
|
This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. |
Note: The polynomial value should be odd only. No even value is supported.
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RxCRC[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 15:0 | RXCRC[15:0]: Rx CRC register |
|
When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard.
A read to this register when the BSY Flag is set could return an incorrect value.
These bits are not used in I2S mode.
|
Address offset: 0x18
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TxCRC[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 15:0 | TxCRC[15:0]: Tx CRC register |
|
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard.
A read to this register when the BSY flag is set could return an incorrect value.
These bits are not used in I2S mode. |
Address offset: 0x1C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | ASTR TEN |
I2SMOD | I2SE | I2SCFG | PCMSYNC | Res. | I2SSTD | CKPOL | DATLEN | CHLEN |
|||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||
| Bits 15:13 | Reserved: Forced to 0 by hardware |
| Bit 12 | ASTRTEN: Asynchronous start enable. |
|
0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal.
The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, The appropriate level is a LOW level on WS signal when I2S Philips Standard is used, or a
Please refer to Section 35.7.4: Start-up description for additional information.
|
|
| Bit 11 | I2SMOD: I2S mode selection |
|
0: SPI mode is selected
This bit should be configured when the SPI is disabled.
|
|
| Bit 10 | I2SE: I2S enable |
|
0: I2S peripheral is disabled
This bit is not used in SPI mode.
|
|
| Bits 9:8 | I2SCFG: I2S configuration mode |
|
00: Slave - transmit
These bits should be configured when the I2S is disabled.
They are not used in SPI mode.
|
|
| Bit 7 | PCMSYNC: PCM frame synchronization |
|
0: Short frame synchronization
This bit has a meaning only if I2SSTD = 11 (PCM standard is used).
It is not used in SPI mode.
|
|
| Bit 6 | Reserved: forced at 0 by hardware |
| Bits 5:4 | I2SSTD: I2S standard selection |
|
00: I2S Philips standard. For more details on I2S standards, refer to Section 35.7.3 on page 1338
For correct operation, these bits should be configured when the I2S is disabled.
They are not used in SPI mode.
|
|
| Bit 3 | CKPOL: Inactive state clock polarity |
|
0: I2S clock inactive state is low level
For correct operation, this bit should be configured when the I2S is disabled.
It is not used in SPI mode.
The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and |
|
| Bits 2:1 | DATLEN: Data length to be transferred |
|
00: 16-bit data length
For correct operation, these bits should be configured when the I2S is disabled.
They are not used in SPI mode.
|
|
| Bit 0 | CHLEN: Channel length (number of bits per audio channel) |
|
0: 16-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in.
For correct operation, this bit should be configured when the I2S is disabled.
It is not used in SPI mode. |
Address offset: 0x20
Reset value: 0x0002
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | MCKOE | ODD | I2SDIV[7:0] |
| rw | rw | rw |
| Bits 15:10 | Reserved: Forced to 0 by hardware |
| Bit 9 | MCKOE: Master clock output enable |
|
0: Master clock output is disabled
This bit should be configured when the I2S is disabled. It is used only when the I2S is in master
It is not used in SPI mode.
|
|
| Bit 8 | ODD: Odd factor for the prescaler |
|
0: Real divider value is = I2SDIV *2 Refer to Section 35.7.4 on page 1345
This bit should be configured when the I2S is disabled. It is used only when the I2S is in master
It is not used in SPI mode.
|
|
| Bits 7:0 | I2SDIV[7:0]: I2S linear prescaler |
|
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 35.7.4 on page 1345
These bits should be configured when the I2S is disabled. They are used only when the I2S is They are not used in SPI mode. |
Table 231 shows the SPI/I2S register map and reset values.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
SPIx_CR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BIDIMODE | BIDIOE | CRCEN | CRCNEXT | CRCL | RXONLY | SSM | SSI | LSBFIRST | SPE | BR [2:0] |
MSTR | CPOL | CPHA | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x04 |
SPIx_CR2
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LDMA_TX | LDMA_RX | FRXTH | DS[3:0] |
TXEIE | RXNEIE | ERRIE | FRF | NSSP | SSOE | TXDMAEN | RXDMAEN | |||
| Reset value | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x08 |
SPIx_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FTLVL[1:0] | FRLVL[1:0] | FRE | BSY | OVR | MODF | CRCERR | UDR | CHSIDE | TXE | RXNE | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
||||||||||||||||||||
| 0x0C |
SPIx_DR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DR[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x10 |
SPIx_CRCPR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CRCPOLY[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
|||||||||||||||||
| 0x14 |
SPIx_RXCRCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RxCRC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x18 |
SPIx_TXCRCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TxCRC[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x1C |
SPIx_I2SCFGR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ASTRTEN | I2SMOD | I2SE | I2SCFG | PCMSYNC | Res. | I2SSTD | CKPOL | DATLEN | CHLEN | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x20 |
SPIx_I2SPR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCKOE | ODD | I2SDIV |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted. I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC’97 protocols may be addressed for example. SPDIF output is offered when the audio block is configured as a transmitter.
To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller.
The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or not (with respect to the other one).
The SAI can be connected with other SAIs to work synchronously.
Figure 443 shows the SAI block diagram while Table 232 and Table 233 list SAI internal and external signals.
| (omitted) |
The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine. Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by DMA in order to leave the CPU free during the communication. Each audio block is independent. They can be synchronous with each other.
An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given audio block in the SAI. Some of these pins can be shared if the two sub-blocks are declared as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can be output, or not, depending on the application, the decoder requirement and whether the audio block is configured as the master.
If one SAI is configured to operate synchronously with another one, even more I/Os can be freed (except for pins SD_x).
The functional state machine can be configured to address a wide range of audio protocols. Some registers are present to set-up the desired protocols (audio frame waveform generator).
The audio sub-block can be a transmitter or receiver, in master or slave mode. The master mode means the SCK_x bit clock and the frame synchronization signal are generated from the SAI, whereas in slave mode, they come from another external or internal master. There is a particular case for which the FS signal direction is not directly linked to the master or slave mode definition. In AC’97 protocol, it will be an SAI output even if the SAI (link controller) is set-up to consume the SCK clock (and so to be in Slave mode).
Note: For ease of reading of this section, the notation SAI_x refers to SAI_A or SAI_B, where ‘x’
represents the SAI A or B sub-block.
| Internal signal name | Signal type | Description |
|---|---|---|
| sai_a_gbl_it/ sai_b_gbl_it |
Output | Audio block A and B global interrupts. |
| sai_a_dma, sai_b_dma | Input/output | Audio block A and B DMA acknowledges and requests. |
| sai_sync_out_sck, sai_sync_out_fs | Output | Internal clock and frame synchronization output signals exchanged with other SAI blocks. |
| sai_sync_in_sck, sai_sync_in_fs | Input | Internal clock and frame synchronization input signals exchanged with other SAI blocks. |
| sai_a_ker_ck/ sai_b_ker_ck |
Input | Audio block A/B kernel clock. |
| sai_pclk | Input | APB clock. |
| Name | Signal type | Comments |
|---|---|---|
| SAI_SCK_A/B | Input/output | Audio block A/B bit clock. |
| SAI_MCLK_A/B | Output | Audio block A/B master clock. |
| SAI_SD_A/B | Input/output | Data line for block A/B. |
| SAI_FS_A/B | Input/output | Frame synchronization line for audio block A/B. |
Each audio sub-block of the SAI can be configured to be master or slave via MODE bits in the SAI_xCR1 register of the selected audio block.
Master mode
In master mode, the SAI delivers the timing signals to the external connected device:
Both SCK_x, FS_x and MCLK_x are configured as outputs.
Slave mode
The SAI expects to receive timing signals from an external device.
In slave mode, MCLK_x pin is not used and can be assigned to another function.
It is recommended to enable the slave device before enabling the master.
Configuring and enabling SAI modes
Each audio sub-block can be independently defined as a transmitter or receiver through the MODE bit in the SAI_xCR1 register of the corresponding audio block. As a result, SAI_SD_x pin will be respectively configured as an output or an input.
Two master audio blocks in the same SAI can be configured with two different MCLK and SCK clock frequencies. In this case they have to be configured in asynchronous mode.
Each of the audio blocks in the SAI are enabled by SAIEN bit in the SAI_xCR1 register. As soon as this bit is active, the transmitter or the receiver is sensitive to the activity on the clock line, data line and synchronization line in slave mode.
In master TX mode, enabling the audio block immediately generates the bit clock for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. After the FIFO receives the first data to transmit, this data is output to external slaves. If there is no data to transmit in the FIFO, 0 values are then sent in the audio frame with an underrun flag generation.
In slave mode, the audio frame starts when the audio block is enabled and when a start of frame is detected.
In Slave TX mode, no underrun event is possible on the first frame after the audio block is enabled, because the mandatory operating sequence in this case is:
There are two levels of synchronization, either at audio sub-block level or at SAI level.
Internal synchronization
An audio sub-block can be configured to operate synchronously with the second audio sub-block in the same SAI. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication. The audio block configured in synchronous mode sees its own SCK_x, FS_x, and MCLK_x pins released back as GPIOs while the audio block configured in asynchronous mode is the one for which FS_x and SCK_x ad MCLK_x I/O pins are relevant (if the audio block is considered as master).
Typically, the audio block in synchronous mode can be used to configure the SAI in full duplex mode. One of the two audio blocks can be configured as a master and the other as slave, or both as slaves with one asynchronous block (corresponding SYNCEN[1:0] bits set to 00 in SAI_xCR1) and one synchronous block (corresponding SYNCEN[1:0] bits set to 01 in the SAI_xCR1).
Note: Due to internal resynchronization stages, PCLK APB frequency must be higher than twice
the bit rate clock frequency.
External synchronization
The audio sub-blocks can also be configured to operate synchronously with another SAI. This can be done as follow:
Note: SYNCIN[1:0] and SYNCOUT[1:0] bits are located into the SAI_GCR register, and SYNCEN
bits into SAI_xCR1 register.
If both audio sub-blocks in a given SAI need to be synchronized with another SAI, it is possible to choose one of the following configurations:
The following table shows how to select the proper synchronization signal depending on the SAI block used. For example SAI2 can select the synchronization from SAI1 by setting SAI2 SYNCIN to 0. If SAI1 wants to select the synchronization coming from SAI2, SAI1 SYNCIN must be set to 1. Positions noted as ‘Res.’ shall not be used.
| Block instance | SYNCIN= 3 | SYNCIN= 2 | SYNCIN= 1 | SYNCIN= 0 |
|---|---|---|---|---|
| SAI1 | Res. | Res. | SAI2 sync | Res. |
| SAI2 | Res. | Res. | Res. | SAI1 sync |
The audio frame can target different data sizes by configuring bit DS[2:0] in the SAI_xCR1 register. The data sizes may be 8, 10, 16, 20, 24 or 32 bits. During the transfer, either the MSB or the LSB of the data are sent first, depending on the configuration of bit LSBFIRST in the SAI_xCR1 register.
The FS signal acts as the Frame synchronization signal in the audio frame (start of frame). The shape of this signal is completely configurable in order to target the different audio protocols with their own specificities concerning this Frame synchronization behavior. This reconfigurability is done using register SAI_xFRCR. Figure 444 illustrates this flexibility.
| (omitted) |
In AC’97 mode or in SPDIF mode (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01 in the SAI_xCR1 register), the frame synchronization shape is forced to match the AC’97 protocol. The SAI_xFRCR register value is ignored.
Each audio block is independent and consequently each one requires a specific configuration.
Frame length
Master mode
The audio frame length can be configured to up to 256 bit clock cycles, by setting FRL[7:0] field in the SAI_xFRCR register.
If the frame length is greater than the number of declared slots for the frame, the remaining bits to transmit will be extended to 0 or the SD line will be released to HI-z depending the state of bit TRIS in the SAI_xCR2 register (refer to FS signal role). In reception mode, the remaining bit is ignored.
If bit NODIV is cleared, (FRL+1) must be equal to a power of 2, from 8 to 256, to ensure that an audio frame contains an integer number of MCLK pulses per bit clock cycle.
If bit NODIV is set, the (FRL+1) field can take any value from 8 to 256. Refer to Section 36.3.8: SAI clock generator”.
Slave mode
The audio frame length is mainly used to specify to the slave the number of bit clock cycles per audio frame sent by the external master. It is used mainly to detect from the master any anticipated or late occurrence of the Frame synchronization signal during an on-going audio frame. In this case an error will be generated. For more details refer to Section 36.3.13: Error flags.
In slave mode, there are no constraints on the FRL[7:0] configuration in the SAI_xFRCR register.
The number of bits in the frame is equal to FRL[7:0] + 1.
The minimum number of bits to transfer in an audio frame is 8.
Frame synchronization polarity
FSPOL bit in the SAI_xFRCR register sets the active polarity of the FS pin from which a frame is started. The start of frame is edge sensitive.
In slave mode, the audio block waits for a valid frame to start transmitting or receiving. Start of frame is synchronized to this signal. It is effective only if the start of frame is not detected during an ongoing communication and assimilated to an anticipated start of frame (refer to Section 36.3.13: Error flags).
In master mode, the frame synchronization is sent continuously each time an audio frame is complete until the SAIEN bit in the SAI_xCR1 register is cleared. If no data are present in the FIFO at the end of the previous audio frame, an underrun condition will be managed as described in Section 36.3.13: Error flags), but the audio communication flow will not be interrupted.
Frame synchronization active level length
The FSALL[6:0] bits of the SAI_xFRCR register allow configuring the length of the active level of the Frame synchronization signal. The length can be set from 1 to 128 bit clock cycles.
As an example, the active length can be half of the frame length in I2S, LSB or MSB-justified modes, or one-bit wide for PCM/DSP or TDM mode.
Frame synchronization offset
Depending on the audio protocol targeted in the application, the Frame synchronization signal can be asserted when transmitting the last bit or the first bit of the audio frame (this is the case in I2S standard protocol and in MSB-justified protocol, respectively). FSOFF bit in the SAI_xFRCR register allows to choose one of the two configurations.
FS signal role
The FS signal can have a different meaning depending on the FS function. FSDEF bit in the SAI_xFRCR register selects which meaning it will have:
When the FS signal is considered as a start of frame and channel side identification within the frame, the number of declared slots must be considered to be half the number for the left channel and half the number for the right channel. If the number of bit clock cycles on half audio frame is greater than the number of slots dedicated to a channel side, and TRIS = 0, 0 is sent for transmission for the remaining bit clock cycles in the SAI_xCR2 register. Otherwise if TRIS = 1, the SD line is released to HI-Z. In reception mode, the remaining bit clock cycles are not considered until the channel side changes.
| (omitted) |
If FSDEF bit in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then:
| (omitted) |
The FS signal is not used when the audio block in transmitter mode is configured to get the SPDIF output on the SD line. The corresponding FS I/O will be released and left free for other purposes.
The slot is the basic element in the audio frame. The number of slots in the audio frame is equal to NBSLOT[3:0] + 1.
The maximum number of slots per audio frame is fixed at 16.
For AC’97 protocol or SPDIF (when bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the number of slots is automatically set to target the protocol specification, and the value of NBSLOT[3:0] is ignored.
Each slot can be defined as a valid slot, or not, by setting SLOTEN[15:0] bits of the SAI_xSLOTR register.
When a invalid slot is transferred, the SD data line is either forced to 0 or released to HI-z depending on TRIS bit configuration (refer to Output data line management on an inactive
slot) in transmitter mode. In receiver mode, the received value from the end of this slot is ignored. Consequently, there will be no FIFO access and so no request to read or write the FIFO linked to this inactive slot status.
The slot size is also configurable as shown in Figure 447. The size of the slots is selected by setting SLOTSZ[1:0] bits in the SAI_xSLOTR register. The size is applied identically for each slot in an audio frame.
| (omitted) |
It is possible to choose the position of the first data bit to transfer within the slots. This offset is configured by FBOFF[4:0] bits in the SAI_xSLOTR register. 0 values will be injected in transmitter mode from the beginning of the slot until this offset position is reached. In reception, the bit in the offset phase is ignored. This feature targets the LSB justified protocol (if the offset is equal to the slot size minus the data size).
| (omitted) |
It is mandatory to respect the following conditions to avoid bad SAI behavior:
FBOFF ≤(SLOTSZ - DS),
DS ≤SLOTSZ,
NBSLOT x SLOTSZ ≤FRL (frame length),
The number of slots must be even when bit FSDEF in the SAI_xFRCR register is set.
In AC’97 and SPDIF protocol (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the slot size is automatically set as defined in Section 36.3.10: AC’97 link controller.
Each audio block has its own clock generator that makes these two blocks completely independent. There is no difference in terms of functionality between these two clock generators.
When the audio block is configured as Master, the clock generator provides the communication clock (the bit clock) and the master clock for external decoders.
When the audio block is defined as slave, the clock generator is OFF.
Figure 449 illustrates the architecture of the audio block clock generator.
| (omitted) |
Note: If NODIV is set to 1, the MCLK_x signal will be set at 0 level if this pin is configured as the
SAI pin in GPIO peripherals.
The clock source for the clock generator comes from the product clock controller. The sai_x_ker_ck clock is equivalent to the master clock which can be divided for the external decoders using bit MCKDIV[3:0]:
MCLK_x = sai_x_ker_ck / (MCKDIV[3:0] * 2), if MCKDIV[3:0] is not equal to 0000.
MCLK_x = sai_x_ker_ck, if MCKDIV[3:0] is equal to 0000.
MCLK_x signal is used only in TDM.
The division must be even in order to keep 50% on the Duty cycle on the MCLK output and on the SCK_x clock. If bit MCKDIV[3:0] = 0000, division by one is applied to obtain MCLK_x equal to sai_x_ker_ck.
In the SAI, the single ratio MCLK/FS = 256 is considered. Mostly, three frequency ranges will be encountered as illustrated in Table 235.
| Input sai_x_ker_ck clock frequency |
Most usual audio frequency sampling achievable | MCKDIV[3:0] |
|---|---|---|
| 192 kHz x 256 |
192 kHz | MCKDIV[3:0] = 0000 |
| 96 kHz | MCKDIV[3:0] = 0001 |
|
| 48 kHz | MCKDIV[3:0] = 0010 |
|
| 16 kHz | MCKDIV[3:0] = 0110 |
|
| 8 kHz | MCKDIV[3:0] = 1100 |
|
| 44.1 kHz x 256 |
44.1 kHz | MCKDIV[3:0] = 0000 |
| 22.05 kHz | MCKDIV[3:0] = 0001 |
|
| 11.025 kHz | MCKDIV[3:0] = 0010 |
|
| sai_x_ker_ck = MCLK(1) |
MCLK | MCKDIV[3:0] = 0000 |
The master clock can be generated externally on an I/O pad for external decoders if the corresponding audio block is declared as master with bit NODIV = 0 in the SAI_xCR1 register. In slave, the value set in this last bit is ignored since the clock generator is OFF, and the MCLK_x I/O pin is released for use as a general purpose I/O.
The bit clock is derived from the master clock. The bit clock divider sets the divider factor between the bit clock (SCK_x) and the master clock (MCLK_x) following the formula:
SCK_x = MCLK x (FRL[7:0] +1) / 256
where:
256 is the fixed ratio between MCLK and the audio frequency sampling.
FRL[7:0] is the number of bit clock cycles- 1 in the audio frame, configured in the SAI_xFRCR register.
In master mode it is mandatory that (FRL[7:0] +1) is equal to a number with a power of 2 (refer to Section 36.3.6: Frame synchronization) to obtain an even integer number of MCLK_x pulses by bit clock cycle. The 50% duty cycle is guaranteed on the bit clock (SCK_x).
The sai_x_ker_ck clock can also be equal to the bit clock frequency. In this case, NODIV bit in the SAI_xCR1 register should be set and the value inside the MCKDIV divider and the bit clock divider will be ignored. In this case, the number of bits per frame is fully configurable without the need to be equal to a power of two.
The bit clock strobing edge on SCK can be configured by bit CKSTR in the SAI_xCR1 register.
Refer to Section 36.3.11: SPDIF output for details on clock generator programming in SPDIF mode.
Each audio block in the SAI has its own FIFO. Depending if the block is defined to be a transmitter or a receiver, the FIFO can be written or read, respectively. There is therefore only one FIFO request linked to FREQ bit in the SAI_xSR register.
An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on:
Interrupt generation in transmitter mode
The interrupt generation depends on the FIFO configuration in transmitter mode:
Interrupt generation in reception mode
The interrupt generation depends on the FIFO configuration in reception mode:
cleared by hardware when the FIFO becomes empty (FLVL[2:0] bits in SAI_xSR is equal to 000b) i.e no data are stored in FIFO.
Like interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is set. The FREQ bit assertion mechanism is the same as the interruption generation mechanism described above for FREQIE.
Each FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one word FIFO location whatever the access size. Each FIFO word contains one audio slot. FIFO pointers are incremented by one word after each access to the SAI_xDR register.
Data should be right aligned when it is written in the SAI_xDR.
Data received will be right aligned in the SAI_xDR.
The FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the SAI_xCR2 register. If FFLUSH is set when the SAI is enabled the data present in the FIFO will be lost automatically.
The SAI is able to work as an AC’97 link controller. In this protocol:
To select this protocol, set PRTCFG[1:0] bits in the SAI_xCR1 register to 10. When AC’97 mode is selected, only data sizes of 16 or 20 bits can be used, otherwise the SAI behavior is not guaranteed.
The FS signal from the block defined as asynchronous is configured automatically as an output, since the AC’97 controller link drives the FS signal whatever the master or slave configuration.
Figure 450 shows an AC’97 audio frame structure.
| (omitted) |
Note: In AC’97 protocol, bit 2 of the tag is reserved (always 0), so bit 2 of the TAG is forced to 0
level whatever the value written in the SAI FIFO.
For more details about tag representation, refer to the AC’97 protocol standard.
One SAI can be used to target an AC’97 point-to-point communication.
Using two SAIs (for devices featuring two embedded SAIs) allows controlling three external AC’97 decoders as illustrated in Figure 451.
In SAI1, the audio block A must be declared as asynchronous master transmitter whereas the audio block B is defined to be slave receiver and internally synchronous to the audio block A.
The SAI2 is configured for audio block A and B both synchronous with the external SAI1 in slave receiver mode.
| (omitted) |
In receiver mode, the SAI acting as an AC’97 link controller requires no FIFO request and so no data storage in the FIFO when the Codec ready bit in the slot 0 is decoded low. If bit CNRDYIE is enabled in the SAI_xIM register, flag CNRDY will be set in the SAI_xSR register and an interrupt is generated. This flag is dedicated to the AC’97 protocol.
Clock generator programming in AC’97 mode
In AC’97 mode, the frame length is fixed at 256 bits, and its frequency shall be set to 48 kHz. The formulas given in Section 36.3.8: SAI clock generator shall be used with FRL = 255, in order to generate the proper frame rate (FFS_x).
The SPDIF interface is available in transmitter mode only. It supports the audio IEC60958.
To select SPDIF mode, set PRTCFG[1:0] bit to 01 in the SAI_xCR1 register.
For SPDIF protocol:
| (omitted) |
A SPDIF block contains 192 frames. Each frame is composed of two 32-bit sub-frames, generally one for the left channel and one for the right channel. Each sub-frame is composed of a SOPD pattern (4-bit) to specify if the sub-frame is the start of a block (and so is identifying a channel A) or if it is identifying a channel A somewhere in the block, or if it is referring to channel B (see Table 236). The next 28 bits of channel information are composed of 24 bits data + 4 status bits.
| SOPD |
Preamble coding |
Description |
|
|---|---|---|---|
| last bit is 0 | last bit is 1 |
||
| B | 11101000 | 00010111 | Channel A data at the start of block |
| W | 11100100 | 00011011 | Channel B data somewhere in the block |
| M | 11100010 | 00011101 | Channel A data |
The data stored in SAI_xDR has to be filled as follows:
If the data size is 20 bits, then data shall be mapped on SAI_xDR[23:4].
If the data size is 16 bits, then data shall be mapped on SAI_xDR[23:8].
SAI_xDR[23] always represents the MSB.
| (omitted) |
Note: The transfer is performed always with LSB first.
The SAI first sends the adequate preamble for each sub-frame in a block. The SAI_xDR is then sent on the SD line (manchester coded). The SAI ends the sub-frame by transferring the Parity bit calculated as described in Table 237.
| SAI_xDR[26:0] | Parity bit P value transferred |
|---|---|
| odd number of 0 | 0 |
| odd number of 1 | 1 |
The underrun is the only error flag available in the SAI_xSR register for SPDIF mode since the SAI can only operate in transmitter mode. As a result, the following sequence should be
executed to recover from an underrun error detected via the underrun interrupt or the underrun status bit:
Flush the FIFO by setting the FFLUSH bit in SAI_xCR2.
The software needs to point to the address of the future data corresponding to a start of new block (data for preamble B). If the DMA is used, the DMA source base address pointer should be updated accordingly.
Clock generator programming in SPDIF generator mode
For the SPDIF generator, the SAI shall provide a bit clock twice faster as the symbol-rate. The table hereafter shows usual examples of symbol rates with respect to the audio sampling rate.
| Audio Sampling Frequencies (FS) | Symbol-rate |
|---|---|
| 44.1 kHz | 2.8224 MHz |
| 48 kHz | 3.072 MHz |
| 96 kHz | 6.144 MHz |
| 192 kHz | 12.288 MHz |
More generally, the relationship between the audio sampling frequency (FS) and the bit clock rate (FSCK_X) is given by the formula:
FSCK_x
And the bit clock rate is obtained as follow:
FSCK_x =FSAI_CK_x
The SAI interface embeds specific features which can be useful depending on the audio protocol selected. These functions are accessible through specific bits of the SAI_xCR2 register.
Mute mode
The mute mode can be used when the audio sub-block is a transmitter or a receiver.
Audio sub-block in transmission mode
In transmitter mode, the mute mode can be selected at anytime. The mute mode is active for entire audio frames. The MUTE bit in the SAI_xCR2 register enables the mute mode when it is set during an ongoing frame.
The mute mode bit is strobed only at the end of the frame. If it is set at this time, the mute mode is active at the beginning of the new audio frame and for a complete frame, until the next end of frame. The bit is then strobed to determine if the next frame will still be a mute frame.
If the number of slots set through NBSLOT[3:0] bits in the SAI_xSLOTR register is lower than or equal to 2, it is possible to specify if the value sent in mute mode is 0 or if it is the last value of each slot. The selection is done via MUTEVAL bit in the SAI_xCR2 register.
If the number of slots set in NBSLOT[3:0] bits in the SAI_xSLOTR register is greater than 2, MUTEVAL bit in the SAI_xCR2 is meaningless as 0 values are sent on each bit on each slot.
The FIFO pointers are still incremented in mute mode. This means that data present in the FIFO and for which the mute mode is requested are discarded.
Audio sub-block in reception mode
In reception mode, it is possible to detect a mute mode sent from the external transmitter when all the declared and valid slots of the audio frame receive 0 for a given consecutive number of audio frames (MUTECNT[5:0] bits in the SAI_xCR2 register).
When the number of MUTE frames is detected, the MUTEDET flag in the SAI_xSR register is set and an interrupt can be generated if MUTEDETIE bit is set in SAI_xCR2.
The mute frame counter is cleared when the audio sub-block is disabled or when a valid slot receives at least one data in an audio frame. The interrupt is generated just once, when the counter reaches the value specified in MUTECNT[5:0] bits. The interrupt event is then reinitialized when the counter is cleared.
Note: The mute mode is not available for SPDIF audio blocks.
Mono/stereo mode
In transmitter mode, the mono mode can be addressed, without any data preprocessing in memory, assuming the number of slots is equal to 2 (NBSLOT[3:0] = 0001 in SAI_xSLOTR). In this case, the access time to and from the FIFO will be reduced by 2 since the data for slot 0 is duplicated into data slot 1.
To enable the mono mode,
In reception mode, the MONO bit can be set and is meaningful only if the number of slots is equal to 2 as in transmitter mode. When it is set, only slot 0 data will be stored in the FIFO. The data belonging to slot 1 will be discarded since, in this case, it is supposed to be the same as the previous slot. If the data flow in reception mode is a real stereo audio flow with a distinct and different left and right data, the MONO bit is meaningless. The conversion from the output stereo file to the equivalent mono file is done by software.
Companding mode
Telecommunication applications can require to process the data to be transmitted or received using a data companding algorithm.
Depending on the COMP[1:0] bits in the SAI_xCR2 register (used only when TDM mode is selected), the application software can choose to process or not the data before sending it on SD serial output line (compression) or to expand the data after the reception on SD serial input line (expansion) as illustrated in Figure 454. The two companding modes supported are the µ-Law and the A-Law log which are a part of the CCITT G.711 recommendation.
The companding standard used in the United States and Japan is the µ-Law. It supports 14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register).
The European companding standard is A-Law and supports 13 bits of dynamic range (COMP[1:0] = 11 in the SAI_xCR2 register).
Both µ-Law or A-Law companding standard can be computed based on 1’s complement or 2’s complement representation depending on the CPL bit setting in the SAI_xCR2 register.
In µ-Law and A-Law standards, data are coded as 8 bits with MSB alignment. Companded data are always 8-bit wide. For this reason, DS[2:0] bits in the SAI_xCR1 register will be forced to 010 when the SAI audio block is enabled (SAIEN bit = 1 in the SAI_xCR1 register) and when one of these two companding modes selected through the COMP[1:0] bits.
If no companding processing is required, COMP[1:0] bits should be kept clear.
| (omitted) |
Expansion and compression mode are automatically selected through the SAI_xCR2:
Output data line management on an inactive slot
In transmitter mode, it is possible to choose the behavior of the SD line output when an inactive slot is sent on the data line (via TRIS bit).
It is important to note that the two transmitters cannot attempt to drive the same SD output pin simultaneously, which could result in a short circuit. To ensure a gap between transmissions, if the data is lower than 32-bit, the data can be extended to 32-bit by setting bit SLOTSZ[1:0] = 10 in the SAI_xSLOTR register. The SD output pin will then be tri-stated at the end of the LSB of the active slot (during the padding to 0 phase to extend the data to 32-bit) if the following slot is declared inactive.
In addition, if the number of slots multiplied by the slot size is lower than the frame length, the SD output line will be tri-stated when the padding to 0 is done to complete the audio frame.
Figure 455 illustrates these behaviors.
| (omitted) |
When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed according to Figure 456 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and half frame length is higher than number of slots/2, and NBSLOT=6).
| (omitted) |
If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 455 and Figure 456 are replaced by a drive with a value of 0.
The SAI implements the following error flags:
FIFO overrun/underrun (OVRUDR)
The FIFO overrun/underrun bit is called OVRUDR in the SAI_xSR register.
The overrun or underrun errors share the same bit since an audio block can be either receiver or transmitter and each audio block in a given SAI has its own SAI_xSR register.
Overrun
When the audio block is configured as receiver, an overrun condition may appear if data are received in an audio frame when the FIFO is full and not able to store the received data. In this case, the received data are lost, the flag OVRUDR in the SAI_xSR register is set and an interrupt is generated if OVRUDRIE bit is set in the SAI_xIM register. The slot number, from which the overrun occurs, is stored internally. No more data will be stored into the FIFO until it becomes free to store new data. When the FIFO has at least one data free, the SAI audio block receiver will store new data (from new audio frame) from the slot number which was stored internally when the overrun condition was detected. This avoids data slot de-alignment in the destination memory (refer to Figure 457).
The OVRUDR flag is cleared when COVRUDR bit is set in the SAI_xCLRFR register.
| (omitted) |
Underrun
An underrun may occur when the audio block in the SAI is a transmitter and the FIFO is empty when data need to be transmitted. If an underrun is detected, the slot number for which the event occurs is stored and MUTE value (00) is sent until the FIFO is ready to transmit the data corresponding to the slot for which the underrun was detected (refer to Figure 458). This avoids desynchronization between the memory pointer and the slot in the audio frame.
The underrun event sets the OVRUDR flag in the SAI_xSR register and an interrupt is generated if the OVRUDRIE bit is set in the SAI_xIM register. To clear this flag, set COVRUDR bit in the SAI_xCLRFR register.
The underrun event can occur when the audio sub-block is configured as master or slave.
| (omitted) |
Anticipated frame synchronization detection (AFSDET)
The AFSDET flag is used only in slave mode. It is never asserted in master mode. It indicates that a frame synchronization (FS) has been detected earlier than expected since the frame length, the frame polarity, the frame offset are defined and known.
Anticipated frame detection sets the AFSDET flag in the SAI_xSR register.
This detection has no effect on the current audio frame which is not sensitive to the anticipated FS. This means that “parasitic” events on signal FS are flagged without any perturbation of the current audio frame.
An interrupt is generated if the AFSDETIE bit is set in the SAI_xIM register. To clear the AFSDET flag, CAFSDET bit must be set in the SAI_xCLRFR register.
To resynchronize with the master after an anticipated frame detection error, four steps are required:
Note: The SAIEN flag is not asserted in AC’97 mode since the SAI audio block acts as a link
controller and generates the FS signal even when declared as slave.It has no meaning in
SPDIF mode since the FS signal is not used.
Late frame synchronization detection
The LFSDET flag in the SAI_xSR register can be set only when the SAI audio block operates as a slave. The frame length, the frame polarity and the frame offset configuration are known in register SAI_xFRCR.
If the external master does not send the FS signal at the expecting time thus generating the signal too late, the LFSDET flag is set and an interrupt is generated if LFSDETIE bit is set in the SAI_xIM register.
The LFSDET flag is cleared when CLFSDET bit is set in the SAI_xCLRFR register.
The late frame synchronization detection flag is set when the corresponding error is detected. The SAI needs to be resynchronized with the master (see sequence described in Anticipated frame synchronization detection (AFSDET)).
In a noisy environment, glitches on the SCK clock may be wrongly detected by the audio block state machine and shift the SAI data at a wrong frame position. This event can be detected by the SAI and reported as a late frame synchronization detection error.
There is no corruption if the external master is not managing the audio data frame transfer in continuous mode, which should not be the case in most applications. In this case, the LFSDET flag will be set.
Note: The LFSDET flag is not asserted in AC’97 mode since the SAI audio block acts as a link
controller and generates the FS signal even when declared as slave.It has no meaning in
SPDIF mode since the signal FS is not used by the protocol.
Codec not ready (CNRDY AC’97)
The CNRDY flag in the SAI_xSR register is relevant only if the SAI audio block is configured to operate in AC’97 mode (PRTCFG[1:0] = 10 in the SAI_xCR1 register). If CNRDYIE bit is set in the SAI_xIM register, an interrupt is generated when the CNRDY flag is set.
CNRDY is asserted when the Codec is not ready to communicate during the reception of the TAG 0 (slot0) of the AC’97 audio frame. In this case, no data will be automatically stored into the FIFO since the Codec is not ready, until the TAG 0 indicates that the Codec is ready. All the active slots defined in the SAI_xSLOTR register will be captured when the Codec is ready.
To clear CNRDY flag, CCNRDY bit must be set in the SAI_xCLRFR register.
Wrong clock configuration in master mode (with NODIV = 0)
When the audio block operates as a master (MODE[1] = 0) and NODIV bit is equal to 0, the WCKCFG flag is set as soon as the SAI is enabled if the following conditions are met:
MODE, NODIV, and SAIEN bits belong to SAI_xCR1 register and FRL to SAI_xFRCR register.
If WCKCFGIE bit is set, an interrupt is generated when WCKCFG flag is set in the SAI_xSR register. To clear this flag, set CWCKCFG bit in the SAI_xCLRFR register.
When WCKCFG bit is set, the audio block is automatically disabled, thus performing a hardware clear of SAIEN bit.
The SAI audio block can be disabled at any moment by clearing SAIEN bit in the SAI_xCR1 register. All the already started frames are automatically completed before the SAI is stops working. SAIEN bit remains High until the SAI is completely switched-off at the end of the current audio frame transfer.
If an audio block in the SAI operates synchronously with the other one, the one which is the master must be disabled first.
To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO). There is one DMA channel per audio sub-block supporting basic DMA request/acknowledge protocol.
To configure the audio sub-block for DMA transfer, set DMAEN bit in the SAI_xCR1 register. The DMA request is managed directly by the FIFO controller depending on the FIFO threshold level (for more details refer to Section 36.3.9: Internal FIFOs). DMA transfer direction is linked to the SAI audio sub-block configuration:
Follow the sequence below to configure the SAI interface in DMA mode:
Note: Before configuring the SAI block, the SAI DMA channel must be disabled.
The SAI supports 7 interrupt sources as shown in Table 239.
| Interrupt source |
Interrupt group | Audio block mode | Interrupt enable | Interrupt clear |
|---|---|---|---|---|
| FREQ | FREQ |
Master or slave Receiver or transmitter |
FREQIE in SAI_xIM register |
Depends on:
For more details refer to Section 36.3.9: Internal FIFOs |
| OVRUDR | ERROR |
Master or slave Receiver or transmitter |
OVRUDRIE in SAI_xIM register | COVRUDR = 1 in SAI_xCLRFR register |
| AFSDET | ERROR |
Slave (not used in AC’97 mode and SPDIF mode) |
AFSDETIE in SAI_xIM register | CAFSDET = 1 in SAI_xCLRFR register |
| LFSDET | ERROR |
Slave (not used in AC’97 mode and SPDIF mode) |
LFSDETIE in SAI_xIM register | CLFSDET = 1 in SAI_xCLRFR register |
| CNRDY | ERROR | Slave (only in AC’97 mode) |
CNRDYIE in SAI_xIM register | CCNRDY = 1 in SAI_xCLRFR register |
| MUTEDET | MUTE |
Master or slave Receiver mode only |
MUTEDETIE in SAI_xIM register |
CMUTEDET = 1 in SAI_xCLRFR register |
| WCKCFG | ERROR | Master with NODIV = 0 in SAI_xCR1 register |
WCKCFGIE in SAI_xIM register | CWCKCFG = 1 in SAI_xCLRFR register |
Follow the sequence below to enable an interrupt:
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYNCOUT[1:0] | Res. | Res. | SYNCIN[1:0] |
||
| rw | rw | rw | rw |
||||||||||||||||||||||||||||
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bits 5:4 | SYNCOUT[1:0]: Synchronization outputs |
|
These bits are set and cleared by software. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | SYNCIN[1:0]: Synchronization inputs |
|
These bits are set and cleared by software. |
Address offset: 0x004
Reset value: 0x0000 0040
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCKDIV[3:0] | NODIV | Res. | DMAEN | SAIEN |
Res. | Res. | OUTD RIV |
MONO | SYNCEN[1:0] | CKSTR | LSBFIRST | DS[2:0] | Res. | PRTCFG[1:0] | MODE[1:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:20 | MCKDIV[3:0]: Master clock divider |
|
These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Fsai_x_ker_ck |
|
| Bit 19 | NODIV: No divider |
|
This bit is set and cleared by software. |
|
| Bit 18 | Reserved, must be kept at reset value. |
| Bit 17 | DMAEN: DMA enable |
|
This bit is set and cleared by software. Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must |
|
| Bit 16 | SAIEN: Audio block enable |
|
This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows controlling the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. When the SAI block (A or B) is configured in master mode, the clock must be present on the |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bit 13 | OUTDRIV: Output drive |
|
This bit is set and cleared by software. 0: Audio block output driven when SAIEN is set
This bit has to be set before enabling the audio block and after the audio block configuration.
|
|
| Bit 12 | MONO: Mono mode |
|
This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. |
|
| Bits 11:10 | SYNCEN[1:0]: Synchronization enable |
|
These bits are set and cleared by software. They must be configured when the audio sub-block is disabled.
The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.
|
|
| Bit 9 | CKSTR: Clock strobing edge |
|
This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. |
|
| Bit 8 | LSBFIRST: Least significant bit first |
|
This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC’97 audio protocol since AC’97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. |
|
| Bits 7:5 | DS[2:0]: Data size |
|
These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. |
|
| Bit 4 | Reserved, must be kept at reset value. |
| Bits 3:2 | PRTCFG[1:0]: Protocol configuration |
|
These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. |
|
| Bits 1:0 | MODE[1:0]: SAIx audio block mode |
|
These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. When the audio block is configured in SPDIF mode, the master transmitter mode is forced |
Address offset: 0x024
Reset value: 0x0000 0040
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCKDIV[3:0] | NODIV | Res. | DMAEN | SAIEN |
Res. | Res. | OUTD RIV |
MONO | SYNCEN[1:0] | CKSTR | LSBFIRST | DS[2:0] | Res. | PRTCFG[1:0] | MODE[1:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:20 | MCKDIV[3:0]: Master clock divider |
|
These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Fsai_x_ker_ck |
|
| Bit 19 | NODIV: No divider |
|
This bit is set and cleared by software. |
|
| Bit 18 | Reserved, must be kept at reset value. |
| Bit 17 | DMAEN: DMA enable |
|
This bit is set and cleared by software. Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must |
|
| Bit 16 | SAIEN: Audio block enable |
|
This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows controlling the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. When the SAI block (A or B) is configured in master mode, the clock must be present on the |
|
| Bits 15:14 | Reserved, must be kept at reset value. |
| Bit 13 | OUTDRIV: Output drive |
|
This bit is set and cleared by software. 0: Audio block output driven when SAIEN is set
This bit has to be set before enabling the audio block and after the audio block configuration.
|
|
| Bit 12 | MONO: Mono mode |
|
This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. |
|
| Bits 11:10 | SYNCEN[1:0]: Synchronization enable |
|
These bits are set and cleared by software. They must be configured when the audio sub-block is disabled.
The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.
|
|
| Bit 9 | CKSTR: Clock strobing edge |
|
This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. |
|
| Bit 8 | LSBFIRST: Least significant bit first |
|
This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC’97 audio protocol since AC’97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. |
|
| Bits 7:5 | DS[2:0]: Data size |
|
These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. |
|
| Bit 4 | Reserved, must be kept at reset value. |
| Bits 3:2 | PRTCFG[1:0]: Protocol configuration |
|
These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. |
|
| Bits 1:0 | MODE[1:0]: SAIx audio block mode |
|
These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. When the audio block is configured in SPDIF mode, the master transmitter mode is forced |
Address offset: 0x008
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
COMP[1:0] | CPL | MUTECNT[5:0] | MUTE VAL |
MUTE | TRIS | F FLUSH |
FTH[2:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:14 | COMP[1:0]: Companding mode. |
|
These bits are set and cleared by software. The µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit.
Companding mode is applicable only when TDM is selected.
|
|
| Bit 13 | CPL: Complement bit. |
|
This bit is set and cleared by software. It defines the type of complement to be used for companding mode 0: 1’s complement representation.
This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm.
|
|
| Bits 12:7 | MUTECNT[5:0]: Mute counter. |
|
These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. |
|
| Bit 6 | MUTEVAL: Mute value. |
|
This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. This bit is meaningless and should not be used for SPDIF audio blocks. |
|
| Bit 5 | MUTE: Mute. |
|
This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2.
This bit is meaningless and should not be used for SPDIF audio blocks.
|
|
| Bit 4 | TRIS: Tristate management on data line. |
|
This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. |
|
| Bit 3 | FFLUSH: FIFO flush. |
|
This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 0: No FIFO flush. 1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interruption must be disabled |
|
| Bits 2:0 | FTH[2:0]: FIFO threshold. |
|
This bit is set and cleared by software. 000: FIFO empty 001: ¼ FIFO |
Address offset: 0x028
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
COMP[1:0] | CPL | MUTECNT[5:0] | MUTE VAL |
MUTE | TRIS | F FLUSH |
FTH[2:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | w | rw | rw | rw | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:14 | COMP[1:0]: Companding mode. |
|
These bits are set and cleared by software. The µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit.
Companding mode is applicable only when TDM is selected.
|
|
| Bit 13 | CPL: Complement bit. |
|
This bit is set and cleared by software. It defines the type of complement to be used for companding mode 0: 1’s complement representation.
This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm.
|
|
| Bits 12:7 | MUTECNT[5:0]: Mute counter. |
|
These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. |
|
| Bit 6 | MUTEVAL: Mute value. |
|
This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set.
This bit is meaningless and should not be used for SPDIF audio blocks.
|
|
| Bit 5 | MUTE: Mute. |
|
This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. This bit is meaningless and should not be used for SPDIF audio blocks. |
|
| Bit 4 | TRIS: Tristate management on data line. |
|
This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. |
|
| Bit 3 | FFLUSH: FIFO flush. |
|
This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 0: No FIFO flush. 1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interruption must be disabled |
|
| Bits 2:0 | FTH[2:0]: FIFO threshold. |
|
This bit is set and cleared by software. 000: FIFO empty 001: ¼ FIFO |
Address offset: 0x00C
Reset value: 0x0000 0007
Note: This register has no meaning in AC’97 and SPDIF audio protocol
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSOFF | FSPOL | FSDEF |
Res. | FSALL[6:0] | FRL[7:0] |
|||||||||||||
| rw | rw | r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bit 18 | FSOFF: Frame synchronization offset. |
|
This bit is set and cleared by software. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. |
|
| Bit 17 | FSPOL: Frame synchronization polarity. |
|
This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. |
|
| Bit 16 | FSDEF: Frame synchronization definition. |
|
This bit is set and cleared by software. 0: FS signal is a start frame signal |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:8 | FSALL[6:0]: Frame synchronization active level length. |
|
These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. |
|
| Bits 7:0 | FRL[7:0]: Frame length. |
|
These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). |
Address offset: 0x02C
Reset value: 0x0000 0007
Note: This register has no meaning in AC’97 and SPDIF audio protocol
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSOFF | FSPOL | FSDEF |
Res. | FSALL[6:0] | FRL[7:0] |
|||||||||||||
| rw | rw | r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bit 18 | FSOFF: Frame synchronization offset. |
|
This bit is set and cleared by software. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. |
|
| Bit 17 | FSPOL: Frame synchronization polarity. |
|
This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. |
|
| Bit 16 | FSDEF: Frame synchronization definition. |
|
This bit is set and cleared by software. 0: FS signal is a start frame signal |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bits 14:8 | FSALL[6:0]: Frame synchronization active level length. |
|
These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. |
|
| Bits 7:0 | FRL[7:0]: Frame length. |
|
These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). |
Address offset: 0x010
Reset value: 0x0000 0000
Note: This register has no meaning in AC’97 and SPDIF audio protocol
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SLOTEN[15:0] |
Res. | Res. | Res. | Res. | NBSLOT[3:0] | SLOTSZ[1:0] | Res. | FBOFF[4:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 31:16 | SLOTEN[15:0]: Slot enable. |
|
These bits are set and cleared by software. |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:8 | NBSLOT[3:0]: Number of slots in an audio frame. |
|
These bits are set and cleared by software. |
|
| Bits 7:6 | SLOTSZ[1:0]: Slot size |
|
This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section : Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bits 4:0 | FBOFF[4:0]: First bit offset |
|
These bits are set and cleared by software. |
Address offset: 0x030
Reset value: 0x0000 0000
Note: This register has no meaning in AC’97 and SPDIF audio protocol
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SLOTEN[15:0] |
Res. | Res. | Res. | Res. | NBSLOT[3:0] | SLOTSZ[1:0] | Res. | FBOFF[4:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bits 31:16 | SLOTEN[15:0]: Slot enable. |
|
These bits are set and cleared by software. |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:8 | NBSLOT[3:0]: Number of slots in an audio frame. |
|
These bits are set and cleared by software. |
|
| Bits 7:6 | SLOTSZ[1:0]: Slot size |
|
This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section : Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bits 4:0 | FBOFF[4:0]: First bit offset |
|
These bits are set and cleared by software. |
Address offset: 0x014
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET IE |
AFSDET IE |
CNRDY IE |
FREQ IE |
WCKCFG IE |
MUTEDET IE |
OVRUDR IE |
| rw | rw | rw | rw | rw | rw | rw |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | LFSDETIE: Late frame synchronization detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 5 | AFSDETIE: Anticipated frame synchronization detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 4 | CNRDYIE: Codec not ready interrupt enable (AC’97). |
|
This bit is set and cleared by software. |
|
| Bit 3 | FREQIE: FIFO request interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 2 | WCKCFGIE: Wrong clock configuration interrupt enable. |
|
This bit is set and cleared by software.
This bit is used only in TDM mode and is meaningless in other modes.
|
|
| Bit 1 | MUTEDETIE: Mute detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 0 | OVRUDRIE: Overrun/underrun interrupt enable. |
|
This bit is set and cleared by software. |
Address offset: 0x034
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET IE |
AFSDET IE |
CNRDY IE |
FREQ IE |
WCKCFG IE |
MUTEDET IE |
OVRUDR IE |
| rw | rw | rw | rw | rw | rw | rw |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | LFSDETIE: Late frame synchronization detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 5 | AFSDETIE: Anticipated frame synchronization detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 4 | CNRDYIE: Codec not ready interrupt enable (AC’97). |
|
This bit is set and cleared by software. |
|
| Bit 3 | FREQIE: FIFO request interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 2 | WCKCFGIE: Wrong clock configuration interrupt enable. |
|
This bit is set and cleared by software.
This bit is used only in TDM mode and is meaningless in other modes.
|
|
| Bit 1 | MUTEDETIE: Mute detection interrupt enable. |
|
This bit is set and cleared by software. |
|
| Bit 0 | OVRUDRIE: Overrun/underrun interrupt enable. |
|
This bit is set and cleared by software. |
Address offset: 0x018
Reset value: 0x0000 0008
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLVL[2:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET | AFSDET | CNRDY | FREQ | WCKCFG | MUTEDET | OVRUDR |
||
| r | r | r |
r | r | r | r | r | r | r | ||||||||||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bits 18:16 | FLVL[2:0]: FIFO level threshold. |
|
This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: |
|
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bit 6 | LFSDET: Late frame synchronization detection. |
|
This bit is read only. |
|
| Bit 5 | AFSDET: Anticipated frame synchronization detection. |
|
This bit is read only. |
|
| Bit 4 | CNRDY: Codec not ready. |
|
This bit is read only. 0: External AC’97 Codec is ready 1: External AC’97 Codec is not ready |
|
| Bit 3 | FREQ: FIFO request. |
|
This bit is read only.
|
|
| Bit 2 | WCKCFG: Wrong clock configuration flag. |
|
This bit is read only. 0: Clock configuration is correct |
|
| Bit 1 | MUTEDET: Mute detection. |
|
This bit is read only. |
|
| Bit 0 | OVRUDR: Overrun / underrun. |
|
This bit is read only. |
Address offset: 0x038
Reset value: 0x0000 0008
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLVL[2:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET | AFSDET | CNRDY | FREQ | WCKCFG | MUTEDET | OVRUDR |
||
| r | r | r |
r | r | r | r | r | r | r | ||||||||||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bits 18:16 | FLVL[2:0]: FIFO level threshold. |
|
This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: |
|
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bit 6 | LFSDET: Late frame synchronization detection. |
|
This bit is read only. |
|
| Bit 5 | AFSDET: Anticipated frame synchronization detection. |
|
This bit is read only. |
|
| Bit 4 | CNRDY: Codec not ready. |
|
This bit is read only. 0: External AC’97 Codec is ready 1: External AC’97 Codec is not ready |
|
| Bit 3 | FREQ: FIFO request. |
|
This bit is read only.
|
|
| Bit 2 | WCKCFG: Wrong clock configuration flag. |
|
This bit is read only. 0: Clock configuration is correct |
|
| Bit 1 | MUTEDET: Mute detection. |
|
This bit is read only. |
|
| Bit 0 | OVRUDR: Overrun / underrun. |
|
This bit is read only. |
Address offset: 0x01C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLFSDET | CAFSDET | CCNRDY | Res. | CWCKCFG | CMUTE DET |
COVRUD R |
| w | w | w | w | w | w |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | CLFSDET: Clear late frame synchronization detection flag. |
|
This bit is write only. |
|
| Bit 5 | CAFSDET: Clear anticipated frame synchronization detection flag. |
|
This bit is write only. |
|
| Bit 4 | CCNRDY: Clear Codec not ready flag. |
|
This bit is write only. |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bit 2 | CWCKCFG: Clear wrong clock configuration flag. |
|
This bit is write only. |
|
| Bit 1 | CMUTEDET: Mute detection flag. |
|
This bit is write only. |
|
| Bit 0 | COVRUDR: Clear overrun / underrun. |
|
This bit is write only. |
Address offset: 0x03C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CLFSDET | CAFSDET | CCNRDY | Res. | CWCKCFG | CMUTE DET |
COVRUD R |
| w | w | w | w | w | w |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | CLFSDET: Clear late frame synchronization detection flag. |
|
This bit is write only. |
|
| Bit 5 | CAFSDET: Clear anticipated frame synchronization detection flag. |
|
This bit is write only. |
|
| Bit 4 | CCNRDY: Clear Codec not ready flag. |
|
This bit is write only. |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bit 2 | CWCKCFG: Clear wrong clock configuration flag. |
|
This bit is write only. |
|
| Bit 1 | CMUTEDET: Mute detection flag. |
|
This bit is write only. |
|
| Bit 0 | COVRUDR: Clear overrun / underrun. |
|
This bit is write only. |
Address offset: 0x020
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA[31:16] |
DATA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATA[31:0]: Data |
|
A write to this register loads the FIFO provided the FIFO is not full. |
Address offset: 0x040
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA[31:16] |
DATA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATA[31:0]: Data |
|
A write to this register loads the FIFO provided the FIFO is not full. |
The following table summarizes the SAI registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0000 |
SAI_GCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYNCOUT[1:0] | Res.. | Res. | SYNCIN[1:0] | ||
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x0004 or 0x0024 |
SAI_xCR1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCKDIV[3:0] | NODIV | Res. | DMAEN | SAIEN | Res. | Res. | OUTDRIV | MONO | SYNCEN[1:0] | CKSTR | LSBFIRST | DS[2:0] | Res. | PRTCFG[1:0] | MODE[1:0] | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x0008 or 0x0028 |
SAI_xCR2 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMP[1:0] | CPL | MUTECN[5:0] |
MUTE VAL | MUTE | TRIS | FFLUS | FTH | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x000C or 0x002C |
SAI_xFRCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSOFF | FSPOL | FSDEF | Res. | FSALL[6:0] | FRL[7:0] |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
|||||||||||||||
| 0x0010 or 0x0030 |
SAI_xSLOTR | SLOTEN[15:0] |
Res. | Res. | Res. | Res. | NBSLOT[3:0] | SLOTSZ[1:0} | Res. | FBOFF[4:0] |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x0014 or 0x0034 |
SAI_xIM |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET | AFSDETIE | CNRDYIE | FREQIE | WCKCFG | MUTEDET | OVRUDRIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x0018 or 0x0038 |
SAI_xSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FLVL[2:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET | AFSDET | CNRDY | FREQ | WCKCFG | MUTEDET | OVRUDR | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|||||||||||||||||||||||
| 0x001C or 0x003C |
SAI_xCLRFR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LFSDET | CAFSDET | CNRDY | Res. | WCKCFG | MUTEDET | OVRUDR |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x0020 or 0x0040 |
SAI_xDR | DATA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Refer to Section 2.2 on page 75 for the register boundary addresses.
The SPDIFRX interface handles S/PDIF audio protocol.
The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS.
The receiver provides all the necessary features to detect the symbol rate, and decode the incoming data. It is possible to use a dedicated path for the user and channel information in order to ease the interface handling. Figure 459 shows a simplified block diagram.
The SPDIFRX_DC block is responsible of the decoding of the S/PDIF stream received from SPDIFRX_IN[4:1] inputs. This block re-sample the incoming signal, decode the manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the REG_IF part, decoded data, and associated status flags.
This peripheral can be fully controlled via the APB1 bus, and can handle two DMA channels:
Interrupt services are also available either as an alternative function to the DMA, or for signaling error or key status of the peripheral.
The SPDIFRX also offers a signal named spdifrx_frame_sync, which toggles every time that a sub-frame’s preamble is detected. So the duty cycle will be 50%, and the frequency equal to the frame rate.
This signal can be connected to timer events, in order to compute frequency drift.
| (omitted) |
S/PDIF block
A S/PDIF frame is composed of two sub-frames (see Figure 461). Each sub-frame contains 32 bits (or time slots):
| (omitted) |
For linear coded audio applications, the first sub-frame (left or “A” channel in stereophonic operation and primary channel in monophonic operation) normally starts with preamble “M”. However, the preamble changes to preamble “B” once every 192 frames to identify the start of the block structure used to organize the channel status and user information. The second sub-frame (right or “B” channel in stereophonic operation and secondary channel in monophonic operation) always starts with preamble “W”.
A S/PDIF block contains 192 pairs of sub-frames of 32 bits.
| (omitted) |
Synchronization preambles
The preambles patterns are inverted or not according to the previous half-bit value. This previous half-bit value is the level of the line before enabling a transfer for the first “B” preamble of the first frame. For the others preambles, this previous half-bit value is the second half-bit of the parity bit of the previous sub-frame. The preambles patterns B, M and W are described in the Figure 462.
| (omitted) |
Coding of information bits
In order to minimize the DC component value on the transmission line, and to facilitate clock recovery from the data stream, bits 4 to 31 are encoded in biphase-mark.
Each bit to be transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit to be transmitted is logical 0. However, it is different if the bit is logical 1. These states are named “UI” (Unit Interval) in the IEC-60958 specification.
The 24 data bits are transferred LSB first.
| (omitted) |
Main principle
The technique used by the SPDIFRX in order to decode the S/PDIF stream is based on the measurement of the time interval between two consecutive edges. Three kinds of time intervals may be found into an S/PDIF stream:
The SPDIFRX_DC block is responsible of the decoding of the received S/PDIF stream. It takes care of the following functions:
Figure 464 gives a detailed view of the SPDIFRX decoder.
| (omitted) |
Noise filtering & rising/falling edge detection
The S/PDIF signal received on the selected SPDIFRX_IN is re-sampled using the SPDIFRX_CLK clock (acquisition clock). A simple filtering is applied in order cancel spurs. This is performed by the stage detecting the edge transitions. The edge transitions are detected as follow:
| (omitted) |
Longest and shortest transition detector
The longest and shortest transition detector block detects the maximum (MAX_CNT) and minimum (MIN_CNT) duration between two transitions. The TRCNT counter is used to measure the time interval duration. It is clocked by the SPDIFRX_CLK signal. On every transition pulse, the counter value is stored and the counter is reset to start counting again.
The maximum duration is normally found during the preamble period. This maximum duration is sent out as MAX_CNT. The minimum duration is sent out as MIN_CNT.
The search of the longest and shortest transition is stopped when the transition timer expires. The transition timer is like a watchdog timer that generates a trigger after 70 transitions of the incoming signal. Note that counting 70 transitions insures a delay a bit longer than a sub-frame.
Note that when the TRCNT overflows due to a too long time interval between two pulses,
the SPDIFRX is stopped and the flag TERR of SPDIFRX_SR register is set to 1.
Transition coder and preamble detector
The transition coder and preamble detector block receives the MAX_CNT and MIN_CNT. It also receives the current transition width from the TRCNT counter (see Figure 464). This block encodes the current transition width by comparing the current transition width with two different thresholds, names THHI and THLO.
The thresholds THHI and THLO are elaborated using two different methods.
If the peripheral is doing its initial synchronization (‘coarse synchronization’), then the thresholds are computed as follow:
Once the ‘coarse synchronization’ is completed, then the SPDIFRX uses a more accurate reference in order to elaborate the thresholds. The SPDIFRX measures the length of 24 symbols (WIDTH24) for defining THLO and the length of 40 symbols (WIDTH40) for THHI. THHI and THLO are computed as follow:
This second synchronization phase is called the ‘fine synchronization’. Refer to Figure 468
for additional information.
As shown in the figure hereafter, THLO is ideally equal to 1.5 UI, and to THHI 2.5 UI.
| (omitted) |
The preamble detector checks four consecutive transitions of a specific sequence to determine if they form the part of preamble. Let us say TRANS0, TRANS1, TRANS2 and TRANS3 represent four consecutive transitions encoded as mentioned above. Table 241
shows the values of these four transitions to form a preamble. Absence of this pattern indicates that these transitions form part of the data in the sub frame and bi-phase decoder will decode them.
| Preamble type | Biphase data pattern | TRANS3 | TRANS2 | TRANS1 | TRANS0 |
|---|---|---|---|---|---|
| Preamble B | 11101000 | TL | TS | TS | TL |
| Preamble M | 11100010 | TL | TL | TS | TS |
| Preamble W | 11100100 | TL | TM | TS | TM |
Bi-phase decoder
The Bi-phase decoder decodes the input bi-phase marked data stream using the transition information provided by the transition coder and preamble detector block. It first waits for the preamble detection information. After the preamble detection, it decodes the following transition information:
After decoding 28 data bits this way, this module looks for the following preamble data. If the new preamble is not what is expected, then this block generates an error signal (FERR set to 1). Refer to Section 37.3.8: Reception errors, for additional information on error flags.
Data packing
This block is responsible of the decoding of the IEC-60958 frames and blocks. It also handles the writing into the RX_BUF or into SPDIFRX_CSR register.
The SPDIFRX tolerance to clock deviation depends on the number of sample clock cycles in one bit slot. The fastest SPDIFRX_CLK is, the more robust the reception will be. The ratio between SPDIFRX_CLK frequency and the symbol rate must be at least 11.
Two kinds of phenomenon (at least!) can degrade the reception quality:
The synchronization phase starts when setting SPDIFRXEN to 0b01 or 0b11. Figure 467
shows the synchronization process.
If the bit WFA of SPDIFRX_CR register is set to 1, then the peripheral must first detect activity on the selected SPDIFRX_IN line before starting the synchronization process. The activity detection is performed by detecting four transitions on the selected SPDIFRX_IN. The peripheral remains in this state until transitions are not detected. This function can be particularly helpful because the IP switches in COARSE SYNC mode only if activity is present on the selected SPDIFRX_IN input, avoiding synchronization errors. See Section 37.4: Programming procedures for additional information. The user can still set the SPDIFRX into STATE_IDLE by setting SPDIFRXEN to 0. If the WFA is set to 0, the peripheral starts the coarse synchronization without checking activity.
The next step consists on doing a first estimate of the thresholds (COARSE SYNC), in order to perform the fine synchronization (FINE SYNC). Due to disturbances of the SPDIFRX line, it could happen that the process is not executed first time right. For this purpose, the user can program the number of allowed re-tries (NBTR) before setting SERR error flag. When the SPDIFRX has been able to measure properly the duration of 24 and 40 consecutive symbols then the FINE SYNC is completed, the threshold values are updated, and the flag SYNCD is set to 1. Refer to Section : Transition coder and preamble detector
for additional information.
Two kinds of errors are detected:
When the first FINE SYNC is completed, the reception of channel status (C) and user data (U) will start when the next “B” preamble is detected (see Figure 471).Then the user can read IEC-60958 C and U bits through SPDIFRX_CSR register. According to this information the user can then select the proper settings for DRFMT and RXSTEO. For example if the user detects that the current audio stream transports encoded data, then he can put RXSTEO to 0, and DRFMT to 0b10 prior to start data reception. Note that DRFMT and RXSTEO cannot be modified when SPDIFRXEN = 0b11. Writes to these fields are ignored if SPDIFRXEN is already 0b11, though these field can be changed with the same write instruction that causes SPDIFRXEN to become 0b11.
Then the SPDIFRX waits for SPDIFRXEN = 0b11 and the “B” preamble before starting saving audio samples.
| (omitted) |
Refer to Frame structure and synchronization error for additional information concerning TRCNT overflow.
The FINE SYNC process is re-triggered every frame in order to update thresholds as shown in Figure 468 in order to continuously track S/PDIF synchronization.
| (omitted) |
The software can control the state of the SPDIFRX through SPDIFRXEN field. The SPDIFRX can be into one of the following states:
The Figure 469 shows the possible states of the SPDIFRX, and how to transition from one state to the other. The bits under software control are followed by the mention “(SW)”, the bits under IP control are followed by the mention “(HW)”.
| (omitted) |
When SPDIFRX is in STATE_IDLE:
When SPDIFRX is in STATE_SYNC:
When SPDIFRX is in STATE_RCV:
When SPDIFRX is in STATE_STOP:
When SPDIFRXEN is set to 0, the IP is disabled, meaning that all the state machines are reset, and RX_BUF is flushed. Note as well that flags FERR, SERR and TERR are reset.
The SPDIFRX offers a double buffer for the audio sample reception. A 32-bit buffer located into the SPDIFRX_CLK clock domain (RX_BUF), and the SPDIFRX_FMTx_DR register. The valid data contained into the RX_BUF will be immediately transferred into SPDIFRX_FMTx_DR if SPDIFRX_FMTx_DR is empty.
The valid data contained into the RX_BUF will be transferred into SPDIFRX_FMTx_DR when the two following conditions are reached:
Having a 2-word buffer gives more flexibility for the latency constraint.
The maximum latency allowed is TSAMPLE - 2TPCLK - 2TSPDIFRX_CLK
Where TSAMPLE is the audio sampling rate of the received stereo audio samples, TPCLK is the period of PCLK1 clock, and TSPDIFRX_CLK is the period of SPDIFRX_CLK clock.
The SPDIFRX offers the possibility to use either DMA (spdifrx_dma_req/clr_d) or interrupts for transferring the audio samples into the memory. The recommended option is DMA, refer to Section 37.3.10: DMA Interface for additional information.
The SPDIFRX offers several way on handling the received data. The user can either have a separate flow for control information and audio samples, or get them all together.
For each sub-frame, the data reception register SPDIFRX_FMTx_DR contains the 24 data bits, and optionally the V, U, C, PE status bits, and the PT (see Mixing data and control
flow).
Note that PE bit stands for Parity Error bit, and will be set to 1 when a parity error is detected
in the decoded sub-frame. The PT field carries the preamble type (B, M or W).
V, U and C are a direct copy of the value received from the S/PDIF interface.
The bit DRFMT allows the selection between 3 audio formats as shown in Figure 470.
| (omitted) |
Setting DRFMT to 0b00 or 0b01, offers the possibility to have the data either right or left aligned into the SPDIFRX_FMTx_DR register. The status information can be enabled or forced to zero according to the way the software wants to handle them.
The format given by DRFMT= 0b10 is interesting in non-linear mode, as only 16 bits per sub-frame are used. By using this format, the data of two consecutive sub-frames are stored into SPDIFRX_FMTx_DR, dividing by two the amount of memory footprint. Note that when RXSTEO = 1, there is no misalignment risks (i.e. data from ChA will be always stored into SPDIFRX_FMTx_DR[31:16]). If RXSTEO = 0, then there is a misalignment risk is case of overrun situation. In that case SPDIFRX_FMTx_DR[31:16] will always contain the oldest value and SPDIFRX_FMTx_DR[15:0] the more recent value (see Figure 472).
In this format the status information cannot be mixed with data, but the user can still get them through SPDIFRX_CSR register, and use a dedicated DMA channel or interrupt to transfer them to memory (see Section 37.3.7: Dedicated control flow)
Mixing data and control flow
The user can choose to use this mode in order to get the full flexibility of the handling of the control flow. The user can select which field shall be kept into the data register (SPDIFRX_FMTx_DR).
The SPDIFRX offers the possibility to catch both user data and channel status information via a dedicated DMA channel. This feature allows the SPDIFRX to acquire continuously the channel status and user information. The acquisition will start at the beginning of a IEC 60958 block. Two fields are available to control this path: CBDMAEN and SPDIFRXEN. When SPDIFRXEN is set to 0b01 or 0x11, the acquisition is started, after completion of the synchronization phase. When 8 channel status and 16 user data bits have been received, they are packed and stored into SPDIFRX_CSR register. A DMA request is triggered if the bit CBDMAEN is set to 1 (see Figure 471).
If CS[0] corresponds to the first bit of a new block, the bit SOB will be set to 1. Refer to Section 37.5.8: Channel status register (SPDIFRX_CSR). A bit is available (CHSEL) in order to select if the user wants to select channel status information (C) from the channel A or B.
| (omitted) |
Note: Once the first start of block is detected (B preamble), the SPDIFRX is checking the
preamble type every 8 frames.
Note: Overrun error on SPDIFRX_FMTx_DR register does not affect this path.
Frame structure and synchronization error
The SPDIFRX, detects errors, when one of the following condition occurs:
When one of those flags goes to 1, the traffic on selected SPDIFRX_IN is then ignored, an interrupt is generated if the IFEIE bit of the SPDIFRX_CR register is set.
The normal procedure when one of those errors occur is:
Refer to Figure 469 for additional information.
Parity error
For each sub-frame, an even number of zeros and ones is expected inside the 28 information bits. If not, the parity error bit PERR is set in the SPDIFRX_SR register and an interrupt is generated if the parity interrupt enable PERRIE bit is set in the SPDIFRX_CR register. The reception of the incoming data is not paused, and the SPDIFRX continue to deliver data to SPDIFRX_FMTx_DR even if the interrupt is still pending.
The interrupt is acknowledged by clearing the PERR flag through PERRCF bit.
If the software wants to guarantee the coherency between the data read in the SPDIFRX_FMTx_DR register and the value of the bit PERR, the bit PMSK must be set to 0.
Overrun error
If both SPDIFRX_FMTx_DR and RX_BUF are full, while the SPDIFRX_DC needs to write a new sample in RX_BUF, this new sample is dropped, and an overrun condition is triggered. The overrun error flag OVR is set in the SPDIFRX_SR register and an interrupt is generated if the OVRIE bit of the SPDIFRX_CR register is set.
If the RXSTEO bit is set to 0, then as soon as the RX_BUF is empty, the IP will store the next incoming data, even if the OVR flag is still pending. The main purpose is to reduce as much as possible the amount of lost samples. Note that the behavior is similar independently of DRFMT value. See Figure 472.
| (omitted) |
If the RXSTEO bit is set to 1, it means that stereo data are transported, then the SPDIFRX has to avoid misalignment between left and right channels. So the peripheral has to drop a second sample even if there is room inside the RX_BUF in order to avoid misalignment. Then the incoming samples can be written normally into the RX_BUF even if the OVR flag is still pending. Refer to Figure 473.
The OVR flag is cleared by software, by setting the OVRCF bit to 1.
| (omitted) |
The SPDIFRX block needs two different clocks:
In order to decode properly the incoming S/PDIF stream the SPDIFRX_DC shall re-sample the received data with a clock at least 11 times higher than the maximum symbol rate, or 704 times higher than the audio sample rate. For example if the user expects to receive a symbol rate to up to 12.288 MHz, the sample rate shall be at least 135.2 MHz. The clock used by the SPDIFRX_DC is the SPDIFRX_CLK.
The frequency of the PCLK1 must be at least equal to the symbol rate.
| Symbol Rate | Minimum SPDIFRX_CLK frequency | Comments |
|---|---|---|
| 3.072 MHz | 33.8 MHz | For 48 kHz stream |
| 6.144 MHz | 67.6 MHz | For 96 kHz stream |
| 12.288 MHz | 135.2 MHz | For 192 kHz stream |
The SPDIFRX interface is able to perform communication using the DMA.
Note: The user should refer to product specifications for availability of the DMA controller.
The SPDIFRX offers two independent DMA channels:
The DMA mode for the data can be enabled for reception by setting the RXDMAEN bit in the SPDIFRX_CR register. In this case, as soon as the SPDIFRX_FMTx_DR is not empty, the
SPDIFRX interface sends a transfer request to the DMA. The DMA reads the data received through the SPDIFRX_FMTx_DR register without CPU intervention.
For the use of DMA for the control data refer to Section 37.3.7: Dedicated control flow.
An interrupt line is shared between:
| (omitted) |
Clearing interrupt source
Note: The SBD event can only occur when the SPDIFRX is synchronized to the input stream
(SYNCD = 1).
The SBD flag behavior is not guaranteed when the sub-frame which contains the B
preamble is lost due to an overrun.
The SPDIFRX block embeds some hardware protection avoid erroneous use of control registers. The table hereafter shows the bit field properties according to the SPDIFRX state.
| Registers | Field |
SPDIFRXEN |
||
|---|---|---|---|---|
|
0b00 (STATE_IDLE) |
0b01 (STATE_SYNC) |
0b11 (STATE_RCV) |
||
| SPDIFRX_CR |
INSEL | rw | r | r |
| WFA | rw | r | r |
|
| NBTR | rw | r | r |
|
| CHSEL | rw | r | r |
|
| CBDMAEN | rw | rw | rw |
|
| PTMSK | rw | rw | rw |
|
| CUMSK | rw | rw | rw |
|
| VMSK | rw | rw | rw |
|
| PMSK | rw | rw | rw |
|
| DRFMT | rw | rw | r |
|
| RXSTEO | rw | rw | r |
|
| RXDMAEN | rw | rw | rw |
|
| SPDIFRX_IMR | All fields | rw | rw | rw |
The table clearly shows that fields such as INSEL must be programmed when the IP is in STATE_IDLE. In the others IP states, the hardware prevents writing to this field.
Note: Even if the hardware allows the writing of CBDMAEN and RXDMAEN “on-the-fly”, it is not
recommended to enable the DMA when the IP is already receiving data.
Note: Note that each of the mask bits (PMSK, VMSK, …) can be changed “on-the-fly” at any IP
state, but any change does not affect data which is already being held in
SPDIFRX_FMTx_DR.
The following example illustrates a complete activation sequence of the SPDIFRX block. The data path and channel status & user information will both use a dedicated DMA channel. The activation sequence is then split into the following steps:
A simple way to check if valid data are available into the SPDIFRX_IN line is to switch the SPDIFRX into the STATE_SYNC, with bit WFA set to 1. The description hereafter will focus on detection. It is also possible to implement this function as follow:
Connect the SPDIFRX_IN input to an external interrupt event block in order to detect transitions of SPDIFRX_IN line. When activity is detected, then SPDIFRXEN can be set to 0b01 or 0b11.
For those two implementations, the bit WFA is set to 0.
Enable the generation of the SPDIFRX_CLK. Refer to Table 242 in order to define the minimum clock frequency versus supported audio sampling rate.
that the audio sampling rate of the received stream is not known in advance.
This means that the user has to select a SPDIFRX_CLK frequency at least 704 times higher than the maximum audio sampling rate the application is supposed to handle: for example if the application is able to handle streams to up to 96 kHz, then FSPDIFRX_CLK shall be at least 704 x 96 kHz = 67.6 MHz
Then the CPU will receive interrupts coming either from DMA or SPDIFRX.
When an interrupt from the SPDIFRX is received, then the software has to check what is the source of the interrupt by reading the SPDIFRX_SR register.
If an interrupt is coming from the DMA channel used of the channel status (SPDIFRX_CSR):
If no error occurred (i.e. PERR), the CPU can start the decoding of channel information. For example bit 1 of the channel status informs the user if the current stream is linear or not. This information is very important in order to set-up the proper processing chain. In the same way, bits 24 to 27 of the channel status give the sampling frequency of the stream incoming stream.
Thanks to that information, the user can then configure the RXSTEO bit and DRFMT field prior to start the data reception. For example if the current stream is non linear PCM then RXSTEO is set to 0, and DRFMT is set to 0b10. Then the user can enable the data reception by setting SPDIFRXEN to 0b11.
The bit SOB, when set to 1 indicates the start of a new block. This information will help the software to identify the bit 0 of the channel status. Note that if the DMA generates an interrupt every time 24 values are transferred into the memory, then the first word will always correspond to the start of a new block.
If an interrupt is coming from the DMA channel used of the audio samples (SPDIFRX_FMTx_DR):
The process performed here depends of the data type (linear or non-linear), and on the data format selected.
For example in linear mode, if PE or V bit is set a special processing can be performed locally in order to avoid spurs on output. In non-linear mode those bits are not important as data frame have their own checksum.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INSEL[2:0] |
Res. |
WFA | NBTR[1:0] | CHSEL | CBDMAEN | PTMSK | CUMSK | VMSK | PMSK | DRFMT[1:0] | RXSTEO | RXDMAEN | SPDIFRXEN[1:0] | |||||
| rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bits 18:16 | INSEL[2:0]: SPDIFRX input selection(1) |
|
0b000: SPDIFRX_IN1 selected |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | WFA: Wait for activity(1) |
|
This bit is set/reset by software |
|
| Bits 13:12 | NBTR[1:0]: Maximum allowed re-tries during synchronization phase(1) |
|
0b00: No re-try is allowed (only one attempt) |
|
| Bit 11 | CHSEL: Channel selection(1) |
|
This bit is set/reset by software |
|
| Bit 10 | CBDMAEN: Control buffer DMA enable for control flow(1) |
|
This bit is set/reset by software When this bit is set, the DMA request is made whenever the CSRNE flag is set. |
|
| Bit 9 | PTMSK: Mask of preamble type bits(1) |
|
This bit is set/reset by software |
|
| Bit 8 | CUMSK: Mask of channel status and user bits(1) |
|
This bit is set/reset by software |
|
| Bit 7 | VMSK: Mask of validity bit(1) |
|
This bit is set/reset by software |
|
| Bit 6 | PMSK: Mask parity error bit(1) |
|
This bit is set/reset by software |
|
| Bits 5:4 | DRFMT[1:0]: RX data format(1) |
|
This bit is set/reset by software |
|
| Bit 3 | RXSTEO: Stereo mode(1) |
|
This bit is set/reset by software |
|
| Bit 2 | RXDMAEN: Receiver DMA enable for data flow(1) |
|
This bit is set/reset by software When this bit is set, the DMA request is made whenever the RXNE flag is set. |
|
| Bits 1:0 | SPDIFRXEN[1:0]: Peripheral block enable(1) |
|
This field is modified by software. It shall be used to change the peripheral phase among the three possible states: STATE_IDLE, STATE_SYNC and STATE_RCV. 0b00: Disable SPDIFRX (STATE_IDLE). it is not possible to transition from STATE_RCV to STATE_SYNC, the user shall first go the |
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IFE IE |
SYNCD IE |
SBLK IE |
OVR IE |
PERR IE |
CSRNE IE |
RXNE IE |
| rw | rw | rw | rw | rw | rw | rw |
| Bits 31:7 | Reserved, must be kept at reset value. |
| Bit 6 | IFEIE: Serial Interface Error Interrupt Enable |
|
This bit is set and cleared by software. |
|
| Bit 5 | SYNCDIE: Synchronization Done |
|
This bit is set and cleared by software. |
|
| Bit 4 | SBLKIE: Synchronization Block Detected Interrupt Enable |
|
This bit is set and cleared by software. |
|
| Bit 3 | OVRIE: Overrun error Interrupt Enable |
|
This bit is set and cleared by software. |
|
| Bit 2 | PERRIE: Parity error interrupt enable |
|
This bit is set and cleared by software. |
|
| Bit 1 |
CSRNEIE: Control Buffer Ready Interrupt Enable
|
|
This bit is set and cleared by software. |
|
| Bit 0 | RXNEIE: RXNE interrupt enable |
|
This bit is set and cleared by software. |
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | WIDTH5[14:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TERR | SERR | FERR | SYNCD | SBD | OVR | PERR | CSRNE | RXNE |
||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r |
||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:16 | WIDTH5[14:0]: Duration of 5 symbols counted with SPDIFRX_CLK |
|
This value represents the amount of SPDIFRX_CLK clock periods contained on a length of 5 consecutive symbols. This value can be used to estimate the S/PDIF symbol rate. Its accuracy is limited by the frequency of SPDIFRX_CLK. that WIDTH5 is updated by the hardware when SYNCD goes high, and then every frame. |
|
| Bits 15:9 | Reserved, must be kept at reset value. |
| Bit 8 | TERR: Time-out error |
|
This bit is set by hardware when the counter TRCNT reaches its max value. It indicates that the time interval between two transitions is too long. It generally indicates that there is no valid signal on SPDIFRX_IN input. |
|
| Bit 7 | SERR: Synchronization error |
|
This bit is set by hardware when the synchronization fails due to amount of re-tries for NBTR. |
|
| Bit 6 | FERR: Framing error |
|
This bit is set by hardware when an error occurs during data reception: preamble not at the expected place, short transition not grouped by pairs... |
|
| Bit 5 | SYNCD: Synchronization Done |
|
This bit is set by hardware when the initial synchronization phase is properly completed. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. |
|
| Bit 4 | SBD: Synchronization Block Detected |
|
This bit is set by hardware when a “B” preamble is detected This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if SBLKIE = 1 in the SPDIFRX_IMR register |
|
| Bit 3 | OVR: Overrun error |
|
This bit is set by hardware when a received data is ready to be transferred in the SPDIFRX_FMTx_DR register while RXNE = 1 and both SPDIFRX_FMTx_DR and RX_BUF are full. When this bit is set, the SPDIFRX_FMTx_DR register content will not be lost but the last data |
|
| Bit 2 | PERR: Parity error |
|
This bit is set by hardware when the data and status bits of the sub-frame received contain an odd number of 0 and 1. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. |
|
| Bit 1 | CSRNE: The Control Buffer register is not empty |
|
This bit is set by hardware when a valid control information is ready. This flag is cleared when reading SPDIFRX_CSR register. |
|
| Bit 0 | RXNE: Read data register not empty |
|
This bit is set by hardware when a valid data is available into SPDIFRX_FMTx_DR register. |
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYNCD CF |
SBD CF |
OVR CF |
PERR CF |
Res. | Res. |
| w | w | w | w |
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bit 5 | SYNCDCF: Clears the Synchronization Done flag |
|
Writing 1 in this bit clears the flag SYNCD in the SPDIFRX_SR register. |
|
| Bit 4 | SBDCF: Clears the Synchronization Block Detected flag |
|
Writing 1 in this bit clears the flag SBD in the SPDIFRX_SR register. |
|
| Bit 3 | OVRCF: Clears the Overrun error flag |
|
Writing 1 in this bit clears the flag OVR in the SPDIFRX_SR register. |
|
| Bit 2 | PERRCF: Clears the Parity error flag |
|
Writing 1 in this bit clears the flag PERR in the SPDIFRX_SR register. |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x10
Reset value: 0x0000 0000
This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | PT[1:0] | C | U | V | PE | DR[23:16] |
DR[15:0] |
|||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bits 29:28 | PT[1:0]: Preamble Type |
|
These bits indicate the preamble received. 00: not used that if PTMSK = 1, this field is forced to zero |
|
| Bit 27 | C: Channel Status bit |
|
Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 |
|
| Bit 26 | U: User bit |
|
Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 |
|
| Bit 25 | V: Validity bit |
|
Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 |
|
| Bit 24 | PE: Parity Error bit |
|
Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 |
|
| Bits 23:0 | DR[23:0]: Data value |
|
Contains the 24 received data bits, aligned on D[23] |
Address offset: 0x10
Reset value: 0x0000 0000
This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b01:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DR[23:8] |
DR[7:0] | Res. | Res. | PT[1:0] | C | U | V | PE |
|||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||
| Bits 31:8 | DR[23:0]: Data value |
|
Contains the 24 received data bits, aligned on D[23] |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bits 5:4 | PT[1:0]: Preamble Type |
|
These bits indicate the preamble received. 00: not used that if PTMSK = 1, this field is forced to zero |
|
| Bit 3 | C: Channel Status bit |
|
Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 |
|
| Bit 2 | U: User bit |
|
Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 |
|
| Bit 1 | V: Validity bit |
|
Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 |
|
| Bit 0 | PE: Parity Error bit |
|
Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 |
Address offset: 0x10
Reset value: 0x0000 0000
This register can take 3 different formats according to DRFMT.
The data format proposed when DRFMT = 0b10, is dedicated to non-linear mode, as only 16 bits are used (bits 23 to 8 from S/PDIF sub-frame).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DRNL2[15:0] |
DRNL1[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | DRNL2[15:0]: Data value |
|
This field contains the Channel A |
|
| Bits 15:0 | DRNL1[15:0]: Data value |
|
This field contains the Channel B |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | SOB | CS[7:0] |
USR[15:0] |
||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bit 24 | SOB: Start Of Block |
|
This bit indicates if the bit CS[0] corresponds to the first bit of a new block 0: CS[0] is not the first bit of a new block |
|
| Bits 23:16 | CS[7:0]: Channel A status information |
|
Bit CS[0] is the oldest value |
|
| Bits 15:0 | USR[15:0]: User data information |
|
Bit USR[0] is the oldest value, and comes from channel A, USR[1] comes channel B. So USR[n] bits come from channel A is n is even, otherwise they come from channel B. |
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | TLO[12:0] |
Res. | Res. | Res. | THI[12:0] |
||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bits 28:16 | TLO[12:0]: Threshold LOW (TLO = 1.5 x UI / TSPDIFRX_CLK) |
|
This field contains the current threshold LOW estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of TLO is limited to a period of the SPDIFRX_CLK. The sampling rate can be estimated as follow: that TLO is updated by the hardware when SYNCD goes high, and then every frame. |
|
| Bits 15:13 | Reserved, must be kept at reset value. |
| Bits 12:0 | THI[12:0]: Threshold HIGH (THI = 2.5 x UI / TSPDIFRX_CLK) |
|
This field contains the current threshold HIGH estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of THI is limited to a period of the SPDIFRX_CLK. The sampling rate can be estimated as follow: that THI is updated by the hardware when SYNCD goes high, and then every frame. |
Table 244 gives the SPDIFRX interface register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
SPDIFRX_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INSEL[2:0] | Res. | WFA | NBTR[1:0] | CHSEL | CBDMAEN | PTMSK | CUMSK | VMSK | PMSK | DRFMT[1:0] | RXSTEO | RXDMAEN | SPDIFRXEN[1:0] | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x04 |
SPDIFRX_IMR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IFEIE | SYNCDIE | SBLKIE | OVRIE | PERRIE | CSRNEIE | RXNEIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||
| 0x08 |
SPDIFRX_SR
|
Res. | WIDTH5[14:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TERR | SERR | FERR | SYNCD | SBD | OVR | PERR | CSRNE | RXNE | ||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x0C |
SPDIFRX_ IFCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYNCDCF | SBDCF | OVRCF | PERRCF | Res. | Res. |
| Reset value | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||||
| 0x10 |
SPDIFRX_ FMT0_DR |
Res. | Res. | PT[1:0] | C | U | V | P E |
DR[23:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 |
SPDIFRX_ FMT1_DR |
DR[23:0] | Res. |
PT[1:0] | C | U | V | P E |
|||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 |
SPDIFRX_ FMT2_DR |
DRNL2[15:0] | DRNL1[15:0] |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x14 |
SPDIFRX_ CSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | SOB | CS[7:0] | USR[15:0] |
||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x18 |
SPDIFRX_DIR
|
Res. | Res. | Res. | TLO[12:0] |
Res. | Res. | Res. | THI[12:0] |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
An MDIO bus can be useful in systems where a master chip needs to manage (configure and get status data from) one or multiple slave chips. The bus protocol uses only two signals:
In each transaction, the master either reads the contents of an MDIOS register in one of its slaves, or it writes data to an MDIOS register in one of its slaves.
The MDIOS peripheral serves as a slave interface to an MDIO bus. An MDIO master can use the MDC/MDIO lines to write and read 32 16-bit MDIOS registers which are held in the MDIOS. These MDIOS registers are managed by the firmware, thus allowing the MDIO master to configure the application running on the STM32 and get status information from it.
The MDIOS can operate in Stop mode, optionally waking up the STM32 if the MDIO master performs a read or a write to one of its MDIOS registers.
The MDIOS includes the following features:
| (omitted) |
The MDIOS protocol uses two signals:
Each transaction is performed using a “frame”. Each frame contains 32 bits: 14 control bits, 2 turn-around bits, and then 16 data bits, each passed serially.
Each frame is usually preceded by a preamble, where the MDIOS stays at ‘1’ for 32 MDC clocks. The master can continue to keep MDIO at ‘1’, indicating the “idle” condition, when it has no frame to send.
When MDIO signal is driven by the master, MDIOS samples it using the rising edge of MDC. When MDIOS drives MDIO, the output changes on the rising edge of MDC.
| (omitted) |
| (omitted) |
The MDIOS is enabled by setting the EN bit in the MDIOS_CR register. When EN=1, the MDIOS monitors the MDIO bus and service frames addressed to one of its MDIOS registers.
When the MDIOS is enabled (setting EN to ‘1’), the same write operation to the MDIOS_CR register must properly set the PORT_ADDRESS[4:0] field to indicate the slave port address. A frame is ignored by the MDIOS if its port address is not the same as PORT_ADDRESS[4:0] (presumably intended for another slave).
When EN=0, the MDIOS ignores the frames being transmitted on the MDC/MDIO lines, and the IP is in a reduced consumption mode. Clearing EN also clears all of the DIN registers. If EN is cleared while the MDIOS is driving read data, it immediately releases the bus and does not drive the rest of the data. If EN is cleared while the MDIOS is receiving a frame, the frame is aborted and the data is lost.
When the MDIOS is enabled, then disabled and subsequently re-enabled, the status flags are not cleared. For a correct operation the firmware shall clear the status flag before re-enabling the MDIOS.
From the point of view of the MDIO master, there are 32 16-bit MDIOS registers in the MDIOS which can be written and read. In reality, for each MDIOS register ‘n’ there are two sets of registers: DINn[15:0] and DOUTn[15:0].
Input data
When the MDIO master transmits a frame which writes to MDIOS register ‘n’ in the MDIOS, it is the DINn[15:0] register which is updated with the incoming data. The DIN registers (DIN0 - DIN31) can be read by the firmware, but they can be written only by the MDIO master via the MDIO bus.
The contents of DINn change immediately after the MDC rising edge when the last data bit is sampled.
If the firmware happens to read the contents of DINn at the moment that it is being updated, there is a possibility that the value read is corrupted (a bit-by-bit cross between the old value and the new value). For this reason, the frmware should assure that two subsequent
reads from the same DINn register give the same value and assure that the data was
stable when it was read. In the very worst case, the firmware would need to read DINn four times: first to get the old value, second to get an incoherent value (when reading at the moment the register changes), third to get the new value, and forth to confirm the new value.
If the firmware uses the WRF interrupt and can guarantee that it reads the DINn register before any new MDIOS write frame completes, the firmware can perform a single read.
If the MDIO master performs a write operation with a register address that is greater than 31, the MDIOS ignores the frame (the data is not saved and no flag is set).
Output data
When the MDIOS receives a frame which requests to read register ‘n’, it returns the value found in the DOUTn[15:0] register. Thus, if the MDIO master expects to read the same value which it previously wrote to MDIOS register ‘n’, the firmware must copy the data from DINn to DOUTn each time new data is written to DINn. For correct operation, the firmware must copy the data to the DOUTn register within a preamble (if the master sends preambles before each frame) plus 15 cycles time.
When an MDIOS register is read via the MDIO bus, the MDIOS passes the 16-bit value (from the corresponding DOUTn register) to the MDIOS clock domain during the 15th cycle of the read frame. If the firmware attempts to write the DOUTn register while the MDIO Master is currently reading MDIOS register ‘n’, then the firmware write operation will be ignored if it occurs during the 15th cycle of the frame (during a one-MDC-cycle window). Therefore, after writing a DOUTn register, the firmware should read back the same
DOUTn register and confirm that the value was actually written. If the DOUTn register does not contain the value which was written, then the firmware can simply try writing and re-reading again.
If the MDIOS frequency is very slow compared to the PCLK frequency, then it might be best not to tie up the CPU by continuously writing and re-reading a DOUT register. Please note that the read flag (RDFn) is set as soon as the DOUTn value is passed to the MDIOS clock domain. Thus, when a write to DOUTn is ignored (when the value read back is not the value which was just written), then the firmware can use a read interrupt to know when it is able to write DOUTn.
Here is a procedure which can be used if the MDC clock is very slow:
If the MDIO master performs a read operation with a register address which is greater than 31, the MDIOS returns a data value of all zeros.
Whenever the firmware reads from an MDIOS_DINRn register or writes to an MDIOS_DOUTRn register, the frequency of the APB bus must be at least 1.5 times the MDC frequency. For example, if MDC is at 20MHz, the APB must be at 30MHz or faster.
When MDIOS register ‘n’ is written via the MDIO bus, the WRFn bit in the MDIOS_WRFR register is set. WRFn becomes ‘1’ a the moment that DINn is updated, which is when the last data bit is sampled on a write frame. An interrupt is generated if WRIEN=1 (in the MDIOS_CR register). WRFn is cleared by software by writing ‘1’ to CWRFn (in the MDIOS_CWRFR register).
When MDIOS register ‘n’ is read via the MDIO bus, the RDFn bit in the MDIOS_RDFR register is set. RDFn becomes ‘1’ at the moment that DOUTn is copied to the MDC clock domain, which is on the 15th cycle of a read frame. An interrupt is generated if RDIEN=1 (in the MDIOS_CR register). RDFn is cleared by software by writing ‘1’ to CRDFn (in the MDIOS_CRDFR register).
There are three types of errors with their corresponding error flags:
Each error flag is set by hardware when the corresponding error condition occurs. Each flag can be cleared by writing ‘1’ to the corresponding bit in the clear flag register (MDIOS_CLRFR).
An interrupt occurs if any of the three error flags is set while EIE=1 (MDIOS_CR).
Besides setting an error flag, the MDIOS performs no action for a frame in which an error is detected: the DINn registers are not updated and the MDIO line is not forced during the data phase.
For a given frame, errors do not accumulate. For example, if a preamble error is detected, no check is done for a start error or a turnaround error for the rest of the current frame.
When DPC=0, following an detected error, all new frames and errors will be ignored until a complete full preamble has been detected.
When DPC=1 (Disable Preamble Check, MDIOS_CR[7]), all frames and new errors are ignored as long as one of the error flags is set. As soon as the error bit is cleared, the MDIOS starts looking for a start sequence. Thus, the application must clear the error flag only when it is sure that no frame is currently in progress. Otherwise, the MDIOS will likely misinterpret the bits being sent and become desynchronized with the master.
Preamble errors
A preamble error occurs when a start sequence begins (with MDIO sampled at ‘0’) without being immediately preceded by a preamble (MDIO sampled at ‘1’ for at least 32 consecutive clocks).
Preamble errors are not reported after the MDIOS is first enabled (EN=1 in MDIOS_CR) until after a full preamble is received. This is to avoid an error condition when the peripheral frame detection is enabled while a preamble or frame is already in progress. In this case, the MDIOS ignores the first frame (since it did not first detect a full preamble), but does not set PERF.
If the DPC bit (Disable Preamble Check, MDIOS_CR[7]) is set, then the MDIO Master can send frames without preceding preambles and no preamble error will be signaled. When DPC=1, the application must assure that the master is not in the process of sending a frame at the moment that the MDIOS is enabled (EN is set). Otherwise, the slave might become desynchronized with the master.
Start errors
A start error occurs when an illegal start sequence occurs or if an illegal command is given. The start sequence must always be “01”, and the command must be either “01” (write) or “10” (read).
As with preamble errors, start errors are not reported until after a full preamble is received.
Turnaround errors
A turnaround error occurs when an error is detected in the turnaround bits of write frames. The 15th bit of the write frame must be ‘1’ and the 16th bit must be ‘0’.
Turnaround errors are only reported after a full preamble is received, there is no start error, the port address in the current frame matches and the register address is in the supported range 0 to 31.
The MDIOS can operate in Stop mode, responding to all reads, performing all writes, and causing the STM32 to wakeup from Stop mode on MDIOS interrupts.
There is a single interrupt vector for the three types of interrupts (write, read, and error). Any of these interrupt sources can wake the STM32 up from Stop mode. All interrupt flags need to be cleared in order to clear the interrupt line.
| Interrupt event | Event flag | Enable control bit |
|---|---|---|
| Write interrupt | WRF[31:0] | WRIE |
| Read interrupt | RDF[31:0] | RDIE |
| Error interrupt |
PERF (preamble), SERF (start), TERF (turnaround) |
EIE |
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | PORT_ADDRESS[4:0] | DPC | Res. | Res. | Res. | EIE | RDIE | WRIE | EN |
||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bits 12:8 | PORT_ADDRESS[4:0]: Slave’s address. |
|
Can be written only when the peripheral is disabled (EN=0). If the address given by the MDIO master matches PORT_ADRESS[4:0], then the MDIOS services the frame. Otherwise the frame is ignored. |
|
| Bit 7 | DPC: Disable Preamble Check. |
|
0: MDIO Master must give preamble before each frame. 1: MDIO Master can send each frame without a preceding preamble, and the MDIOS will not signal a preamble error. When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. This bit cannot be changed unless EN=0 (though it can be changed at the same time that EN is being set). |
|
| Bits 6:4 | Reserved, must be kept at reset value. |
| Bit 3 | EIE: Error interrupt enable. |
|
0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set. |
|
| Bit 2 | RDIE: Register Read Interrupt Enable. |
|
0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the read flags (RDF[31:0] in the MDIOS_RDFR register) is set. |
|
| Bit 1 | WRIE: Register write interrupt enable. |
|
0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the read flags (WRF[31:0] in the MDIOS_WRFR register) is set. |
|
| Bit 0 | EN: Peripheral enable. |
|
0: MDIOS is disabled 1: MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO) |
Address offset: 0x04
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WRF[31:16] |
WRF[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | WRF[31:0]: Write flags for MDIOS registers 0 to 31. |
|
Each bit is set by hardware when the MDIO master performs a write to the corresponding MDIOS register. An interrupt is generates if WRIE (in MDIOS_CR) is set. Each bit is cleared by software by writing ‘1’ to the corresponding CWRF bit in the MDIOS_CWRFR register. For WRFn: 0: MDIOS register ‘n’ has not been written by the MDIO master |
Address offset: 0x08
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CWRF[31:16] |
CWRF[15:0] |
||||||||||||||||||||||||||||||
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:0 | CWRF[31:0]: Clear the write flag |
|
Writing ‘1’ to CWRFn clears the WRFn bit in the MDIOS_WRF register. |
Address offset: 0x0C
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RDF[31:16] |
RDF[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | RDF[31:0]: Read flags for MDIOS registers 0 to 31. |
|
Each bit is set by hardware when the MDIO master performs a read from the corresponding MDIOS register. An interrupt is generates if RDIE (in MDIOS_CR) is set. Each bit is cleared by software by writing ‘1’ to the corresponding CRDF bit in the MDIOS_CRDFR register. For RDFn: 0: MDIOS register ‘n’ has not been read by the MDIO master |
Address offset: 0x10
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CRDF[31:16] |
CRDF[15:0] |
||||||||||||||||||||||||||||||
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:0 | CRDF[31:0]: Clear the read flag |
|
Writing ‘1’ to CRDFn clears the RDFn bit in the MDIOS_RDF register. |
Address offset: 0x14
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TERF | SERF | PERF |
| r | r | r |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | TERF: Turnaround error flag |
|
0: No turnaround error has occurred Writing ‘1’ to CTERF (MDIOS_CLRFR) clears this bits. |
|
| Bit 1 | SERF: Start error flag |
|
0: No start error has occurred Writing ‘1’ to CSERF (MDIOS_CLRFR) clears this bits. |
|
| Bit 0 | PERF: Preamble error flag |
|
0: No preamble error has occurred Writing ‘1’ to CPERF (MDIOS_CLRFR) clears this bits. This bit will not get set if DPC (Disable Preamble Check, MDIOS_CR[7]) is set. |
Note: Writes to MDIOS_SR have no effect.
Address offset: 0x18
Power-on reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CTERF | CSERF | CPERF |
| rc_w1 | rc_w1 | rc_w1 |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | CTERF: Clear the turnaround error flag |
|
Writing ‘1’ to this bit clears the TERF flag (MDIOS_SR). When DPC=’1’ (MDIOS_CR[7]), the TERF flag must be cleared only when there is not a frame already in progress. |
|
| Bit 1 | CSERF: Clear the start error flag |
|
Writing ‘1’ to this bit clears the SERF flag (MDIOS_SR). When DPC=’1’ (MDIOS_CR[7]), the SERF flag must be cleared only when there is not a frame already in progress. |
|
| Bit 0 | CPERF: Clear the preamble error flag |
|
Writing ‘1’ to this bit clears the PERF flag (MDIOS_SR). |
Note: Reading MDIOS_CLRFR returns all zeros.
Address offset: 0x100-0x17C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DINn[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | DINn[15:0]: Input data received from MDIO Master during write frames |
|
This field written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register ‘n’. |
Address offset: 0x180-0x1FC
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DOUTn[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | DOUTn[15:0]: Output data sent to MDIO Master during read frames |
|
This field is written by SW. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register ‘n’. |
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
MDIOS_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PORT_ ADDRESS[4:0] |
Res. | Res. | Res. | Res. | EEI | RDIE | WRIE | EN | ||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x04 | MDIOS_WRFR | WRF[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x08 | MDIOS_CWRFR | CWRF[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C | MDIOS_RDFR | RDF[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 | MDIOS_CRDFR | CRDF[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x14 |
MDIOS_SR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TERF | SERF | PERF |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x18 |
MDIOS_CLRFR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CTERF | CSERF | CPERF |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x1C - 0xFC |
Reserved
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x100 |
MDIOS_DINR0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DIN0[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x104 |
MDIOS_DINR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DIN1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| ... |
|||||||||||||||||||||||||||||||||
| 0x17C |
MDIOS_DINR31
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DIN31[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x180 |
MDIOS_DOUTR0
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOUT0[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x184 |
MDIOS_DOUTR1
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOUT1[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| ... | |||||||||||||||||||||||||||||||||
| 0x1FC |
MDIOS_DOUTR31
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DOUT31[15:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The SD/SDIO MMC card host interface (SDMMC) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards.
The MultiMediaCard system specifications are available through the MultiMediaCard Association website, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card Association website.
The SDMMC features include the following:
Note: 1 The SDMMC does not have an SPI-compatible communication mode.
2 The SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the
MultiMediaCard system specification V2.11. Several commands required for SD memory
devices are not supported by either SD I/O-only cards or the I/O portion of combo cards.
Some of these commands have no use in SD I/O devices, such as erase commands, and
thus are not supported in the SDIO protocol. In addition, several commands are different
between SD memory cards and SD I/O cards and thus are not supported in the SDIO
protocol. For details refer to SD I/O card Specification Version 1.0.
The MultiMediaCard/SD bus connects cards to the controller.
The current version of the SDMMC supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.
Communication over the bus is based on command and data transfers.
The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token.
Data transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers to/from MMC are done data blocks or streams.
| (omitted) |
| (omitted) |
| (omitted) |
Note: The SDMMC will not send any data as long as the Busy signal is asserted (SDMMC_D0
pulled low).
| (omitted) |
| (omitted) |
The SDMMC consists of two parts:
| (omitted) |
By default SDMMC_D0 is used for data transfer. After initialization, the host can change the databus width.
If a MultiMediaCard is connected to the bus, SDMMC_D0, SDMMC_D[3:0] or SDMMC_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDMMC_D0 can be used.
If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host to use SDMMC_D0 or SDMMC_D[3:0]. All data lines are operating in push-pull mode.
SDMMC_CMD has two operational modes:
SDMMC_CK is the clock to the card: one bit is transferred on both command and data lines with each clock cycle.
The SDMMC uses two clock signals:
PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
Frequenc( PCLK2 ) > ((3xWidth ) ⁄ 32 ) × Frequency( SDMMC_CK )
The signals shown in Table 247 are used on the MultiMediaCard/SD/SD I/O card bus.
| Pin | Direction | Description |
|---|---|---|
| SDMMC_CK | Output | MultiMediaCard/SD/SDIO card clock. This pin is the clock from host to card. |
| SDMMC_CMD | Bidirectional | MultiMediaCard/SD/SDIO card command. This pin is the bidirectional command/response signal. |
| SDMMC_D[7:0] | Bidirectional | MultiMediaCard/SD/SDIO card data. These pins are the bidirectional databus. |
Figure 484 shows a simplified block diagram of an SDMMC adapter.
| (omitted) |
The SDMMC adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits:
Note: The adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit,
command path and data path use the SDMMC adapter clock domain (SDMMCCLK).
Adapter register block
The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location in the SDMMC Clear register.
Control unit
The control unit contains the power management functions and the clock divider for the memory card clock.
There are three power phases:
| (omitted) |
The control unit is illustrated in Figure 485. It consists of a power management subunit and a clock management subunit.
The power management subunit disables the card bus output signals during the power-off and power-up phases.
The clock management subunit generates and controls the SDMMC_CK signal. The SDMMC_CK output can use either the clock divide or the clock bypass mode. The clock output is inactive:
The clock management subunit controls SDMMC_CK dephasing. When not in bypass mode the SDMMC command and data output are generated on the SDMMCCLK falling edge succeeding the rising edge of SDMMC_CK. (SDMMC_CK rising edge occurs on SDMMCCLK rising edge) when SDMMC_CLKCR[13] bit is reset (NEGEDGE = 0). When SDMMC_CLKCR[13] bit is set (NEGEDGE = 1) SDMMC command and data changed on the SDMMC_CK falling edge.
When SDMMC_CLKCR[10] is set (BYPASS = 1), SDMMC_CK rising edge occurs on SDMMCCLK rising edge. The data and the command change on SDMMCCLK falling edge whatever NEGEDGE value.
The data and command responses are latched using SDMMC_CK rising edge.
| (omitted) |
Command path
The command path unit sends commands to and receives responses from the cards.
| (omitted) |
| (omitted) |
When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered.
Note: The command timeout has a fixed value of 64 SDMMC_CK clock periods.
If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits for an interrupt request from one of the cards. If a pending bit is set in the command register, the CPSM enters the Pend state, and waits for a CmdPend signal from the data path subunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the data counter to trigger the stop command transmission.
Note: The CPSM remains in the Idle state for at least eight SDMMC_CK periods to meet the NCC
and NRC timing constraints. NCC is the minimum delay between two host commands, and
NRC is the minimum delay between the host command and the card response.
| (omitted) |
Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the CMD line. All commands have a fixed length of 48 bits. The general format for a command token for MultiMediaCards, SD-Memory cards and SDIO-Cards is shown in Table 248.
The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the Send state, the SDMMC_CMD output is in the Hi-Z state, as shown in Figure 489 on page 1480. Data on SDMMC_CMD are synchronous with the rising edge of SDMMC_CK. Table 248 shows the command format.
| Bit position | Width | Value | Description |
|---|---|---|---|
| 47 | 1 | 0 | Start bit |
| 46 | 1 | 1 | Transmission bit |
| [45:40] | 6 | - | Command index |
| [39:8] | 32 | - | Argument |
| [7:1] | 7 | - | CRC7 |
| 0 | 1 | 1 | End bit |
The SDMMC supports two response types. Both use CRC error checking:
Note: If the response does not contain a CRC (CMD1 response), the device driver must ignore the
CRC failed status.
| Bit position | Width | Value | Description |
|---|---|---|---|
| 47 | 1 | 0 | Start bit |
| 46 | 1 | 0 | Transmission bit |
| [45:40] | 6 | - | Command index |
| [39:8] | 32 | - | Argument |
| [7:1] | 7 | - | CRC7(or 1111111) |
| 0 | 1 | 1 | End bit |
| Bit position | Width | Value | Description |
|---|---|---|---|
| 135 | 1 | 0 | Start bit |
| 134 | 1 | 0 | Transmission bit |
| [133:128] | 6 | 111111 | Reserved |
| [127:1] | 127 | - | CID or CSD (including internal CRC7) |
| 0 | 1 | 1 | End bit |
The command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long (see Section 39.8.4 on page 1516). The command path implements the status flags shown in Table 251:
| Flag | Description |
| CMDREND | Set if response CRC is OK. |
| CCRCFAIL | Set if response CRC fails. |
| CMDSENT | Set when command (that does not require response) is sent |
| CTIMEOUT | Response timeout. |
| CMDACT | Command transfer in progress. |
The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long response format. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation.
The CRC checksum is a 7-bit value:
CRC[6:0] = Remainder [(M(x) * x7) / G(x)]
G(x) = x7 + x3 + 1
M(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or
M(x) = (start bit) * x119 + ... + (last bit before CRC) * x0
Data path
The data path subunit transfers data to and from cards. Figure 490 shows a block diagram of the data path.
| (omitted) |
The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (SDMMC_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (SDMMC_D[7:0]). If the wide bus mode is not enabled, only one bit per clock cycle is transferred over SDMMC_D0.
Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled:
Data path state machine (DPSM)
The DPSM operates at SDMMC_CK frequency. Data on the card bus signals is synchronous to the rising edge of SDMMC_CK. The DPSM has six states, as shown in Figure 491: Data path state machine (DPSM).
| (omitted) |
Receive: serial data received from a card is packed in bytes and written to the data FIFO. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream:
If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state:
Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing
requirements, where NWR is the number of clock cycles between the reception of the card
response and the start of the data transfer from the host.
Send: the DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream:
If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state.
Busy: the DPSM waits for the CRC status flag:
If a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and moves to the Idle state.
The data timer is enabled when the DPSM is in the Wait_R or Busy state, and generates the data timeout error:
| Description | Start bit | Data | CRC16 | End bit |
|---|---|---|---|---|
| Block Data | 0 | - | yes | 1 |
| Stream Data | 0 | - | no | 1 |
DPSM Flags
The status of the data path subunit transfer is reported by several status flags
| Flag | Description |
|---|---|
| DBCKEND |
Set to high when data block send/receive CRC check is passed. In SDIO multibyte transfer mode this flag is set at the end of the transfer (a multibyte transfer is considered as a single block transfer by the host). |
| DATAEND |
Set to high when SDMMC_DCOUNT register decrements and reaches 0. DATAEND indicates the end of a transfer on SDMMC data line. |
| DTIMEOUT |
Set to high when data timeout period is reached. When data timer reaches zero while DPSM is in Wait_R or Busy state, timeout is set. DTIMEOUT can be set after DATAEND if DPSM remains in busy state for longer than the programmed period. |
| DCRCFAIL | Set to high when data block send/receive CRC check fails. |
Data FIFO
The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.
The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. Because the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the subunits in the SDMMC clock domain (SDMMCCLK) are resynchronized.
Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive:
Transmit FIFO:
Data can be written to the transmit FIFO through the APB2 interface when the SDMMC is enabled for transmission.
The transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO contains a data output register that holds the data word pointed to by the read pointer. When the data path subunit has loaded its shift register, it increments the read pointer and drives new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit asserts TXACT when it transmits data.
| Flag | Description |
|---|---|
| TXFIFOF | Set to high when all 32 transmit FIFO words contain valid data. |
| TXFIFOE | Set to high when the transmit FIFO does not contain valid data. |
| TXFIFOHE | Set to high when 8 or more transmit FIFO words are empty. This flag can be used as a DMA request. |
| TXDAVL | Set to high when the transmit FIFO contains valid data. This flag is the inverse of the TXFIFOE flag. |
| TXUNDERR |
Set to high when an underrun error occurs. This flag is cleared by writing to the SDMMC Clear register. Note: In case of TXUNDERR, and DMA is used to fill SDMMC FIFO, user |
Receive FIFO
When the data path subunit receives a word of data, it drives the data on the write databus. The write pointer is incremented after the write operation completes. On the read side, the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus. If the receive FIFO is disabled, all status flags are deasserted, and the read and write pointers are reset. The data path subunit asserts RXACT when it receives data. Table 255 lists the receive FIFO status flags. The receive FIFO is accessible via 32 sequential addresses.
| Flag | Description |
|---|---|
| RXFIFOF | Set to high when all 32 receive FIFO words contain valid data |
| RXFIFOE | Set to high when the receive FIFO does not contain valid data. |
| RXFIFOHF | Set to high when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA request. |
| RXDAVL | Set to high when the receive FIFO is not empty. This flag is the inverse of the RXFIFOE flag. |
| RXOVERR |
Set to high when an overrun error occurs. This flag is cleared by writing to the SDMMC Clear register. Note: In case of RXOVERR, and DMA is used to read SDMMC FIFO, user |
The APB2 interface generates the interrupt and DMA requests, and accesses the SDMMC adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic.
SDMMC interrupts
The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. A mask register is provided to allow selection of the conditions that will generate an interrupt. A status flag generates the interrupt request if a corresponding mask flag is set.
SDMMC/DMA interface
SDMMC APB interface controls all subunit to perform transfers between the host and card
Example of read procedure using DMA
Send CMD17 (READ_BLOCK) as follows:
Note: When FIFO overrun error occurs with last 1-4 bytes, it may happens that RXOVERR flag is
set 2 APB clock cycles after DATAEND flag is set. To guarantee success of read operation
RXOVERR must be cheked after FIFO is empty.
Example of write procedure using DMA
Send CMD24 (WRITE_BLOCK) as follows:
DMA configuration for SDMMC controller
Note: SDMMC host allows only to use the DMA in peripheral flow controller mode. DMA stream
used to serve SDMMC must be configured in peripheral flow controller mode
SDMMC generates only DMA burst requests to DMA controller. DMA must be configured in
incremental burst mode on peripheral side.
While in card identification mode the host resets all cards, validates the operation voltage range, identifies cards and sets a relative card address (RCA) for each card on the bus. All data communications in the card identification mode use the command line (CMD) only.
The GO_IDLE_STATE command (CMD0) is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high-impedance state and the cards are initialized with a default relative card address (RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability).
All cards can communicate with the SDMMC card host using any operating voltage within the specification range. The supported minimum and maximum VDD values are defined in the operation conditions register (OCR) on the card.
Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer VDD
conditions. When the SDMMC card host module and the card have incompatible VDD
ranges, the card is not able to complete the identification cycle and cannot send CSD data. For this purpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 for SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a mechanism to identify and reject cards that do not match the VDD range desired by the SDMMC card host. The SDMMC card host sends the required VDD voltage window as the operand of these commands. Cards that cannot perform data transfer in the specified range disconnect from the bus and go to the inactive state.
By using these commands without including the voltage range as the operand, the SDMMC card host can query each card and determine the common voltage range before placing out-of-range cards in the inactive state. This query is used when the SDMMC card host is able to select a common voltage range or when the user requires notification that cards are not usable.
The card identification process differs for MultiMediaCards and SD cards. For MultiMediaCard cards, the identification process starts at clock rate Fod. The SDMMC_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows:
addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull.
For the SD card, the identification process starts at clock rate Fod, and the SDMMC_CMD line output drives are push-pull drivers instead of open-drain. The registration process is accomplished as follows:
For the SD I/O card, the registration process is accomplished as follows:
During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. A card supporting block write is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, the card indicates the failure on the SDMMC_D line and the transferred data are discarded and not written, and all further transmitted blocks (in multiple block write mode) are ignored.
If the host uses partial blocks whose accumulated length is not block aligned and, block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment error before the beginning of the first misaligned block. (ADDRESS_ERROR error bit is set in the status register). The write operation will also be aborted if the host tries to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.
Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corresponding part of the receive buffer. If this match fails, then the card reports an error and does not change any register contents.
Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDMMC_D line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The READY_FOR_DATA status bit indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to select a different card), which will place the card in the Disconnect state and release the SDMMC_D line(s) without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling SDMMC_D to low if programming is still in progress and the write buffer is unavailable.
In Block read mode the basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and end addresses are entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and after completing the transfer, the card returns to the Transfer state.
CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.
The host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command.
If the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state. The host must than abort the operation by sending the stop transmission command. The read error is reported in the response to the stop transmission command.
If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the status register).
In stream mode, data is transferred in bytes and no CRC is appended at the end of each block.
Stream write (MultiMediaCard only)
WRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDMMC card host to the card, beginning at the specified address and continuing until the SDMMC card host issues a stop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is set), the data stream can start and stop at any address within the card address space, otherwise it can only start and stop at block boundaries. Because the amount of data to be transferred is not determined in advance, a CRC cannot be used. When the end of the memory range is reached while sending data and no stop command is sent by the SDMMC card host, any additional transferred data are discarded.
The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register:
(8× 2writebllen ) (–NSAC
)
If the host attempts to use a higher frequency, the card may not be able to process the data and stop programming, set the OVERRUN error bit in the status register, and while ignoring all further data transfer, wait (in the receive data state) for a stop command. The write operation is also aborted if the host tries to write over a write-protected area. In this case, however, the card sets the WP_VIOLATION bit.
Stream read (MultiMediaCard only)
READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer.
This command instructs the card to send its data, starting at a specified address, until the SDMMC card host sends STOP_TRANSMISSION (CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command. When the end of the memory range is reached while sending data and no stop command is sent by the SDMMC card host, any subsequent data sent are considered undefined.
The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register.
(8× 2readbllen ) (–NSAC
)
If the host attempts to use a higher frequency, the card is not able to sustain data transfer. If this happens, the card sets the UNDERRUN error bit in the status register, aborts the transmission and waits in the data state for a stop command.
The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD.
The host can erase a contiguous range of Erase Groups. Starting the erase process is a three-step sequence.
First the host defines the start address of the range using the ERASE_GROUP_START (CMD35) command, next it defines the last address of the range using the ERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing the ERASE (CMD38) command. The address field in the erase commands is an Erase Group address in byte units. The card ignores all LSBs below the Erase Group size, effectively rounding the address down to the Erase Group boundary.
If an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR bit in the status register and resets the whole sequence.
If an out-of-sequence (neither of the erase commands, except SEND_STATUS) command received, the card sets the ERASE_RESET status bit in the status register, resets the erase sequence and executes the last command.
If the erase range includes write protected blocks, they are left intact and only nonprotected blocks are erased. The WP_ERASE_SKIP status bit in the status register is set.
The card indicates that an erase is in progress by holding SDMMC_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card.
Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE (CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only valid in a transfer state, which means that the bus width can be changed only after a card is selected by SELECT/DESELECT_CARD (CMD7).
Three write protection methods for the cards are supported in the SDMMC card host module:
Internal card write protection
Card data can be protected against write and erase. By setting the permanent or temporary write-protect bits in the CSD, the entire card can be permanently write-protected by the manufacturer or content provider. For cards that support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the data can be protected, and the write protection can be changed by the application. The write protection is in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT and CLR_WRITE_PROT commands control the protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command. The card sends
a data block containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units.
The card ignores all LSBs below the group size.
Mechanical write protect switch
A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card. When the sliding tab is positioned with the window open, the card is write-protected, and when the window is closed, the card contents can be changed. A matched switch on the socket side indicates to the SDMMC card host module that the card is write-protected. The SDMMC card host module is responsible for protecting the card. The position of the write protect switch is unknown to the internal circuitry of the card.
Password protect
The password protection feature enables the SDMMC card host module to lock and unlock a card with a password. The password is stored in the 128-bit PWD register and its size is set in the 8-bit PWD_LEN register. These registers are nonvolatile so that a power cycle does not erase them. Locked cards respond to and execute certain commands. This means that the SDMMC card host module is allowed to reset, initialize, select, and query for status, however it is not allowed to access data on the card. When the password is set (as indicated by a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with the CSD and CID register write commands, the lock/unlock commands are available in the transfer state only. In this state, the command does not include an address argument and the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock). The command data block size is defined by the SDMMC card host module before it sends the card lock/unlock command, and has the structure shown in Table 269.
The bit settings are as follows:
The following sections list the command sequences to set/reset a password, lock/unlock the card, and force an erase.
Setting the password
When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command.
The password length field (PWD_LEN) indicates whether a password is currently set. When this field is nonzero, there is a password set and the card locks itself after power-up. It is possible to lock the card immediately in the current power session by setting the LOCK_UNLOCK bit (while setting the password) or sending an additional command for card locking.
Resetting the password
Locking a card
It is possible to set the password and to lock the card in the same sequence. In this case, the SDMMC card host module performs all the required steps for setting the password (see Setting the password on page 1494), however it is necessary to set the LOCK_UNLOCK bit in Step 3 when the new password command is sent.
When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Unlocking the card
The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up.
An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Forcing erase
If the user has forgotten the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation erases all card data and all password data.
An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previously issued command.
Table 256 defines the different entries of the status. The type and clear condition fields in the table are abbreviated as follows:
Type:
Clear condition:
| Bits | Identifier | Type | Value | Description | Clear condition |
|---|---|---|---|---|---|
| 31 | ADDRESS_ OUT_OF_RANGE | E R X |
’0’= no error ’1’= error |
The command address argument was out of the allowed range for this card. A multiple block or stream read/write operation is (although started in a valid address) attempting to read or write beyond the card capacity. |
C |
| 30 | ADDRESS_MISALIGN | - |
’0’= no error ’1’= error |
The commands address argument (in accordance with the currently set block length) positions the first data block misaligned to the card physical blocks. A multiple block read/write operation (although started with a valid address/block-length combination) is attempting to read or write a data block which is not aligned with the physical blocks of the card. |
C |
| 29 | BLOCK_LEN_ERROR | - |
’0’= no error ’1’= error |
Either the argument of a SET_BLOCKLEN command exceeds the maximum value allowed for the card, or the previously defined block length is illegal for the current command (e.g. the host issues a write command, the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks) | C |
| 28 | ERASE_SEQ_ERROR | - | ’0’= no error ’1’= error |
An error in the sequence of erase commands occurred. | C |
| 27 | ERASE_PARAM | E X | ’0’= no error ’1’= error | An invalid selection of erase groups for erase occurred. | C |
| 26 | WP_VIOLATION | E X | ’0’= no error ’1’= error | Attempt to program a write-protected block. | C |
| 25 | CARD_IS_LOCKED | S R | ‘0’ = card unlocked ‘1’ = card locked |
When set, signals that the card is locked by the host | A |
| 24 | LOCK_UNLOCK_ FAILED | E X | ’0’= no error ’1’= error | Set when a sequence or password error has been detected in lock/unlock card command | C |
| 23 | COM_CRC_ERROR | E R | ’0’= no error ’1’= error | The CRC check of the previous command failed. | B |
| 22 | ILLEGAL_COMMAND | E R | ’0’= no error ’1’= error | Command not legal for the card state | B |
| 21 | CARD_ECC_FAILED | E X | ’0’= success ’1’= failure |
Card internal ECC was applied but failed to correct the data. | C |
| 20 | CC_ERROR | E R | ’0’= no error ’1’= error |
(Undefined by the standard) A card error occurred, which is not related to the host command. | C |
| 19 | ERROR | E X | ’0’= no error ’1’= error | (Undefined by the standard) A generic card error related to the (and detected during) execution of the last host command (e.g. read or write failures). | C |
| 18 | Reserved |
||||
| 17 | Reserved |
||||
| 16 | CID/CSD_OVERWRITE | E X | ’0’= no error ‘1’= error | Can be either of the following errors:
|
C |
| 15 | WP_ERASE_SKIP | E X | ’0’= not protected ’1’= protected |
Set when only partial address space was erased due to existing write |
C |
| 14 | CARD_ECC_DISABLED | S X | ’0’= enabled ’1’= disabled |
The command has been executed without using the internal ECC. | A |
| 13 | ERASE_RESET | - | ’0’= cleared ’1’= set | An erase sequence was cleared before executing because an out of erase sequence command was received (commands other than CMD35, CMD36, CMD38 or CMD13) | C |
| 12:9 | CURRENT_STATE | S R |
0 = Idle 1 = Ready 2 = Ident 3 = Stby 4 = Tran 5 = Data 6 = Rcv 7 = Prg 8 = Dis 9 = Btst 10-15 = reserved |
The state of the card when receiving the command. If the command execution causes a state change, it will be visible to the host in the response on the next command. The four bits are interpreted as a binary number between 0 and 15. | B |
| 8 | READY_FOR_DATA | S R | ’0’= not ready ‘1’ = ready |
Corresponds to buffer empty signalling on the bus | - |
| 7 | SWITCH_ERROR | E X | ’0’= no error ’1’= switch error |
If set, the card did not switch to the expected mode as requested by the SWITCH command | B |
| 6 | Reserved |
||||
| 5 | APP_CMD | S R | ‘0’ = Disabled ‘1’ = Enabled | The card will expect ACMD, or an indication that the command has been interpreted as ACMD |
C |
| 4 | Reserved for SD I/O Card |
||||
| 3 | AKE_SEQ_ERROR | E R | ’0’= no error ’1’= error | Error in the sequence of the authentication process | C |
| 2 | Reserved for application specific commands | ||||
| 1 |
Reserved for manufacturer test mode | ||||
| 0 |
|||||
The SD status contains status bits that are related to the SD memory card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits. The contents of this register are transmitted to the SDMMC card host if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in transfer state only (card is selected).
Table 257 defines the different entries of the SD status register. The type and clear condition fields in the table are abbreviated as follows:
Type:
Clear condition:
| Bits | Identifier | Type | Value | Description | Clear condition |
|---|---|---|---|---|---|
| 511: 510 | DAT_BUS_WIDTH | S R |
’00’= 1 (default) ‘01’= reserved ‘10’= 4 bit width ‘11’= reserved |
Shows the currently defined databus width that was defined by SET_BUS_WIDTH command |
A |
| 509 | SECURED_MODE | S R | ’0’= Not in the mode ’1’= In Secured Mode |
Card is in Secured Mode of operation (refer to the “SD Security Specification”). |
A |
| 508: 496 | Reserved |
||||
| 495: 480 | SD_CARD_TYPE | S R |
’00xxh’= SD Memory Cards as defined in Physical Spec Ver1.01- 2.00 (’x’= don’t care). The following cards are currently defined: ’0000’= Regular SD RD/WR Card. ’0001’= SD ROM Card |
In the future, the 8 LSBs will be used to define different variations of an SD memory card (each bit will define different SD types). The 8 MSBs will be used to define SD Cards that do not comply with current SD physical layer specification. |
A |
| 479: 448 | SIZE_OF_PROTE CT ED_AREA |
S R | Size of protected area (See below) | (See below) | A |
| 447: 440 | SPEED_CLASS | S R | Speed Class of the card (See below) | (See below) | A |
| 439: 432 | PERFORMANCE_ MOVE |
S R |
Performance of move indicated by 1 [MB/s] step. (See below) |
(See below) | A |
| 431:428 | AU_SIZE | S R |
Size of AU (See below) |
(See below) | A |
| 427:424 | Reserved |
||||
| 423:408 | ERASE_SIZE | S R | Number of AUs to be erased at a time | (See below) | A |
| 407:402 | ERASE_TIMEOUT | S R |
Timeout value for erasing areas specified by UNIT_OF_ERASE_AU |
(See below) | A |
| 401:400 | ERASE_OFFSET | S R | Fixed offset value added to erase time. | (See below) | A |
| 399:312 | Reserved |
||||
| 311:0 | Reserved for Manufacturer |
||||
SIZE_OF_PROTECTED_AREA
Setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows:
Protected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.
SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN.
In the case of a high-capacity card, the capacity of protected area is specified in this field:
Protected area = SIZE_OF_PROTECTED_AREA
SIZE_OF_PROTECTED_AREA is specified by the unit in bytes.
SPEED_CLASS
This 8-bit field indicates the speed class and the value can be calculated by PW/2 (where PW is the write performance).
| SPEED_CLASS | Value definition |
|---|---|
| 00h | Class 0 |
| 01h | Class 2 |
| 02h | Class 4 |
| 03h | Class 6 |
| 04h – FFh | Reserved |
PERFORMANCE_MOVE
This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps. If the card does not move used RUs (recording units), Pm should be considered as infinity. Setting the field to FFh means infinity.
| PERFORMANCE_MOVE | Value definition |
|---|---|
| 00h | Not defined |
| 01h | 1 [MB/sec] |
| 02h | 02h 2 [MB/sec] |
| --------- | --------- |
| FEh | 254 [MB/sec] |
| FFh | Infinity |
AU_SIZE
This 4-bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB.
| AU_SIZE | Value definition |
|---|---|
| 00h | Not defined |
| 01h | 16 KB |
| 02h | 32 KB |
| 03h | 64 KB |
| 04h | 128 KB |
| 05h | 256 KB |
| 06h | 512 KB |
| 07h | 1 MB |
| 08h | 2 MB |
| 09h | 4 MB |
| Ah – Fh | Reserved |
The maximum AU size, which depends on the card capacity, is defined in Table 261. The card can be set to any AU size between RU size and maximum AU size.
| Capacity | 16 MB-64 MB | 128 MB-256 MB | 512 MB | 1 GB-32 GB |
|---|---|---|---|---|
| Maximum AU Size | 512 KB | 1 MB | 2 MB | 4 MB |
ERASE_SIZE
This 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the timeout value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation. If this field is set to 0, the erase timeout calculation is not supported.
| ERASE_SIZE | Value definition |
|---|---|
| 0000h | Erase timeout calculation is not supported. |
| 0001h | 1 AU |
| 0002h | 2 AU |
| 0003h | 3 AU |
| --------- | --------- |
| FFFFh | 65535 AU |
ERASE_TIMEOUT
This 6-bit field indicates TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE.
| ERASE_TIMEOUT | Value definition |
|---|---|
| 00 | Erase timeout calculation is not supported. |
| 01 | 1 [sec] |
| 02 | 2 [sec] |
| 03 | 3 [sec] |
| --------- | --------- |
| 63 | 63 [sec] |
ERASE_OFFSET
This 2-bit field indicates TOFFSET and one of four values can be selected. This field is meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0.
| ERASE_OFFSET | Value definition |
|---|---|
| 0h | 0 [sec] |
| 1h | 1 [sec] |
| 2h | 2 [sec] |
| 3h | 3 [sec] |
SD I/O interrupts
To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin on the SD interface. Pin 8, used as SDMMC_D1 when operating in the 4-
bit SD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is level-sensitive, which means that the interrupt line must be held active (low) until it is either recognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end of the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s internal registers. The interrupt output of all SD I/O cards is active low and the application must provide pull-up resistors externally on all data lines (SDMMC_D[3:0]). The MultiMediaCard/SD module samples the level of pin 8 (SDMMC_D/IRQ) into the interrupt detector only during the interrupt period. At all other times, the MultiMediaCard/SD module ignores this value.
The interrupt period is applicable for both memory and I/O operations. The definition of the interrupt period for operations with single blocks is different from the definition for multiple-block data transfers.
SD I/O suspend and resume
Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus. To share access to the MMC/SD module among multiple devices, SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports suspend/resume, the MMC/SD module can temporarily halt a data transfer operation to one function or memory (suspend) to free the bus for a higher-priority transfer to a different function or memory. After this higher-priority transfer is complete, the original transfer is resumed (restarted) where it left off. Support of suspend/resume is optional on a per-card basis. To perform the suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps:
SD I/O ReadWait
The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple
registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test capability bits in the internal card registers. The timing for ReadWait is based on the interrupt period.
Application-specific and general commands
The SDMMC card host module system is designed to provide a standard interface for a variety of applications types. In this environment, there is a need for specific customer/application features. To implement these features, two types of generic commands are defined in the standard: application-specific commands (ACMD) and general commands (GEN_CMD).
When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an application-specific command. ACMDs have the same structure as regular MultiMediaCard commands and can have the same CMD number. The card recognizes it as ACMD because it appears after APP_CMD (CMD55). When the command immediately following the APP_CMD (CMD55) is not a defined application-specific command, the standard command is used. For example, when the card has a definition for SD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), this is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 immediately following APP_CMD (CMD55) and the card does not have a definition for ACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7.
To use one of the manufacturer-specific ACMDs the SD card Host must perform the following steps:
When an invalid command is sent (neither ACMD nor CMD) it is handled as a standard MultiMediaCard illegal command error.
The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning.
The card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data block size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) is in R1b format.
Command types
Both application-specific and general commands are divided into the four following types:
Command formats
See Table 248 on page 1480 for command formats.
Commands for the MultiMediaCard/SD module
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
| CMD23 | ac |
[31:16] set to 0 [15:0] number of blocks |
R1 | SET_BLOCK_COUNT |
Defines the number of blocks which are going to be transferred in the multiple-block read or write command that follows. |
| CMD24 | adtc | [31:0] data address | R1 | WRITE_BLOCK | Writes a block of the size selected by the SET_BLOCKLEN command. |
| CMD25 | adtc | [31:0] data address | R1 | WRITE_MULTIPLE_BLOCK |
Continuously writes blocks of data until a STOP_TRANSMISSION follows or the requested number of blocks has been received. |
| CMD26 | adtc | [31:0] stuff bits | R1 | PROGRAM_CID |
Programming of the card identification register. This command must be issued only once per card. The card contains hardware to prevent this operation after the first programming. Normally this command is reserved for manufacturer. |
| CMD27 | adtc | [31:0] stuff bits | R1 | PROGRAM_CSD | Programming of the programmable bits of the CSD. |
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
| CMD28 | ac | [31:0] data address | R1b | SET_WRITE_PROT |
If the card has write protection features, this command sets the write protection bit of the addressed group. The properties of write protection are coded in the card- specific data (WP_GRP_SIZE). |
| CMD29 | ac | [31:0] data address | R1b | CLR_WRITE_PROT |
If the card provides write protection features, this command clears the write protection bit of the addressed group. |
| CMD30 | adtc |
[31:0] write protect data address |
R1 | SEND_WRITE_PROT |
If the card provides write protection features, this command asks the card to send the status of the write protection bits. |
| CMD31 | Reserved |
||||
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
|
CMD32 ... CMD34 |
Reserved. These command indexes cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCard. |
||||
| CMD35 | ac | [31:0] data address | R1 | ERASE_GROUP_START |
Sets the address of the first erase group within a range to be selected for erase. |
| CMD36 | ac | [31:0] data address | R1 | ERASE_GROUP_END |
Sets the address of the last erase group within a continuous range to be selected for erase. |
| CMD37 | Reserved. This command index cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCards |
||||
| CMD38 | ac | [31:0] stuff bits | R1 | ERASE | Erases all previously selected write blocks. |
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
| CMD39 | ac |
[31:16] RCA [15:15] register write flag [14:8] register address [7:0] register data |
R4 | FAST_IO |
Used to write and read 8-bit (register) data fields. The command addresses a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the addressed register. This command accesses application-dependent registers that are not defined in the MultiMediaCard standard. |
| CMD40 | bcr | [31:0] stuff bits | R5 | GO_IRQ_STATE | Places the system in the interrupt mode. |
| CMD41 | Reserved |
||||
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
| CMD42 | adtc | [31:0] stuff bits | R1b | LOCK_UNLOCK |
Sets/resets the password or locks/unlocks the card. The size of the data block is set by the SET_BLOCK_LEN command. |
| CMD43 ... CMD54 |
Reserved |
||||
| CMD index | Type | Argument | Response format | Abbreviation | Description |
|---|---|---|---|---|---|
| CMD55 | ac |
[31:16] RCA [15:0] stuff bits |
R1 | APP_CMD |
Indicates to the card that the next command bits is an application specific command rather than a standard command |
| CMD56 | adtc |
[31:1] stuff bits [0]: RD/WR |
- | - |
Used either to transfer a data block to the card or to get a data block from the card for general purpose/application-specific commands. The size of the data block shall be set by the SET_BLOCK_LEN command. |
| CMD57 ... CMD59 |
Reserved. |
||||
| CMD60 ... CMD63 |
Reserved for manufacturer. | ||||
All responses are sent via the SDMMC command line SDMMC_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type.
A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. All responses, except for the R3 response type, are protected by a CRC. Every command code word is terminated by the end bit (always 1).
There are five types of responses. Their formats are defined as follows:
Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits.
| Bit position | Width (bits | Value | Description |
|---|---|---|---|
| 47 | 1 | 0 | Start bit |
| 46 | 1 | 0 | Transmission bit |
| [45:40] | 6 | X | Command index |
| [39:8] | 32 | X | Card status |
| [7:1] | 7 | X | CRC7 |
| 0 | 1 | 1 | End bit |
It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.
Code length = 136 bits. The contents of the CID register are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. The card indicates that an erase is in progress by holding SDMMC_D0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card.
| Bit position | Width (bits | Value | Description |
|---|---|---|---|
| 135 | 1 | 0 | Start bit |
| 134 | 1 | 0 | Transmission bit |
| [133:128] | 6 | ‘111111’ | Command index |
| [127:1] | 127 | X | Card status |
| 0 | 1 | 1 | End bit |
Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1. The level coding is as follows: restricted voltage windows = low, card busy = low.
| Bit position | Width (bits | Value | Description |
|---|---|---|---|
| 47 | 1 | 0 | Start bit |
| 46 | 1 | 0 | Transmission bit |
| [45:40] | 6 | ‘111111’ | Reserved |
| [39:8] | 32 | X | OCR register |
| [7:1] | 7 | ‘1111111’ | Reserved |
| 0 | 1 | 1 | End bit |
Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content.
| Bit position | Width (bits | Value | Description |
|
|---|---|---|---|---|
| 47 | 1 | 0 | Start bit |
|
| 46 | 1 | 0 | Transmission bit |
|
| [45:40] | 6 | ‘100111’ | CMD39 |
|
| [39:8] Argument field |
[31:16] | 16 | X | RCA |
| [15:8] | 8 | X | register address |
|
| [7:0] | 8 | X | read register contents |
|
| [7:1] | 7 | X | CRC7 |
|
| 0 | 1 | 1 | End bit |
|
For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is:
| Bit position | Width (bits | Value | Description |
|
|---|---|---|---|---|
| 47 | 1 | 0 | Start bit |
|
| 46 | 1 | 0 | Transmission bit |
|
| [45:40] | 6 | X | Reserved | |
| [39:8] Argument field |
39 | 16 | X | Card is ready |
| [38:36] | 3 | X | Number of I/O functions |
|
| 35 | 1 | X | Present memory |
|
| [34:32] | 3 | X | Stuff bits |
|
| [31:8] | 24 | X | I/O ORC |
|
| [7:1] | 7 | X | Reserved |
|
| 0 | 1 | 1 | End bit |
|
Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card. Note that an SD memory-only card may respond to a CMD5. The proper response for a memory-only card would be Present memory = 1 and Number of I/O functions = 0. A memory-only card built to meet the SD Memory Card specification version 1.0 would detect the CMD5 as an illegal command and not respond. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4 response.
Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0.
| Bit position | Width (bits | Value | Description |
|
|---|---|---|---|---|
| 47 | 1 | 0 | Start bit |
|
| 46 | 1 | 0 | Transmission bit |
|
| [45:40] | 6 | ‘101000’ | CMD40 |
|
| [39:8] Argument field |
[31:16] | 16 | X | RCA [31:16] of winning card or of the host |
| [15:0] | 16 | X | Not defined. May be used for IRQ data |
|
| [7:1] | 7 | X | CRC7 |
|
| 0 | 1 | 1 | End bit | |
Only for SD I/O. The normal response to CMD3 by a memory device. It is shown in Table 277.
| Bit position | Width (bits) | Value | Description |
|
|---|---|---|---|---|
| 47 | 1 | 0 | Start bit |
|
| 46 | 1 | 0 | Transmission bit |
|
| [45:40] | 6 | ‘101000’ | CMD40 |
|
| [39:8] Argument field |
[31:16] | 16 | X | RCA [31:16] of winning card or of the host |
| [15:0] | 16 | X | Not defined. May be used for IRQ data |
|
| [7:1] | 7 | X | CRC7 |
|
| 0 | 1 | 1 | End bit | |
The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values:
The following features are SD I/O-specific operations:
The SDMMC supports these operations only if the SDMMC_DCTRL[11] bit is set, except for read suspend that does not need specific hardware implementation.
It is possible to start the readwait interval before the first block is received: when the data path is enabled (SDMMC_DCTRL[0] bit set), the SDIO-specific operation is enabled (SDMMC_DCTRL[11] bit set), read wait starts (SDMMC_DCTRL[10] =0 and SDMMC_DCTRL[8] =1) and data direction is from card to SDMMC (SDMMC_DCTRL[1] = 1), the DPSM directly moves from Idle to Readwait. In Readwait the DPSM drives SDMMC_D2 to 0 after 2 SDMMC_CK clock cycles. In this state, when you set the RWSTOP bit (SDMMC_DCTRL[9]), the DPSM remains in Wait for two more SDMMC_CK clock cycles to drive SDMMC_D2 to 1 for one clock cycle (in accordance with SDIO specification). The DPSM then starts waiting again until it receives data from the card. The DPSM will not start a readwait interval while receiving a block even if read wait start is set: the readwait interval will start after the CRC is received. The RWSTOP bit has to be cleared to start a new read wait operation. During the readwait interval, the SDMMC can detect SDIO interrupts on SDMMC_D1.
If the SDIO card does not support the previous read wait method, the SDMMC can perform a read wait by stopping SDMMC_CK (SDMMC_DCTRL is set just like in the method presented in Section 39.6.1, but SDMMC_DCTRL[10] =1): DSPM stops the clock two SDMMC_CK cycles after the end bit of the current received block and starts the clock again after the read wait start bit is set.
As SDMMC_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDMMC can detect SDIO interrupts on SDMMC_D1.
While sending data to the card, the SDMMC can suspend the write operation. the SDMMC_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command. The CPSM analyzes the response and when the ACK is received from the card (suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC token of the current block.
The hardware does not save the number of the remaining block to be sent to complete the suspended operation (resume).
The write operation can be suspended by software, just by disabling the DPSM (SDMMC_DCTRL[0] =0) when the ACK of the suspend command is received from the card. The DPSM enters then the Idle state.
To suspend a read: the DPSM waits in the Wait_r state as the function to be suspended sends a complete packet just before stopping the data transaction. The application continues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically.
SDIO interrupts are detected on the SDMMC_D1 line once the SDMMC_DCTRL[11] bit is set.
When SDIO interrupt is detected, SDMMC_STA[22] (SDIOIT) bit is set. This static bit can be cleared with clear bit SDMMC_ICR[22] (SDIOITC). An interrupt can be generated when SDIOIT status bit is set. Separated interrupt enable SDMMC_MASK[22] bit (SDIOITE) is available to enable and disable interrupt request.
When SD card interrupt occurs (SDMMC_STA[22] bit set), host software follows below steps to handle it.
Steps 2 to 4 can be executed out of the SDIO interrupt service routine.
The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDMMC_CK and freeze SDMMC state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked by SDMMCCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated.
To enable HW flow control, the SDMMC_CLKCR[14] register bit must be set to 1. After reset Flow Control is disabled.
The device communicates to the system via 32-bit-wide control registers accessible via APB2.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PWRCTRL |
|
| rw | rw |
||||||||||||||||||||||||||||||
| Bits 31:2 | Reserved, must be kept at reset value. |
[1:0] PWRCTRL: Power supply control bits.
These bits are used to define the current functional state of the card clock:
00: Power-off: the clock to card is stopped.
01: Reserved
10: Reserved power-up
11: Power-on: the card is clocked.
Note: At least seven PCLK2 clock periods are needed between two write accesses to this register.
Note: After a data write, data cannot be written to this register for three SDMMCCLK clock periods
plus two PCLK2 clock periods.
Address offset: 0x04
Reset value: 0x0000 0000
The SDMMC_CLKCR register controls the SDMMC_CK output clock.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | HWFC _EN |
NEGE DGE |
WID BUS |
BYPAS S |
PWRS AV |
CLKEN | CLKDIV |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bit 14 | HWFC_EN: HW Flow Control enable |
|
0b: HW Flow Control is disabled |
|
| Bit 13 | NEGEDGE: SDMMC_CK dephasing selection bit |
|
0b: Command and Data changed on the SDMMCCLK falling edge succeeding the rising edge of SDMMC_CK. (SDMMC_CK rising edge occurs on SDMMCCLK rising edge). |
|
| Bits 12:11 | WIDBUS: Wide bus mode enable bit |
|
00: Default bus mode: SDMMC_D0 used |
|
| Bit 10 | BYPASS: Clock divider bypass enable bit |
|
0: Disable bypass: SDMMCCLK is divided according to the CLKDIV value before driving the SDMMC_CK output signal. |
|
| Bit 9 | PWRSAV: Power saving configuration bit |
|
For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: |
|
| Bit 8 | CLKEN: Clock enable bit |
|
0: SDMMC_CK is disabled |
|
| Bits 7:0 | CLKDIV: Clock divide factor |
|
This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [CLKDIV + 2]. |
Note: 1 While the SD/SDIO card or MultiMediaCard is in identification mode, the SDMMC_CK
frequency must be less than 400 kHz.
2 The clock frequency can be changed to the maximum card bus frequency when relative
card addresses are assigned to all cards.
3 After a data write, data cannot be written to this register for three SDMMCCLK clock periods
plus two PCLK2 clock periods. SDMMC_CK can also be stopped during the read wait
interval for SD I/O cards: in this case the SDMMC_CLKCR register does not control
SDMMC_CK.
Address offset: 0x08
Reset value: 0x0000 0000
The SDMMC_ARG register contains a 32-bit command argument, which is sent to a card as part of a command message.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CMDARG[31:16] |
CMDARG[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | CMDARG: Command argument |
|
Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. |
Address offset: 0x0C
Reset value: 0x0000 0000
The SDMMC_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | SDIO Suspend |
CPSM EN |
WAIT PEND |
WAIT INT |
WAITRESP | CMDINDEX |
||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bit 11 | SDIOSuspend: SD I/O suspend command |
|
If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card). |
|
| Bit 10 | CPSMEN: Command path state machine (CPSM) Enable bit |
|
If this bit is set, the CPSM is enabled. |
|
| Bit 9 | WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal). |
|
If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command. This feature is available only with Stream data transfer mode SDMMC_DCTRL[2] = 1. |
|
| Bit 8 | WAITINT: CPSM waits for interrupt request |
|
If this bit is set, the CPSM disables command timeout and waits for an interrupt request. |
|
| Bits 7:6 | WAITRESP: Wait for response bits |
|
They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. |
|
| Bits 5:0 | CMDINDEX: Command index |
|
The command index is sent to the card as part of a command message. |
Note: 1 After a data write, data cannot be written to this register for three SDMMCCLK clock periods
plus two PCLK2 clock periods.
2 MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long
responses,136 bits long. SD card and SD I/O card can send only short responses, the
argument can vary according to the type of response: the software will distinguish the type
of response according to the sent command.
Address offset: 0x10
Reset value: 0x0000 0000
The SDMMC_RESPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RESPCMD |
|||||
| r | r | r | r | r | r |
||||||||||||||||||||||||||
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bits 5:0 | RESPCMD: Response command index |
|
Read-only bit field. Contains the command index of the last command response received. |
Address offset: (0x10 + (4 × x)); x = 1..4
Reset value: 0x0000 0000
The SDMMC_RESP1/2/3/4 registers contain the status of a card, which is part of the received response.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CARDSTATUSx[31:16] |
CARDSTATUSx[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | CARDSTATUSx: see Table 278. |
The Card Status size is 32 or 127 bits, depending on the response type.
| Register | Short response | Long response |
|---|---|---|
| SDMMC_RESP1 | Card Status[31:0] | Card Status [127:96] |
| SDMMC_RESP2 | Unused | Card Status [95:64] |
| SDMMC_RESP3 | Unused | Card Status [63:32] |
| SDMMC_RESP4 | Unused | Card Status [31:1]0b |
The most significant bit of the card status is received first. The SDMMC_RESP4 register LSB is always 0b.
Address offset: 0x24
Reset value: 0x0000 0000
The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods.
A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATATIME[31:16] |
DATATIME[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DATATIME: Data timeout period |
|
Data timeout period expressed in card bus clock periods. |
Note: A data transfer must be written to the data timer register and the data length register before
being written to the data control register.
Address offset: 0x28
Reset value: 0x0000 0000
The SDMMC_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATALENGTH[24:16] |
DATALENGTH[15:0] |
|||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | DATALENGTH: Data length value |
|
Number of data bytes to be transferred. |
Note: For a block data transfer, the value in the data length register must be a multiple of the block
size (see SDMMC_DCTRL). Before being written to the data control register a timeout must
be written to the data timer register and the data length register.
In case of IO_RW_EXTENDED (CMD53):
- If the Stream or SDIO multibyte data transfer is selected the value in the data length
register must be between 1 and 512.
- If the Block data transfer is selected the value in the data length register must be between
1*Data block size and 512*Data block size.
Address offset: 0x2C
Reset value: 0x0000 0000
The SDMMC_DCTRL register control the data path state machine (DPSM).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | SDIO EN |
RW MOD |
RW STOP |
RW START |
DBLOCKSIZE | DMA EN |
DT MODE |
DTDIR | DTEN |
|||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bit 11 | SDIOEN: SD I/O enable functions |
|
If this bit is set, the DPSM performs an SD I/O-card-specific operation. |
|
| Bit 10 | RWMOD: Read wait mode |
|
0: Read Wait control stopping SDMMC_D2 |
|
| Bit 9 | RWSTOP: Read wait stop |
|
0: Read wait in progress if RWSTART bit is set |
|
| Bit 8 | RWSTART: Read wait start |
|
If this bit is set, read wait operation starts. |
|
| Bits 7:4 | DBLOCKSIZE: Data block size |
|
Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 20 = 1 byte |
|
| Bit 3 | DMAEN: DMA enable bit |
|
0: DMA disabled. |
|
| Bit 2 | DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. |
|
0: Block data transfer |
|
| Bit 1 | DTDIR: Data transfer direction selection |
|
0: From controller to card. |
[0] DTEN: Data transfer enabled bit
Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data transfer but the SDMMC_DCTRL must be updated to enable a new data transfer
Note: After a data write, data cannot be written to this register for three SDMMCCLK clock periods
plus two PCLK2 clock periods.
The meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When
SDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when
SDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer.
Address offset: 0x30
Reset value: 0x0000 0000
The SDMMC_DCOUNT register loads the value from the data length register (see SDMMC_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and the data status end flag, DATAEND, is set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATACOUNT[24:16] |
DATACOUNT[15:0] |
|||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
|||||||
| Bits 31:25 | Reserved, must be kept at reset value. |
| Bits 24:0 | DATACOUNT: Data count value |
|
When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no effect. |
Note: This register should be read only when the data transfer is complete.
Address offset: 0x34
Reset value: 0x0000 0000
The SDMMC_STA register is a read-only register. It contains two types of flag:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOIT | RXD AVL |
TXD AVL |
RX FIFOE |
TX FIFOE |
RX FIFOF |
TX FIFOF |
RX FIFO HF |
TX FIFO HE |
RXACT | TXACT | CMD ACT |
DBCK END |
Res. | DATA END |
CMDS ENT |
CMDR END |
RX OVERR |
TXUND ERR |
DTIME OUT |
CTIME OUT |
DCRC FAIL |
CCRC FAIL |
| r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||
| Bits 31:23 | Reserved, must be kept at reset value. |
| Bit 22 | SDIOIT: SDIO interrupt received |
| Bit 21 | RXDAVL: Data available in receive FIFO |
| Bit 20 | TXDAVL: Data available in transmit FIFO |
| Bit 19 | RXFIFOE: Receive FIFO empty |
| Bit 18 | TXFIFOE: Transmit FIFO empty |
|
When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. |
|
| Bit 17 | RXFIFOF: Receive FIFO full |
|
When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. |
|
| Bit 16 | TXFIFOF: Transmit FIFO full |
| Bit 15 | RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO |
| Bit 14 | TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO |
| Bit 13 | RXACT: Data receive in progress |
| Bit 12 | TXACT: Data transmit in progress |
| Bit 11 | CMDACT: Command transfer in progress |
| Bit 10 | DBCKEND: Data block sent/received (CRC check passed) |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| Bit 7 | CMDSENT: Command sent (no response required) |
| Bit 6 | CMDREND: Command response received (CRC check passed) |
| Bit 5 | RXOVERR: Received FIFO overrun error |
|
If DMA is used to read SDMMC FIFO (DMAEN bit is set in SDMMC_DCTRL register), |
|
| Bit 4 | TXUNDERR: Transmit FIFO underrun error |
|
If DMA is used to fill SDMMC FIFO (DMAEN bit is set in SDMMC_DCTRL register), |
|
| Bit 3 | DTIMEOUT: Data timeout |
| Bit 2 | CTIMEOUT: Command response timeout |
|
The Command TimeOut period has a fixed value of 64 SDMMC_CK clock periods. |
|
| Bit 1 | DCRCFAIL: Data block sent/received (CRC check failed) |
| Bit 0 | CCRCFAIL: Command response received (CRC check failed) |
Address offset: 0x38
Reset value: 0x0000 0000
The SDMMC_ICR register is a write-only register. Writing a bit with 1b clears the corresponding bit in the SDMMC_STA Status register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIO ITC |
Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | DBCK ENDC |
Res. | DATA ENDC |
CMD SENTC |
CMD REND C |
RX OVERR C |
TX UNDERR C |
DTIME OUTC |
CTIME OUTC |
DCRC FAILC |
CCRC FAILC |
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:23 | Reserved, must be kept at reset value. |
| Bit 22 | SDIOITC: SDIOIT flag clear bit |
|
Set by software to clear the SDIOIT flag. |
|
| Bits 21:11 | Reserved, must be kept at reset value. |
| Bit 10 | DBCKENDC: DBCKEND flag clear bit |
|
Set by software to clear the DBCKEND flag. |
|
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | DATAENDC: DATAEND flag clear bit |
|
Set by software to clear the DATAEND flag. |
|
| Bit 7 | CMDSENTC: CMDSENT flag clear bit |
|
Set by software to clear the CMDSENT flag. |
|
| Bit 6 | CMDRENDC: CMDREND flag clear bit |
|
Set by software to clear the CMDREND flag. |
|
| Bit 5 | RXOVERRC: RXOVERR flag clear bit |
|
Set by software to clear the RXOVERR flag. |
|
| Bit 4 | TXUNDERRC: TXUNDERR flag clear bit |
|
Set by software to clear TXUNDERR flag. |
|
| Bit 3 | DTIMEOUTC: DTIMEOUT flag clear bit |
|
Set by software to clear the DTIMEOUT flag. |
|
| Bit 2 | CTIMEOUTC: CTIMEOUT flag clear bit |
|
Set by software to clear the CTIMEOUT flag. |
|
| Bit 1 | DCRCFAILC: DCRCFAIL flag clear bit |
|
Set by software to clear the DCRCFAIL flag. |
|
| Bit 0 | CCRCFAILC: CCRCFAIL flag clear bit |
|
Set by software to clear the CCRCFAIL flag. |
Address offset: 0x3C
Reset value: 0x0000 0000
The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIO ITIE |
RXD AVLIE |
TXD AVLIE |
RX FIFO EIE |
TX FIFO EIE |
RX FIFO FIE |
TX FIFO FIE |
RX FIFO HFIE |
TX FIFO HEIE |
RX ACTIE |
TX ACTIE |
CMD ACTIE |
DBCK ENDIE |
Res. | DATA ENDIE |
CMD SENT IE |
CMD REND IE |
RX OVERR IE |
TX UNDERR IE |
DTIME OUTIE |
CTIME OUTIE |
DCRC FAILIE |
CCRC FAILIE |
| rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:23 | Reserved, must be kept at reset value. |
| Bit 22 | SDIOITIE: SDIO mode interrupt received interrupt enable |
|
Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. |
|
| Bit 21 | RXDAVLIE: Data available in Rx FIFO interrupt enable |
|
Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Rx FIFO. |
|
| Bit 20 | TXDAVLIE: Data available in Tx FIFO interrupt enable |
|
Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO. |
|
| Bit 19 | RXFIFOEIE: Rx FIFO empty interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty. |
|
| Bit 18 | TXFIFOEIE: Tx FIFO empty interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. |
|
| Bit 17 | RXFIFOFIE: Rx FIFO full interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. |
|
| Bit 16 | TXFIFOFIE: Tx FIFO full interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. |
|
| Bit 15 | RXFIFOHFIE: Rx FIFO half full interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. |
|
| Bit 14 | TXFIFOHEIE: Tx FIFO half empty interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. |
|
| Bit 13 | RXACTIE: Data receive acting interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting). |
|
| Bit 12 | TXACTIE: Data transmit acting interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting). |
|
| Bit 11 | CMDACTIE: Command acting interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting). |
|
| Bit 10 | DBCKENDIE: Data block end interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data block end. |
|
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | DATAENDIE: Data end interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data end. |
|
| Bit 7 | CMDSENTIE: Command sent interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by sending command. |
|
| Bit 6 | CMDRENDIE: Command response received interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by receiving command response. |
|
| Bit 5 | RXOVERRIE: Rx FIFO overrun error interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. |
|
| Bit 4 | TXUNDERRIE: Tx FIFO underrun error interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. |
|
| Bit 3 | DTIMEOUTIE: Data timeout interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data timeout. |
|
| Bit 2 | CTIMEOUTIE: Command timeout interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by command timeout. |
|
| Bit 1 | DCRCFAILIE: Data CRC fail interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by data CRC failure. |
|
| Bit 0 | CCRCFAILIE: Command CRC fail interrupt enable |
|
Set and cleared by software to enable/disable interrupt caused by command CRC failure. |
Address offset: 0x48
Reset value: 0x0000 0000
The SDMMC_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDMMC_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDMMC_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FIFOCOUNT[23:16] |
FIFOCOUNT[15:0] |
||||||||||||||||||||||
| r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:0 | FIFOCOUNT: Remaining number of words to be written to or read from the FIFO. |
Address offset: 0x80
Reset value: 0x0000 0000
The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIF0Data[31:16] |
FIF0Data[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
bits 31:0 FIFOData: Receive and transmit FIFO data
The FIFO data occupies 32 entries of 32-bit words, from address:
SDMMC base + 0x080 to SDMMC base + 0xFC.
The following table summarizes the SDMMC registers.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
SDMMC_ POWER |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PWRCTRL | |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x04 |
SDMMC_ CLKCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HWFC_EN | NEGEDGE | WIDBUS | BYPASS | PWRSAV | CLKEN | CLKDIV | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x08 |
SDMMC_ARG | CMDARG |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C |
SDMMC_CMD
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOSuspend | CPSMEN | WAITPEND | WAITINT | WAITRESP | CMDINDEX | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x10 |
SDMMC_ RESPCMD |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RESPCMD |
|||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x14 |
SDMMC_ RESP1 |
CARDSTATUS1 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x18 |
SDMMC_ RESP2 |
CARDSTATUS2 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1C |
SDMMC_ RESP3 |
CARDSTATUS3 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x20 |
SDMMC_ RESP4 |
CARDSTATUS4 |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x24 |
SDMMC_ DTIMER |
DATATIME |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x28 |
SDMMC_ DLEN |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATALENGTH |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x2C |
SDMMC_ DCTRL |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOEN | RWMOD | RWSTOP | RWSTART | DBLOCKSIZE | DMAEN | DTMODE | DTDIR | DTEN | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||
| 0x30 |
SDMMC_ DCOUNT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | DATACOUNT |
||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x34 |
SDMMC_STA
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOIT | RXDAVL | TXDAVL | RXFIFOE | TXFIFOE | RXFIFOF | TXFIFOF | RXFIFOHF | TXFIFOHE | RXACT | TXACT | CMDACT | DBCKEND | Res. | DATAEND | CMDSENT | CMDREND | RXOVERR | TXUNDERR | DTIMEOUT | CTIMEOUT | DCRCFAIL | CCRCFAIL |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x38 |
SDMMC_ICR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOITC | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBCKENDC | Res. | DATAENDC | CMDSENTC | CMDRENDC | RXOVERRC | TXUNDERRC | DTIMEOUTC | CTIMEOUTC | DCRCFAILC | CCRCFAILC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x3C |
SDMMC_ MASK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SDIOITIE | RXDAVLIE | TXDAVLIE | RXFIFOEIE | TXFIFOEIE | RXFIFOFIE | TXFIFOFIE | RXFIFOHFIE | TXFIFOHEIE | RXACTIE | TXACTIE | CMDACTIE | DBCKENDIE | Res. | DATAENDIE | CMDSENTIE | CMDRENDIE | RXOVERRIE | TXUNDERRIE | DTIMEOUTIE | CTIMEOUTIE | DCRCFAILIE | CCRCFAILIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x48 |
SDMMC_ FIFOCNT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FIFOCOUNT |
|||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0x80 |
SDMMC_FIFO | FIF0Data |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages.
For safety-critical applications, the CAN controller provides all hardware functions for supporting the CAN Time Triggered Communication option.
Transmission
Reception
Time-triggered communication option
Management
Dual CAN peripheral configuration
Single CAN peripheral configuration:
See Table 280.
| CAN features | CAN1 | CAN2 | CAN3 |
|---|---|---|---|
| SRAM size | 512-byte shared between the two bxCAN | 512-byte |
|
| Filter banks | 26 filter banks shared between CAN1 and CAN2 | 14 fiter banks | |
In today CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (to be handled by each node) has significantly increased. In addition to the application messages, Network Management and Diagnostic messages have been introduced.
Furthermore, application tasks require more CPU time, therefore real-time constraints caused by message reception have to be reduced.
The standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an efficient interface to the CAN controller.
| (omitted) |
The bxCAN module handles the transmission and the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware.
The application uses these registers to:
Three transmit mailboxes are provided to the software for setting up messages. The transmission Scheduler decides which mailbox has to be transmitted first.
The bxCAN provides up to 28 scalable/configurable identifier filter banks in dual CAN configuration or up to 14 scalable/configurable identifier filter banks in single CAN configuration, for selecting the incoming messages, that the software needs and discarding the others.
Receive FIFO
Two receive FIFOs are used by hardware to store the incoming messages. Three complete messages can be stored in each FIFO. The FIFOs are managed completely by hardware.
| (omitted) |
| (omitted) |
bxCAN has three main operating modes: initialization, normal and Sleep. After a hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pull-up is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode by setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been entered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and the internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal
mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX.
The software initialization can be done while the hardware is in Initialization mode. To enter this mode the software sets the INRQ bit in the CAN_MCR register and waits until the hardware has confirmed the request by setting the INAK bit in the CAN_MSR register.
To leave Initialization mode, the software clears the INQR bit. bxCAN has left Initialization mode once the INAK bit has been cleared by hardware.
While in Initialization Mode, all message transfers to and from the CAN bus are stopped and the status of the CAN bus output CANTX is recessive (high).
Entering Initialization Mode does not change any of the configuration registers.
To initialize the CAN Controller, software has to set up the Bit Timing (CAN_BTR) and CAN options (CAN_MCR) registers.
To initialize the registers associated with the CAN filter banks (mode, scale, FIFO assignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter initialization also can be done outside the initialization mode.
Note: When FINIT=1, CAN reception is deactivated.
The filter values also can be modified by deactivating the associated filter activation bits (in
the CAN_FA1R register).
If a filter bank is not used, it is recommended to leave it non active (leave the corresponding
FACT bit cleared).
Once the initialization is complete, the software must request the hardware to enter Normal mode to be able to synchronize on the CAN bus and start reception and transmission.
The request to enter Normal mode is issued by clearing the INRQ bit in the CAN_MCR register. The bxCAN enters Normal mode and is ready to take part in bus activities when it has synchronized with the data transfer on the CAN bus. This is done by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle state). The switch to Normal mode is confirmed by the hardware by clearing the INAK bit in the CAN_MSR register.
The initialization of the filter values is independent from Initialization Mode but must be done while the filter is not active (corresponding FACTx bit cleared). The filter scale and mode configuration must be configured before entering Normal Mode.
To reduce power consumption, bxCAN has a low-power mode called Sleep mode. This mode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In this mode, the bxCAN clock is stopped, however software can still access the bxCAN mailboxes.
If software requests entry to initialization mode by setting the INRQ bit while bxCAN is in Sleep mode, it must also clear the SLEEP bit.
bxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on detection of CAN bus activity.
On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode.
Note: If the wakeup interrupt is enabled (WKUIE bit set in CAN_IER register) a wakeup interrupt
will be generated on detection of CAN bus activity, even if the bxCAN automatically
performs the wakeup sequence.
After the SLEEP bit has been cleared, Sleep mode is exited once bxCAN has synchronized with the CAN bus, refer to Figure 495: bxCAN operating modes. The Sleep mode is exited once the SLAK bit has been cleared by hardware.
| (omitted) |
Test mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits must be configured while bxCAN is in Initialization mode. Once test mode has been selected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode.
The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register.
In Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot start a transmission. If the bxCAN has to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant bit, although the CAN bus may remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames).
| (omitted) |
The bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR register. In Loop Back Mode, the bxCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a Receive mailbox.
| (omitted) |
This mode is provided for self-test functions. To be independent of external events, the CAN Core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal feedback from its Tx output to its Rx input. The actual value of the CANRX input pin is disregarded by the bxCAN. The transmitted messages can be monitored on the CANTX pin.
It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and SILM bits in the CAN_BTR register. This mode can be used for a “Hot Selftest”, meaning the bxCAN can be tested like in Loop Back mode but without affecting a running CAN system connected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected from the bxCAN and the CANTX pin is held recessive.
| (omitted) |
When the microcontroller enters the debug mode (Cortex®-M7 core halted), the bxCAN continues to work normally or stops, depending on:
In order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (DLC) and the data before requesting the transmission by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left empty state, the software no longer has write access to the mailbox registers. Immediately after the TXRQ bit has been set, the mailbox enters pending state and waits to become the highest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest priority it will be scheduled for transmission. The transmission of the message of the scheduled mailbox will start (enter transmit state) when the CAN bus becomes idle. Once the mailbox has been successfully transmitted, it will become empty again. The hardware indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR register.
If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.
Transmit priority
By identifier
When more than one transmit mailbox is pending, the transmission order is given by the identifier of the message stored in the mailbox. The message with the lowest identifier value has the highest priority according to the arbitration of the CAN protocol. If the identifier values are equal, the lower mailbox number will be scheduled first.
By transmit request order
The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order.
This mode is very useful for segmented transmission.
Abort
A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register. In pending or scheduled state, the mailbox is aborted immediately. An abort request while the mailbox is in transmit state can have two results. If the mailbox is transmitted successfully the mailbox becomes empty with the TXOK bit set in the CAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the transmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox will become empty again at least at the end of the current transmission.
Non automatic retransmission mode
This mode has been implemented in order to fulfill the requirement of the Time Triggered Communication option of the CAN standard. To configure the hardware in this mode the NART bit in the CAN_MCR register must be set.
In this mode, each transmission is started only once. If the first attempt fails, due to an arbitration loss or an error, the hardware will not automatically restart the message transmission.
At the end of the first transmission attempt, the hardware considers the request as completed and sets the RQCP bit in the CAN_TSR register. The result of the transmission is indicated in the CAN_TSR register by the TXOK, ALST and TERR bits.
| (omitted) |
In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 40.7.7: Bit timing). The internal counter is captured on the sample point of the Start Of Frame bit in both reception and transmission.
For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to the CAN protocol (no error until the last but one bit of the EOF field) and It passed through the identifier filtering successfully, see Section 40.7.4: Identifier filtering.
| (omitted) |
FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register. The FIFO becomes empty again. If a new valid message has been received in the meantime, the FIFO stays in pending_1 state and the new message is available in the output mailbox.
If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message. Otherwise the next valid message received will cause a loss of message.
Refer also to Section 40.7.5: Message storage
Overrun
Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. The hardware signals the overrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost depends on the configuration of the FIFO:
Reception related interrupts
Once a message has been stored in the FIFO, the FMP[1:0] bits are updated and an interrupt request is generated if the FMPIE bit in the CAN_IER register is set.
When the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CAN_RFR register is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set.
On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in the CAN_IER register is set.
In the CAN protocol the identifier of a message is not associated with the address of a node but related to the content of the message. Consequently a transmitter broadcasts its message to all receivers. On message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. If the message is needed, it is copied into the SRAM. If not, the message must be discarded without intervention by the software.
To fulfill this requirement in dual CAN configuration, bxCAN Controller provides 28 configurable and scalable filter banks (27-0) to the application. In single CAN configuration bxCAN Controller provides 14 configurable and scalable filter banks (13-0) to the application in order to receive only the messages the software needs.
This hardware filtering saves CPU resources which would be otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1.
Scalable width
To optimize and adapt the filters to the application needs, each filter bank can be scaled independently. Depending on the filter scale a filter bank provides:
Refer to Figure 501.
Furthermore, the filters can be configured in mask mode or in identifier list mode.
Mask mode
In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”.
Identifier list mode
In identifier list mode, the mask registers are used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers. All bits of the incoming identifier must match the bits specified in the filter registers.
Filter bank scale and mode configuration
The filter banks are configured by means of the corresponding CAN_FMR register. To configure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR register. The filter scale is configured by means of the corresponding FSCx bit in the CAN_FS1R register, refer to Figure 501. The identifier list or identifier mask mode for the corresponding Mask/Identifier registers is configured by means of the FBMx bits in the CAN_FMR register.
To filter a group of identifiers, configure the Mask/Identifier registers in mask mode.
To select single identifiers, configure the Mask/Identifier registers in identifier list mode.
Filters not used by the application should be left deactivated.
Each filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum dependent on the mode and the scale of each of the filter banks.
Concerning the filter configuration, refer to Figure 501.
| (omitted) |
Filter match index
Once a message has been received in the FIFO it is available to the application. Typically, application data is copied into SRAM locations. To copy the data to the right location the application has to identify the data by means of the identifier. To avoid this, and to ease the access to the SRAM locations, the CAN controller provides a Filter Match Index.
This index is stored in the mailbox together with the message according to the filter priority rules. Thus each received message has its associated filter match index.
The Filter Match index can be used in two ways:
For non masked filters, the software no longer has to compare the identifier.
If the filter is masked the software reduces the comparison to the masked bits only.
The index value of the filter number does not take into account the activation state of the filter banks. In addition, two independent numbering schemes are used, one for each FIFO. Refer to Figure 502 for an example.
| (omitted) |
Filter priority rules
Depending on the filter combination it may occur that an identifier passes successfully through several filters. In this case the filter match value stored in the receive mailbox is chosen according to the following priority rules:
| (omitted) |
The example above shows the filtering principle of the bxCAN. On reception of a message, the identifier is compared first with the filters configured in identifier list mode. If there is a match, the message is stored in the associated FIFO and the index of the matching filter is stored in the Filter Match Index. As shown in the example, the identifier matches with Identifier #2 thus the message content and FMI 2 is stored in the FIFO.
If there is no match, the incoming identifier is then compared with the filters configured in mask mode.
If the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without disturbing the software.
The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes. A mailbox contains all information related to a message; identifier, data, control, status and time stamp information.
Transmit mailbox
The software sets up the message to be transmitted in an empty transmit mailbox. The status of the transmission is indicated by hardware in the CAN_TSR register.
| Offset to transmit mailbox base address | Register name |
|---|---|
| 0 | CAN_TIxR |
| 4 | CAN_TDTxR |
| 8 | CAN_TDLxR |
| 12 | CAN_TDHxR |
Receive mailbox
When a message has been received, it is available to the software in the FIFO output mailbox. Once the software has handled the message (e.g. read it) the software must release the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to make the next incoming message available. The filter match index is stored in the MFMI field of the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] field of CAN_RDTxR.
| Offset to receive mailbox base address (bytes) | Register name |
|---|---|
| 0 | CAN_RIxR |
| 4 | CAN_RDTxR |
| 8 | CAN_RDLxR |
| 12 | CAN_RDHxR |
| (omitted) |
The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition. For detailed information about TEC and REC management, refer to the CAN standard.
Both of them may be read by software to determine the stability of the network. Furthermore, the CAN hardware provides detailed information on the current error status in CAN_ESR register. By means of the CAN_IER register (ERRIE bit, etc.), the software can configure the interrupt generation on error detection in a very flexible way.
Bus-Off recovery
The Bus-Off state is reached when TEC is greater than 255, this state is indicated by BOFF bit in CAN_ESR register. In Bus-Off state, the bxCAN is no longer able to transmit and receive messages.
Depending on the ABOM bit in the CAN_MCR register bxCAN will recover from Bus-Off (become error active again) either automatically or on software request. But in both cases the bxCAN has to wait at least for the recovery sequence specified in the CAN standard (128 occurrences of 11 consecutive recessive bits monitored on CANRX).
If ABOM is set, the bxCAN will start the recovering sequence automatically after it has entered Bus-Off state.
If ABOM is cleared, the software must initiate the recovering sequence by requesting bxCAN to enter and to leave initialization mode.
Note: In initialization mode, bxCAN does not monitor the CANRX signal, therefore it cannot
complete the recovery sequence. To recover, bxCAN must be in normal mode.
The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on the following edges.
Its operation may be explained simply by splitting nominal bit time into three segments as follows:
The resynchronization Jump Width (SJW) defines an upper bound to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta.
A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit.
If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by up to SJW so that the transmit point is moved earlier.
As a safeguard against programming errors, the configuration of the Bit Timing Register (CAN_BTR) is only possible while the device is in Standby mode.
Note: For a detailed description of the CAN bit timing and resynchronization mechanism, refer to
the ISO 11898 standard.
| (omitted) |
| (omitted) |
Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER).
| (omitted) |
The peripheral registers have to be accessed by words (32 bits).
Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network. Therefore the CAN_BTR register can be modified by software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network level, it can severely disturb the application. A transmit mailbox can be only modified by software while it is in empty state, refer to Figure 499: Transmit mailbox states.
The filter values can be modified either deactivating the associated filter banks or by setting the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
CAN master control register (CAN_MCR)
Address offset: 0x00
Reset value: 0x0001 0002
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBF |
RESET | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TTCM | ABOM | AWUM | NART | RFLM | TXFP | SLEEP | INRQ |
| rw |
rs | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | DBF: Debug freeze |
|
0: CAN working during debug |
|
| Bit 15 | RESET: bxCAN software master reset |
|
0: Normal operation. |
|
| Bits 14:8 | Reserved, must be kept at reset value. |
| Bit 7 | TTCM: Time triggered communication mode |
|
0: Time Triggered Communication mode disabled.
For more information on Time Triggered Communication mode, refer to Section 40.7.2:
|
|
| Bit 6 | ABOM: Automatic bus-off management |
|
This bit controls the behavior of the CAN hardware on leaving the Bus-Off state. 0: The Bus-Off state is left on software request, once 128 occurrences of 11 recessive bits have been monitored and the software has first set and cleared the INRQ bit of the CAN_MCR register. 1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11 recessive bits have been monitored. |
|
| Bit 5 | AWUM: Automatic wakeup mode |
|
This bit controls the behavior of the CAN hardware on message reception during Sleep mode. 0: The Sleep mode is left on software request by clearing the SLEEP bit of the CAN_MCR register. |
|
| Bit 4 | NART: No automatic retransmission |
|
0: The CAN hardware will automatically retransmit the message until it has been successfully transmitted according to the CAN standard. |
|
| Bit 3 | RFLM: Receive FIFO locked mode |
|
0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming message will overwrite the previous one. |
|
| Bit 2 | TXFP: Transmit FIFO priority |
|
This bit controls the transmission order when several mailboxes are pending at the same time. |
|
| Bit 1 | SLEEP: Sleep mode request |
|
This bit is set by software to request the CAN hardware to enter the Sleep mode. Sleep mode will be entered as soon as the current CAN activity (transmission or reception of a CAN frame) has been completed. |
|
| Bit 0 | INRQ: Initialization request |
|
The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception. Hardware signals this event by clearing the INAK bit in the CAN_MSR register. |
CAN master status register (CAN_MSR)
Address offset: 0x04
Reset value: 0x0000 0C02
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | RX | SAMP | RXM | TXM | Res. | Res. | Res. | SLAKI | WKUI | ERRI | SLAK | INAK |
| r | r | r | r | rc_w1 | rc_w1 | rc_w1 | r | r |
| Bits 31:12 | Reserved, must be kept at reset value. |
| Bit 11 | RX: CAN Rx signal |
|
Monitors the actual value of the CAN_RX Pin. |
|
| Bit 10 | SAMP: Last sample point |
|
The value of RX on the last sample point (current received bit value). |
|
| Bit 9 | RXM: Receive mode |
|
The CAN hardware is currently receiver. |
|
| Bit 8 | TXM: Transmit mode |
|
The CAN hardware is currently transmitter. |
|
| Bits 7:5 | Reserved, must be kept at reset value. |
| Bit 4 | SLAKI: Sleep acknowledge interrupt |
|
When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep Mode. When set, this bit generates a status change interrupt if the SLKIE bit in the CAN_IER register is set. When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be |
|
| Bit 3 | WKUI: Wakeup interrupt |
|
This bit is set by hardware to signal that a SOF bit has been detected while the CAN hardware was in Sleep mode. Setting this bit generates a status change interrupt if the WKUIE bit in the CAN_IER register is set. |
|
| Bit 2 | ERRI: Error interrupt |
|
This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set. |
|
| Bit 1 | SLAK: Sleep acknowledge |
|
This bit is set by hardware and indicates to the software that the CAN hardware is now in Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP bit in CAN_MCR register). The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR |
|
| Bit 0 | INAK: Initialization acknowledge |
|
This bit is set by hardware and indicates to the software that the CAN hardware is now in initialization mode. This bit acknowledges the initialization request from the software (set INRQ bit in CAN_MCR register). |
CAN transmit status register (CAN_TSR)
Address offset: 0x08
Reset value: 0x1C00 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOW2 | LOW1 | LOW0 | TME2 | TME1 | TME0 | CODE[1:0] | ABRQ2 | Res. | Res. | Res. | TERR2 | ALST2 | TXOK2 | RQCP2 |
ABRQ1 | Res. | Res. | Res. | TERR1 | ALST1 | TXOK1 | RQCP1 | ABRQ0 | Res. | Res. | Res. | TERR0 | ALST0 | TXOK0 | RQCP0 |
|
| r | r | r | r | r | r | r | r | rs | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rs | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rs | rc_w1 | rc_w1 | rc_w1 | rc_w1 | |||||||||
| Bit 31 | LOW2: Lowest priority flag for mailbox 2 |
|
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. |
|
| Bit 30 | LOW1: Lowest priority flag for mailbox 1 |
|
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. |
|
| Bit 29 | LOW0: Lowest priority flag for mailbox 0 |
|
This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority.
The LOW[2:0] bits are set to zero when only one mailbox is pending.
|
|
| Bit 28 | TME2: Transmit mailbox 2 empty |
|
This bit is set by hardware when no transmit request is pending for mailbox 2. |
|
| Bit 27 | TME1: Transmit mailbox 1 empty |
|
This bit is set by hardware when no transmit request is pending for mailbox 1. |
|
| Bit 26 | TME0: Transmit mailbox 0 empty |
|
This bit is set by hardware when no transmit request is pending for mailbox 0. |
|
| Bits 25:24 | CODE[1:0]: Mailbox code |
|
In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. |
|
| Bit 23 | ABRQ2: Abort request for mailbox 2 |
|
Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. |
|
| Bits 22:20 | Reserved, must be kept at reset value. |
| Bit 19 | TERR2: Transmission error of mailbox 2 |
|
This bit is set when the previous TX failed due to an error. |
|
| Bit 18 | ALST2: Arbitration lost for mailbox 2 |
|
This bit is set when the previous TX failed due to an arbitration lost. |
|
| Bit 17 | TXOK2: Transmission OK of mailbox 2 |
|
The hardware updates this bit after each transmission attempt. |
|
| Bit 16 | RQCP2: Request completed mailbox2 |
|
Set by hardware when the last request (transmit or abort) has been performed. |
|
| Bit 15 | ABRQ1: Abort request for mailbox 1 |
|
Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. |
|
| Bits 14:12 | Reserved, must be kept at reset value. |
| Bit 11 | TERR1: Transmission error of mailbox1 |
|
This bit is set when the previous TX failed due to an error. |
|
| Bit 10 | ALST1: Arbitration lost for mailbox1 |
|
This bit is set when the previous TX failed due to an arbitration lost. |
|
| Bit 9 | TXOK1: Transmission OK of mailbox1 |
|
The hardware updates this bit after each transmission attempt. |
|
| Bit 8 | RQCP1: Request completed mailbox1 |
|
Set by hardware when the last request (transmit or abort) has been performed. |
|
| Bit 7 | ABRQ0: Abort request for mailbox0 |
|
Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. |
|
| Bits 6:4 | Reserved, must be kept at reset value. |
| Bit 3 | TERR0: Transmission error of mailbox0 |
|
This bit is set when the previous TX failed due to an error. |
|
| Bit 2 | ALST0: Arbitration lost for mailbox0 |
|
This bit is set when the previous TX failed due to an arbitration lost. |
|
| Bit 1 | TXOK0: Transmission OK of mailbox0 |
|
The hardware updates this bit after each transmission attempt. |
|
| Bit 0 | RQCP0: Request completed mailbox0 |
|
Set by hardware when the last request (transmit or abort) has been performed. |
CAN receive FIFO 0 register (CAN_RF0R)
Address offset: 0x0C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFOM0 | FOVR0 | FULL0 | Res. | FMP0[1:0] |
|
| rs | rc_w1 | rc_w1 | r | r | |||||||||||||||||||||||||||
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bit 5 | RFOM0: Release FIFO 0 output mailbox |
|
Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect. If at least two messages are pending in the FIFO, the software has to release the output mailbox to access the next message. |
|
| Bit 4 | FOVR0: FIFO 0 overrun |
|
This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. |
|
| Bit 3 | FULL0: FIFO 0 full |
|
Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bits 1:0 | FMP0[1:0]: FIFO 0 message pending |
|
These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit. |
CAN receive FIFO 1 register (CAN_RF1R)
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFOM1 | FOVR1 | FULL1 | Res. | FMP1[1:0] |
|
| rs | rc_w1 | rc_w1 | r | r |
|||||||||||||||||||||||||||
| Bits 31:6 | Reserved, must be kept at reset value. |
| Bit 5 | RFOM1: Release FIFO 1 output mailbox |
|
Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect. If at least two messages are pending in the FIFO, the software has to release the output mailbox to access the next message. |
|
| Bit 4 | FOVR1: FIFO 1 overrun |
|
This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. |
|
| Bit 3 | FULL1: FIFO 1 full |
|
Set by hardware when three messages are stored in the FIFO. |
|
| Bit 2 | Reserved, must be kept at reset value. |
| Bits 1:0 | FMP1[1:0]: FIFO 1 message pending |
|
These bits indicate how many messages are pending in the receive FIFO1. FMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is decreased each time the software releases the output mailbox by setting the RFOM1 bit. |
CAN interrupt enable register (CAN_IER)
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SLKIE | WKUIE |
ERRIE | Res. | Res. | Res. | LEC IE |
BOF IE |
EPV IE |
EWG IE |
Res. | FOV IE1 |
FF IE1 |
FMP IE1 |
FOV IE0 |
FF IE0 |
FMP IE0 |
TME IE |
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | SLKIE: Sleep interrupt enable |
|
0: No interrupt when SLAKI bit is set. |
|
| Bit 16 | WKUIE: Wakeup interrupt enable |
|
0: No interrupt when WKUI is set. |
|
| Bit 15 | ERRIE: Error interrupt enable |
|
0: No interrupt will be generated when an error condition is pending in the CAN_ESR. |
|
| Bits 14:12 | Reserved, must be kept at reset value. |
| Bit 11 | LECIE: Last error code interrupt enable |
|
0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection. |
|
| Bit 10 | BOFIE: Bus-off interrupt enable |
|
0: ERRI bit will not be set when BOFF is set. |
|
| Bit 9 | EPVIE: Error passive interrupt enable |
|
0: ERRI bit will not be set when EPVF is set. |
|
| Bit 8 | EWGIE: Error warning interrupt enable |
|
0: ERRI bit will not be set when EWGF is set. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | FOVIE1: FIFO overrun interrupt enable |
|
0: No interrupt when FOVR is set. |
|
| Bit 5 | FFIE1: FIFO full interrupt enable |
|
0: No interrupt when FULL bit is set. |
|
| Bit 4 | FMPIE1: FIFO message pending interrupt enable |
|
0: No interrupt generated when state of FMP[1:0] bits are not 00b. |
|
| Bit 3 | FOVIE0: FIFO overrun interrupt enable |
|
0: No interrupt when FOVR bit is set. |
|
| Bit 2 | FFIE0: FIFO full interrupt enable |
|
0: No interrupt when FULL bit is set. |
|
| Bit 1 | FMPIE0: FIFO message pending interrupt enable |
|
0: No interrupt generated when state of FMP[1:0] bits are not 00b. |
|
| Bit 0 | TMEIE: Transmit mailbox empty interrupt enable |
|
0: No interrupt when RQCPx bit is set.
Refer to Section 40.8: bxCAN interrupts.
|
CAN error status register (CAN_ESR)
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REC[7:0] | TEC[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LEC[2:0] | Res. | BOFF | EPVF | EWGF |
||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
rw | rw | rw | r | r | r | ||||||||||
| Bits 31:24 | REC[7:0]: Receive error counter |
|
The implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. |
|
| Bits 23:16 | TEC[7:0]: Least significant byte of the 9-bit transmit error counter |
|
The implementing part of the fault confinement mechanism of the CAN protocol. |
|
| Bits 15:7 | Reserved, must be kept at reset value. |
| Bits 6:4 | LEC[2:0]: Last error code |
|
This field is set by hardware and holds a code which indicates the error condition of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’. The LEC[2:0] bits can be set to value 0b111 by software. They are updated by hardware to indicate the current communication status. |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bit 2 | BOFF: Bus-off flag |
|
This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255, refer to Section 40.7.6 on page 1548. |
|
| Bit 1 | EPVF: Error passive flag |
|
This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127). |
|
| Bit 0 | EWGF: Error warning flag |
|
This bit is set by hardware when the warning limit has been reached (Receive Error Counter or Transmit Error Counter≥96). |
CAN bit timing register (CAN_BTR)
Address offset: 0x1C
Reset value: 0x0123 0000
This register can only be accessed by the software when the CAN hardware is in initialization mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SILM | LBKM | Res. | Res. | Res. | Res. | SJW[1:0] | Res. | TS2[2:0] | TS1[3:0] |
Res. | Res. | Res. | Res. | Res. | Res. | BRP[9:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||
| Bit 31 | SILM: Silent mode (debug) |
|
0: Normal operation |
|
| Bit 30 | LBKM: Loop back mode (debug) |
|
0: Loop Back Mode disabled |
|
| Bits 29:26 | Reserved, must be kept at reset value. |
| Bits 25:24 | SJW[1:0]: Resynchronization jump width |
|
These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization. |
|
| Bit 23 | Reserved, must be kept at reset value. |
| Bits 22:20 | TS2[2:0]: Time segment 2 |
|
These bits define the number of time quanta in Time Segment 2. |
|
| Bits 19:16 | TS1[3:0]: Time segment 1 |
|
These bits define the number of time quanta in Time Segment 1 |
|
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bits 9:0 | BRP[9:0]: Baud rate prescaler |
|
These bits define the length of a time quanta. |
This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 40.7.5: Message storage on page 1546 for detailed register mapping.
Transmit and receive mailboxes have the same registers except:
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.
| (omitted) |
CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2)
Address offsets: 0x180, 0x190, 0x1A0
Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0)
All TX registers are write protected when the mailbox is pending transmission (TMEx reset).
This register also implements the TX request control (bit 0) - reset value 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STID[10:0]/EXID[28:18] | EXID[17:13] |
EXID[12:0] | IDE | RTR | TXRQ |
||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:21 | STID[10:0]/EXID[28:18]: Standard identifier or extended identifier |
|
The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value). |
|
| Bits 20:3 | EXID[17:0]: Extended identifier |
|
The LSBs of the extended identifier. |
|
| Bit 2 | IDE: Identifier extension |
|
This bit defines the identifier type of message in the mailbox. |
|
| Bit 1 | RTR: Remote transmission request |
|
0: Data frame |
|
| Bit 0 | TXRQ: Transmit mailbox request |
|
Set by software to request the transmission for the corresponding mailbox. |
CAN mailbox data length control and time stamp register
(CAN_TDTxR) (x = 0..2)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x184, 0x194, 0x1A4
Reset value: 0xXXXX XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIME[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DLC[3:0] |
||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw |
||||||||||||
| Bits 31:16 | TIME[15:0]: Message time stamp |
|
This field contains the 16-bit timer value captured at the SOF transmission. |
|
| Bits 15:9 | Reserved, must be kept at reset value. |
| Bit 8 | TGT: Transmit global time |
|
This bit is active only when the hardware is in the Time Trigger Communication mode, TTCM bit of the CAN_MCR register is set. |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | DLC[3:0]: Data length code |
|
This field defines the number of data bytes a data frame contains or a remote frame request. |
CAN mailbox data low register (CAN_TDLxR) (x = 0..2)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x188, 0x198, 0x1A8
Reset value: 0xXXXX XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA3[7:0] | DATA2[7:0] |
DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | DATA3[7:0]: Data byte 3 |
|
Data byte 3 of the message. |
|
| Bits 23:16 | DATA2[7:0]: Data byte 2 |
|
Data byte 2 of the message. |
|
| Bits 15:8 | DATA1[7:0]: Data byte 1 Data byte 1 of the message. |
| Bits 7:0 | DATA0[7:0]: Data byte 0 |
|
Data byte 0 of the message. |
CAN mailbox data high register (CAN_TDHxR) (x = 0..2)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x18C, 0x19C, 0x1AC
Reset value: 0xXXXX XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA7[7:0] | DATA6[7:0] |
DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:24 | DATA7[7:0]: Data byte 7 |
|
Data byte 7 of the message. If TGT of this message and TTCM are active, DATA7 and DATA6 will be replaced by |
|
| Bits 23:16 | DATA6[7:0]: Data byte 6 |
|
Data byte 6 of the message. |
|
| Bits 15:8 | DATA5[7:0]: Data byte 5 Data byte 5 of the message. |
| Bits 7:0 | DATA4[7:0]: Data byte 4 Data byte 4 of the message. |
CAN receive FIFO mailbox identifier register (CAN_RIxR) (x = 0..1)
Address offsets: 0x1B0, 0x1C0
Reset value: 0xXXXX XXXX
All RX registers are write protected.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STID[10:0]/EXID[28:18] | EXID[17:13] |
EXID[12:0] | IDE | RTR | Res |
||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
|
| Bits 31:21 | STID[10:0]/EXID[28:18]: Standard identifier or extended identifier |
|
The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value). |
|
| Bits 20:3 | EXID[17:0]: Extended identifier |
|
The LSBs of the extended identifier. |
|
| Bit 2 | IDE: Identifier extension |
|
This bit defines the identifier type of message in the mailbox. |
|
| Bit 1 | RTR: Remote transmission request |
|
0: Data frame |
|
| Bit 0 | Reserved, must be kept at reset value. |
CAN receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x = 0..1)
Address offsets: 0x1B4, 0x1C4
Reset value: 0xXXXX XXXX
All RX registers are write protected.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIME[15:0] |
FMI[7:0] | Res. | Res. | Res. | Res. | DLC[3:0] |
|||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r |
||||
| Bits 31:16 | TIME[15:0]: Message time stamp |
|
This field contains the 16-bit timer value captured at the SOF detection. |
|
| Bits 15:8 | FMI[7:0]: Filter match index |
|
This register contains the index of the filter the message stored in the mailbox passed through. For more details on identifier filtering refer to Section 40.7.4: Identifier filtering on |
|
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | DLC[3:0]: Data length code |
|
This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case of a remote frame request. |
CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x1B8, 0x1C8
Reset value: 0xXXXX XXXX
All RX registers are write protected.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA3[7:0] | DATA2[7:0] |
DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:24 | DATA3[7:0]: Data Byte 3 |
|
Data byte 3 of the message. |
|
| Bits 23:16 | DATA2[7:0]: Data Byte 2 |
|
Data byte 2 of the message. |
|
| Bits 15:8 | DATA1[7:0]: Data Byte 1 Data byte 1 of the message. |
| Bits 7:0 | DATA0[7:0]: Data Byte 0 |
|
Data byte 0 of the message. |
CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1)
Address offsets: 0x1BC, 0x1CC
Reset value: 0xXXXX XXXX
All RX registers are write protected.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA7[7:0] | DATA6[7:0] |
DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:24 | DATA7[7:0]: Data Byte 7 |
|
Data byte 3 of the message. |
|
| Bits 23:16 | DATA6[7:0]: Data Byte 6 |
|
Data byte 2 of the message. |
|
| Bits 15:8 | DATA5[7:0]: Data Byte 5 Data byte 1 of the message. |
| Bits 7:0 | DATA4[7:0]: Data Byte 4 |
|
Data byte 0 of the message. |
CAN filter master register (CAN_FMR)
Address offset: 0x200
Reset value: 0x2A1C 0E01
All bits of this register are set and cleared by software.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | CANSB[5:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FINIT |
|||||
| rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bits 13:8 | CANSB[5:0]: CAN start bank |
|
These bits are set and cleared by software. When both CAN are used, they define the start bank of each CAN interface: 000001 = 1 filter assigned to CAN1 and 27 assigned to CAN2
Bits [13:8] are available only for dual CAN peripheral configuration and are reserved |
|
| Bits 7:1 | Reserved, must be kept at reset value. |
| Bit 0 | FINIT: Filter initialization mode |
|
Initialization mode for filter banks |
CAN filter mode register (CAN_FM1R)
Address offset: 0x204
Reset value: 0x0000 0000
This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | FBM27 | FBM26 | FBM25 | FBM24 | FBM23 | FBM22 | FBM21 | FBM20 | FBM19 | FBM18 | FBM17 | FBM16 |
FBM15 | FBM14 | FBM13 | FBM12 | FBM11 | FBM10 | FBM9 | FBM8 | FBM7 | FBM6 | FBM5 | FBM4 | FBM3 | FBM2 | FBM1 | FBM0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Refer to Figure 501: Filter bank scale configuration - register organization on page 1544.
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:0 | FBMx: Filter mode |
|
Mode of the registers of Filter x. 0: Two 32-bit registers of filter bank x are in Identifier Mask mode. Bits 27:14 are available for dual CAN configuration and are reserved for single CAN |
CAN filter scale register (CAN_FS1R)
Address offset: 0x20C
Reset value: 0x0000 0000
This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | FSC27 | FSC26 | FSC25 | FSC24 | FSC23 | FSC22 | FSC21 | FSC20 | FSC19 | FSC18 | FSC17 | FSC16 |
FSC15 | FSC14 | FSC13 | FSC12 | FSC11 | FSC10 | FSC9 | FSC8 | FSC7 | FSC6 | FSC5 | FSC4 | FSC3 | FSC2 | FSC1 | FSC0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:0 | FSCx: Filter scale configuration |
|
These bits define the scale configuration of Filters 27-0. Bits 27:14 are available for dual CAN configuration and are reserved for single CAN |
Note: Refer to Figure 501: Filter bank scale configuration - register organization on page 1544.
CAN filter FIFO assignment register (CAN_FFA1R)
Address offset: 0x214
Reset value: 0x0000 0000
This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | FFA27 | FFA26 | FFA25 | FFA24 | FFA23 | FFA22 | FFA21 | FFA20 | FFA19 | FFA18 | FFA17 | FFA16 |
FFA15 | FFA14 | FFA13 | FFA12 | FFA11 | FFA10 | FFA9 | FFA8 | FFA7 | FFA6 | FFA5 | FFA4 | FFA3 | FFA2 | FFA1 | FFA0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:0 | FFAx: Filter FIFO assignment for filter x |
|
The message passing through this filter will be stored in the specified FIFO. Bits 27:14 are available for dual CAN configuration and are reserved for single CAN |
CAN filter activation register (CAN_FA1R)
Address offset: 0x21C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | FACT 27 |
FACT 26 |
FACT 25 |
FACT 24 |
FACT 23 |
FACT 22 |
FACT 21 |
FACT 20 |
FACT 19 |
FACT 18 |
FACT 17 |
FACT 16 |
FACT 15 |
FACT 14 |
FACT 13 |
FACT 12 |
FACT 11 |
FACT 10 |
FACT9 | FACT8 | FACT7 | FACT6 | FACT5 | FACT4 | FACT3 | FACT2 | FACT1 | FACT0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bits 27:0 | FACTx: Filter active |
|
The software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]), the FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set. Bits 27:14 are available for dual CAN configuration and are reserved for single CAN |
Filter bank i register x (CAN_FiRx) (i = 0..27, x = 1, 2)
Address offsets: 0x240 to 0x31C
Reset value: 0xXXXX XXXX
Depending on CAN peripheral configuration there are 28 filter banks, in dual CAN or 14 filter banks in single CAN configuration. Each filter bank i (i= 0 to 27 in dual CAN configuration and i= 0 to 13 in single CAN configuration) is composed of two 32-bit registers, CAN_FiR[2:1].
This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FB31 | FB30 | FB29 | FB28 | FB27 | FB26 | FB25 | FB24 | FB23 | FB22 | FB21 | FB20 | FB19 | FB18 | FB17 | FB16 |
FB15 | FB14 | FB13 | FB12 | FB11 | FB10 | FB9 | FB8 | FB7 | FB6 | FB5 | FB4 | FB3 | FB2 | FB1 | FB0 |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
In all configurations:
| Bits 31:0 | FB[31:0]: Filter bits |
|
Identifier |
Note: Depending on the scale and mode configuration of the filter the function of each register can
differ. For the filter mapping, functions description and mask registers association, refer to
Section 40.7.4: Identifier filtering on page 1542.
A Mask/Identifier register in mask mode has the same bit mapping as in identifier list
mode.
For the register mapping/addresses of the filter banks refer to Table 283 on page 1573.
Refer to Section 2.2.2 on page 76 for the register boundary addresses. The registers from offset 0x200 to 0x31C are present only in CAN1 and CAN3.
| Offset | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 |
CAN_MCR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBF | RESET | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TTCM | ABOM | AWUM | NART | RFLM | TXFP | SLEEP | INRQ |
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|||||||||||||||||||||||
| 0x004 |
CAN_MSR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RX | SAMP | RXM | TXM | Res. | Res. | Res. | SLAKI | WKUI | ERRI | SLAK | INAK |
| Reset value | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
||||||||||||||||||||||||
| 0x008 |
CAN_TSR
|
LOW[2:0] | TME[2:0] | CODE[1:0] | ABRQ2 | Res. | Res. | Res. | TERR2 | ALST2 | TXOK2 | RQCP2 | ABRQ1 | Res. | Res. | Res. | TERR1 | ALST1 | TXOK1 | RQCP1 | ABRQ0 | Res. | Res. | Res. | TERR0 | ALST0 | TXOK0 | RQCP0 | |||||
| Reset value | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x00C |
CAN_RF0R
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFOM0 | FOVR0 | FULL0 | Res. | FMP0[1:0] | |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x010 |
CAN_RF1R
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFOM1 | FOVR1 | FULL1 | Res. | FMP1[1:0] | |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x014 |
CAN_IER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SLKIE | WKUIE | ERRIE | Res. | Res. | Res. | LECIE | BOFIE | EPVIE | EWGIE | Res. | FOVIE1 | FFIE1 | FMPIE1 | FOVIE0 | FFIE0 | FMPIE0 | TMEIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x018 |
CAN_ESR | REC[7:0] | TEC[7:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LEC[2:0] | Res. | BOFF | EPVF | EWGF | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||
| 0x01C |
CAN_BTR
|
SILM | LBKM | Res. | Res. | Res. | Res. | SJW[1:0] | Res. | TS2[2:0] | TS1[3:0] |
Res. | Res. | Res. | Res. | Res. | Res. | BRP[9:0] |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| 0x020- 0x17F |
- |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x180 |
CAN_TI0R | STID[10:0]/EXID[28:18] | EXID[17:0] |
IDE | RTR | TXRQ | |||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | 0 | |
| 0x184 |
CAN_TDT0R | TIME[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGT | Res. | Res. | Res. | Res. | DLC[3:0] |
||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - | - | - | - | - | - | - | x | - | - | - | - | x | x | x | x |
|
| 0x188 |
CAN_TDL0R | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x18C |
CAN_TDH0R | DATA7[7:0] | DATA6[7:0] | DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x190 |
CAN_TI1R | STID[10:0]/EXID[28:18] | EXID[17:0] |
IDE | RTR | TXRQ | |||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | 0 |
|
| 0x194 |
CAN_TDT1R | TIME[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGT | Res. | Res. | Res. | Res. | DLC[3:0] |
||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - | - | - | - | - | - | - | x | - | - | - | - | x | x | x | x |
|
| 0x198 |
CAN_TDL1R | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x19C |
CAN_TDH1R | DATA7[7:0] | DATA6[7:0] | DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1A0 |
CAN_TI2R | STID[10:0]/EXID[28:18] | EXID[17:0] |
IDE | RTR | TXRQ | |||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | 0 |
|
| 0x1A4 |
CAN_TDT2R | TIME[15:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGT | Res. | Res. | Res. | Res. | DLC[3:0] |
||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - | - | - | - | - | - | - | x | - | - | - | - | x | x | x | x |
|
| 0x1A8 |
CAN_TDL2R | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1AC |
CAN_TDH2R | DATA7[7:0] | DATA6[7:0] | DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1B0 |
CAN_RI0R | STID[10:0]/EXID[28:18] | EXID[17:0] |
IDE | RTR | Res. | |||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - |
|
| 0x1B4 |
CAN_RDT0R | TIME[15:0] | FMI[7:0] |
Res. | Res. | Res. | Res. | DLC[3:0] |
|||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - | - | - | - | x | x | x | x |
|
| 0x1B8 |
CAN_RDL0R | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1BC |
CAN_RDH0R | DATA7[7:0] | DATA6[7:0] | DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1C0 |
CAN_RI1R | STID[10:0]/EXID[28:18] | EXID[17:0] |
IDE | RTR | Res. | |||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - |
|
| 0x1C4 |
CAN_RDT1R | TIME[15:0] | FMI[7:0] |
Res. | Res. | Res. | Res. | DLC[3:0] |
|||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | - | - | - | - | x | x | x | x |
|
| 0x1C8 |
CAN_RDL1R | DATA3[7:0] | DATA2[7:0] | DATA1[7:0] | DATA0[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1CC |
CAN_RDH1R | DATA7[7:0] | DATA6[7:0] | DATA5[7:0] | DATA4[7:0] |
||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x1D0- 0x1FF |
- |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x200 |
CAN_FMR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CANSB[5:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | FINIT | |||||
| Reset value | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
||||||||||||||||||||||||||
| 0x204 |
CAN_FM1R
|
Res. | Res. | Res. | Res. | FBM[27:0] |
|||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x208 |
- |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| - |
|||||||||||||||||||||||||||||||||
| 0x20C |
CAN_FS1R
|
Res. | Res. | Res. | Res. | FSC[27:0] |
|||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x210 | - |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x214 |
CAN_FFA1R
|
Res. | Res. | Res. | Res. | FFA[27:0] |
|||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x218 | - |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x21C |
CAN_FA1R
|
Res. | Res. | Res. | Res. | FACT[27:0] |
|||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||
| 0x220 | - |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x224- 0x23F |
- |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 0x240 |
CAN_F0R1 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x244 |
CAN_F0R2 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x248 |
CAN_F1R1 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x24C |
CAN_F1R2 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x318 |
CAN_F27R1 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
| 0x31C |
CAN_F27R2 | FB[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x |
|
Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.
This section presents the architecture and the programming model of the OTG_FS/OTG_HS controller.
The following acronyms are used throughout the section:
FS Full-speed
LS Low-speed
HS High-speed
MAC Media access controller
OTG On-the-go
PFC Packet FIFO controller
PHY Physical layer
USB Universal serial bus
UTMI USB 2.0 Transceiver Macrocell interface (UTMI)
ULPI UTMI+ Low Pin Interface
LPM Link power management
BCD Battery charging detector
HNP Host negotiation protocol
SRP Session request protocol
References are made to the following documents:
The USB OTG is a dual-role device (DRD) controller that supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0
Specification. It can also be configured as a host-only or device-only controller, fully compliant with the USB 2.0 Specification. OTG_HS supports the speeds defined in the Table 284: OTG_HS speeds supported below.OTG_FS supports the speeds defined in the Table 285: OTG_FS speeds supported below. The USB OTG supports both HNP and SRP. The only external device required is a charge pump for VBUS in OTG mode.
| - | HS (480 Mb/s) | FS (12 Mb/s) | LS (1.5 Mb/s) |
|---|---|---|---|
| Host mode | X | X | X |
| Device mode | X | X | - |
| - | HS (480 Mb/s) | FS (12 Mb/s) | LS (1.5 Mb/s) |
|---|---|---|---|
| Host mode | - | X | X |
| Device mode | - | X | - |
The main features can be divided into three categories: general, host-mode and device-mode features.
The OTG_FS/OTG_HS interface general features are the following:
The OTG_FS/OTG_HS interface main features and requirements in host-mode are the following:
The OTG_FS/OTG_HS interface main features in peripheral-mode are the following:
| USB features | OTG_FS | OTG_HS |
|---|---|---|
| Device bidirectional endpoints (including EP0) | 6 | 9 |
| Host mode channels | 12 | 16 |
| Size of dedicated SRAM | 1.2 KB | 4 KB |
| USB 2.0 link power management (LPM) support | X |
|
| OTG revision supported | 2.0 |
|
| Attach detection protocol (ADP) support | - |
|
| Battery charging detection (BCD) support | - | |
| (omitted) |
| (omitted) |
| Signal name | Signal type | Description |
|---|---|---|
| OTG_FS_DP | Digital input/output | USB OTG D+ line |
| OTG_FS_DM | Digital input/output | USB OTG D- line |
| OTG_FS_ID | Digital input | USB OTG ID |
| OTG_FS_VBUS | Analog input | USB OTG VBUS |
| OTG_FS_SOF | Digital output | USB OTG Start Of Frame (visibility) |
| Signal name | Signal type | Description |
|---|---|---|
| OTG_HS_DP | Digital input/output | USB OTG D+ line |
| OTG_HS_DM | Digital input/output | USB OTG D- line |
| OTG_HS_ID | Digital input | USB OTG ID |
| OTG_HS_VBUS | Analog input | USB OTG VBUS |
| OTG_HS_SOF | Digital output | USB OTG Start Of Frame (visibility) |
| OTG_HS_ULPI_CK | Digital input | USB OTG ULPI clock |
| OTG_HS_ULPI_DIR | Digital input | USB OTG ULPI data bus direction control |
| OTG_HS_ULPI_STP | Digital output | USB OTG ULPI data stream stop |
| OTG_HS_ULPI_NXT | Digital input | USB OTG ULPI next data stream request |
| OTG_HS_ULPI_D[0..7] | Digital input/output | USB OTG ULPI 8-bit bi-directional data bus |
| Signal name | Signal type | Description |
|---|---|---|
| usb_sof | Digital output | USB OTG start-of-frame event for on chip peripherals |
| usb_wkup | Digital output | USB OTG wakeup event output |
| usb_gbl_it | Digital output | USB OTG global interrupt |
| usb_ep1_in_it | Digital output | USB OTG endpoint 1 in interrupt |
| usb_ep1_out_it | Digital output | USB OTG endpoint 1 out interrupt |
The USB OTG receives the 48 MHz clock from the reset and clock controller (RCC). The USB clock is used for driving the 48 MHz domain at full-speed (12 Mbit/s) and must be enabled prior to configuring the OTG core.
The CPU reads and writes from/to the OTG core registers through the AHB peripheral bus. It is informed of USB events through the single USB OTG interrupt line described in Section 41.13: OTG_FS/OTG_HS interrupts.
The CPU submits data over the USB by writing 32-bit words to dedicated OTG locations (push registers). The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM. There is one Tx FIFO push register for each in-endpoint (peripheral mode) or out-channel (host mode).
The CPU receives the data from the USB by reading 32-bit words from dedicated OTG addresses (pop registers). The data are then automatically retrieved from a shared Rx FIFO configured within the 1.25[FS] / 4[HS]-Kbyte USB data RAM. There is one Rx FIFO pop register for each out-endpoint or in-channel.
The USB protocol layer is driven by the serial interface engine (SIE) and serialized over the USB by the transceiver module within the on-chip physical layer (PHY) or external HS PHY.
The embedded full-speed OTG PHY is controlled by the OTG FS core and conveys USB control & data signals through the full-speed subset of the UTMI+ Bus (UTMIFS). It provides
a. The content of this section applies only to USB OTG FS.
the physical support to USB connectivity.
The full-speed OTG PHY includes the following components:
Caution: To guarantee a correct operation for the USB OTG FS peripheral, the AHB frequency should be higher than 14.2 MHz.
The full-speed OTG PHY includes the following components:
a. The content of this section applies only to USB OTG HS.
To guarantee a correct operation for the USB OTG_HS peripheral, the AHB frequency should be higher than 30 MHz.
The USB OTG_HS core includes an ULPI interface to connect an external HS PHY.
| (omitted) |
The host or peripheral (the default) role is assumed depending on the ID input pin. The ID line status is determined on plugging in the USB cable, depending on whether a MicroA or MicroB plug is connected to the micro-AB receptacle.
a. The content of this section applies only to USB OTG HS.
The HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_ GUSBCFG) enables the OTG_FS/OTG_HS core to dynamically change its role from A-host to A-peripheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the host negotiation protocol (HNP). The current device status can be read by the combined values of the connector ID status bit in the Global OTG control and status register (CIDSTS bit in OTG_GOTGCTL) and the current mode of operation bit in the global interrupt and status register (CMOD bit in OTG_GINTSTS).
The HNP program model is described in detail in Section 41.16: OTG_FS/OTG_HS
programming model.
The SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_FS/OTG_HS core to switch off the generation of VBUS
for the A-device to save power. Note that the A-device is always in charge of driving VBUS
regardless of the host or peripheral role of the OTG_FS/OTG_HS.
The SRP A/B-device program model is described in detail in Section 41.16:
OTG_FS/OTG_HS programming model.
This section gives the functional description of the OTG_FS/OTG_HS in the USB peripheral mode. The OTG_FS/OTG_HS works as an USB peripheral in the following circumstances:
Note: To build a bus-powered device implementation in case of the B-device or peripheral-only
configuration, an external regulator has to be added, that generates the necessary power-supply from VBUS.
| (omitted) |
The SRP capable bit in the Global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_FS/OTG_HS to support the session request protocol (SRP). In this way, it allows the remote A-device to save power by switching off VBUS while the USB session is suspended.
The SRP peripheral mode program model is described in detail in the B-device session
request protocol section.
Powered state
The VBUS input detects the B-session valid voltage by which the USB peripheral is allowed to enter the powered state (see USB2.0 section 9.1). The OTG_FS/OTG_HS then automatically connects the DP pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (SRQINT bit in OTG_GINTSTS) to notify the powered state.
The VBUS input also ensures that valid VBUS levels are supplied by the host during USB operations. If a drop in VBUS below B-session valid happens to be detected (for instance because of a power disturbance or if the host port has been switched off), the OTG_FS/OTG_HS automatically disconnects and the session end detected (SEDET bit in OTG_GOTGINT) interrupt is generated to notify that the OTG_FS/OTG_HS has exited the powered state.
In the powered state, the OTG_FS/OTG_HS expects to receive some reset signaling from the host. No other USB operation is possible. When a reset signaling is received the reset detected interrupt (USBRST in OTG_GINTSTS) is generated. When the reset signaling is complete, the enumeration done interrupt (ENUMDNE bit in OTG_GINTSTS) is generated and the OTG_FS/OTG_HS enters the Default state.
Soft disconnect
The powered state can be exited by software with the soft disconnect feature. The DP pull-up resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port.
Default state
In the Default state the OTG_FS/OTG_HS expects to receive a SET_ADDRESS command from the host. No other USB operation is possible. When a valid SET_ADDRESS command is decoded on the USB, the application writes the corresponding number into the device address field in the device configuration register (DAD bit in OTG_DCFG). The OTG_FS/OTG_HS then enters the address state and is ready to answer host transactions at the configured USB address.
Suspended state
The OTG_FS/OTG_HS peripheral constantly monitors the USB activity. After counting 3 ms of USB idleness, the early suspend interrupt (ESUSP bit in OTG_GINTSTS) is issued, and confirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in OTG_GINTSTS). The device suspend bit is then automatically set in the device status register (SUSPSTS bit in OTG_DSTS) and the OTG_FS/OTG_HS enters the suspended state.
The suspended state may optionally be exited by the device itself. In this case the application sets the remote wakeup signaling bit in the device control register (RWUSIG bit in OTG_DCTL) and clears it after 1 to 15 ms.
When a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in OTG_GINTSTS) is generated and the device suspend bit is automatically cleared.
The OTG_FS/OTG_HS core instantiates the following USB endpoints:
which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF).
Endpoint control
Endpoint transfer
The device endpoint-x transfer size registers (OTG_DIEPTSIZx/OTG_DOEPTSIZx) allow the application to program the transfer size parameters and read the transfer status. Programming must be done before setting the endpoint enable bit in the endpoint control register. Once the endpoint is enabled, these fields are read-only as the OTG_FS/OTG_HS core updates them with the current transfer status.
The following transfer parameters can be programmed:
Endpoint status/interrupt
The device endpoint-x interrupt registers (OTG_DIEPINTx/OTG_DOPEPINTx) indicate the status of an endpoint with respect to USB- and AHB-related events. The application must read these registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in
the core interrupt register (OEPINT bit in OTG_GINTSTS or IEPINT bit in OTG_GINTSTS, respectively) is set. Before the application can read these registers, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers
The peripheral core provides the following status checks and interrupt generation:
This section gives the functional description of the OTG_FS/OTG_HS in the USB host mode. The OTG_FS/OTG_HS works as a USB host in the following circumstances:
Note: On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are
available on the application board, a basic power switch must be added externally to drive
the 5 V VBUS line. The external charge pump can be driven by any GPIO output. This is
required for the OTG A-host, A-device and host-only configurations.
| (omitted) |
SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG). With the SRP feature enabled, the host can save power by switching off the VBUS power while the USB session is suspended.
The SRP host mode program model is described in detail in the A-device session request
protocol) section.
Host port power
On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch, must be added externally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO output or via an I
2C interface connected to an external PMIC (power management IC). When the application decides to power on VBUS, it must also set the port power bit in the host port control and status register (PPWR bit in OTG_HPRT).
VBUS valid
When HNP or SRP is enabled the VBUS sensing pin should be connected to VBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold (4.4 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in OTG_GOTGINT). The application is then required to remove the VBUS power and clear the port power bit.
When HNP and SRP are both disabled, the VBUS sensing pin does not need to be connected to VBUS.
The charge pump overcurrent flag can also be used to prevent electrical damage. Connect the overcurrent flag output from the charge pump to any GPIO input and configure it to generate a port interrupt on the active level. The overcurrent ISR must promptly disable the VBUS generation and clear the port power bit.
Host detection of a peripheral connection
If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_FS/OTG_HS will not detect any bus connection until VBUS is no longer sensed at a valid level (5 V). When VBUS is at a valid level and a remote B-device is attached, the OTG_FS/OTG_HS core issues a host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in OTG_HPRT).
When HNP and SRP are both disabled, USB peripherals or B-device are detected as soon as they are connected. The OTG_FS/OTG_HS core issues a host port interrupt triggered by the device connected bit in the host port control and status (PCDET bit in OTG_HPRT).
Host detection of peripheral a disconnection
The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_GINTSTS).
Host enumeration
After detecting a peripheral connection the host must start the enumeration process by sending USB reset and configuration commands to the new peripheral.
Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by the debounce done bit (DBCDNE bit in OTG_GOTGINT), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on DP (FS) or DM (LS).
The application drives a USB reset signaling (single-ended zero) over the USB by keeping the port reset bit set in the host port control and status register (PRST bit in OTG_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes care of the timing count and then of clearing the port reset bit.
Once the USB reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (PENCHNG bit in OTG_HPRT). This informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (PSPD bit in OTG_HPRT) and that the host is starting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the peripheral enumeration by sending peripheral configuration commands.
Host suspend
The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_HPRT). The OTG_FS/OTG_HS core stops sending SOFs and enters the suspended state.
The suspended state can be optionally exited on the remote device’s initiative (remote wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_GINTSTS) is generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (PRES bit in OTG_HPRT) self-sets, and resume signaling is automatically driven over the USB. The application must time the resume window and then clear the port resume bit to exit the suspended state and restart the SOF.
If the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit.
The OTG_FS/OTG_HS core instantiates 12[FS] / 16[HS] host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 12[FS] / 16[HS] transfer requests at the same time. If more than 12[FS] / 16[HS] transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts.
Each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (OTG_HCCHARx), transfer configuration (OTG_HCTSIZx) and status/interrupt (OTG_HCINTx) registers with associated mask (OTG_HCINTMSKx) registers.
Host channel control
Host channel transfer
The host channel transfer size registers (OTG_HCTSIZx) allow the application to program the transfer size parameters, and read the transfer status. Programming must be done before setting the channel enable bit in the host channel characteristics register. Once the endpoint is enabled the packet count field is read-only as the OTG_FS/OTG_HS core updates it according to the current transfer status.
Host channel status/interrupt
The host channel-x interrupt register (OTG_HCINTx) indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read these register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read these registers, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
The mask bits for each interrupt source of each channel are also available in the OTG_HCINTMSKx register.
The host core features a built-in hardware scheduler which is able to autonomously re-order and manage the USB transaction requests posted by the application. At the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interrupt transfer types by the USB specification.
The host processes the USB transactions through request queues (one for periodic and one for nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a pending transaction request from the application, and holds the IN or OUT channel number along with other information to perform a transaction on the USB. The order in which the requests are written to the queue determines the sequence of the transactions on the USB interface.
At the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt (IPXFR bit in OTG_GINTSTS) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the current frame. The OTG_FS/OTG_HS core is fully responsible for the management of the periodic and nonperiodic request queues.The periodic transmit FIFO and queue status register (OTG_HPTXSTS) and nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) are read-only registers which can be used by the application to read the status of each request queue. They contain:
As request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respect to the moment they physically reach the SB for a maximum of 8 pending periodic transactions plus 8 pending non-periodic transactions.
To post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the
PTXQSAV bits in the OTG_HNPTXSTS register or NPTQXSAV bits in the OTG_HNPTXSTS register.
| (omitted) |
The OTG_FS/OTG_HS core provides means to monitor, track and configure SOF framing in the host and peripheral, as well as an SOF pulse output connectivity feature.
Such utilities are especially useful for adaptive audio clock generation techniques, where the audio peripheral needs to synchronize to the isochronous stream provided by the PC, or the host needs to trim its framing rate according to the requirements of the audio peripheral.
In host mode the number of PHY clocks occurring between the generation of two consecutive SOF (HS/FS) or Keep-alive (LS) tokens is programmable in the host frame interval register (HFIR), thus providing application control over the SOF framing period. An interrupt is generated at any start of frame (SOF bit in OTG_GINTSTS). The current frame number and the time remaining until the next SOF are tracked in the host frame number register (HFNUM).
A SOF pulse signal, is generated at any SOF starting token and with a width of 20 HCLK cycles. The SOF pulse is also internally connected to the input trigger of the timer, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse.
In device mode, the start of frame interrupt is generated each time an SOF token is received on the USB (SOF bit in OTG_GINTSTS). The corresponding frame number can be read from the device status register (FNSOF bit in OTG_DSTS). A SOF pulse signal with a width of 20 HCLK cycles is also generated.The SOF pulse signal is also internally connected to the TIM input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse.
The end of periodic frame interrupt (OTG_GINTSTS/EOPF) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_DCFG). This feature can be used to determine if all of the isochronous traffic for that frame is complete.
Table 290 below defines the STM32 low power modes and their compatibility with the OTG.
| Mode | Description | USB compatibility |
|---|---|---|
| Run | MCU fully active | Required when USB not in suspend state. |
| Sleep | USB suspend exit causes the device to exit Sleep mode. Peripheral registers content is kept. |
Available while USB is in suspend state. |
| Stop | USB suspend exit causes the device to exit Stop mode. Peripheral registers content is kept(1). |
Available while USB is in suspend state. |
| Standby | Powered-down. The peripheral must be reinitialized after exiting Standby mode. |
Not compatible with USB applications. |
The following bits and procedures reduce power consumption.
The power consumption of the OTG PHY is controlled by two or three bits in the general core configuration register, depending on OTG revision supported.
PHY power down (OTG_GCCFG/PWRDWN)
It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily set to allow any USB operation
VBUS detection enable (OTG_GCCFG/VBDEN)
It switches on/off the VBUS sensing comparators associated with OTG operations
Power reduction techniques are available while in the USB suspended state, when the USB session is not yet valid or the device is disconnected.
Stop PHY clock (STPPCLK bit in OTG_PCGCCTL)
When setting the stop PHY clock bit in the clock gating control register, most of the 48 MHz clock domain internal to the OTG full-speed core is switched off by clock gating. The dynamic power consumption due to the USB clock switching activity is cut even if the 48 MHz clock input is kept running by the application
Most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive.
Gate HCLK (GATEHCLK bit in OTG_PCGCCTL)
When setting the Gate HCLK bit in the clock gating control register, most of the system clock domain internal to the OTG_FS/OTG_HS core is switched off by clock gating. Only the register read and write interface is kept alive. The dynamic power
consumption due to the USB clock switching activity is cut even if the system clock is kept running by the application for other purposes.
USB system stop
When the OTG_FS/OTG_HS is in the USB suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system. USB System Stop is activated by first setting the Stop PHY clock bit and then configuring the system deep sleep mode in the power control system module (PWR).
The OTG_FS/OTG_HS core automatically reactivates both system and USB clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the USB.
To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS/OTG_HS core.
The USB core embeds a dynamic trimming capability of micro-SOF[HS] / SOF[FS] framing period in host mode allowing to synchronize an external device with the micro-SOF[HS] / SOF[FS] frames.
When the OTG_HFIR register is changed within a current micro-SOF[HS] / SOF[FS] frame, the SOF period correction is applied in the next frame as described in Figure 515.
For a dynamic update, it is required to set RLDCTRL=0.
| (omitted) |
The USB system features 1.25[FS] / 4[HS] Kbytes of dedicated RAM with a sophisticated FIFO control mechanism. The packet FIFO controller module in the OTG_FS/OTG_HS core organizes RAM space into Tx FIFOs into which the application pushes the data to be temporarily stored before the USB transmission, and into a single Rx FIFO where the data received from the USB are temporarily stored before retrieval (popped) by the application. The number of instructed FIFOs and how these are organized inside the RAM depends on
the device’s role. In peripheral mode an additional Tx FIFO is instructed for each active IN endpoint. Any FIFO size is software configured to better meet the application requirements.
| (omitted) |
Peripheral Rx FIFO
The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT endpoints. Received packets are stacked back-to-back until free space is available in the Rx FIFO. The status of the received packet (which contains the OUT endpoint destination number, the byte count, the data PID and the validity of the received data) is also stored by the core on top of the data payload. When no more space is available, host transactions are NACKed and an interrupt is received on the addressed endpoint. The size of the receive FIFO is configured in the receive FIFO size register (OTG_GRXFSIZ).
The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in the receive RAM buffer:
The application keeps receiving the Rx FIFO non-empty interrupt (RXFLVL bit in OTG_GINTSTS) as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register (OTG_GRXSTSP) and finally pops data off the receive FIFO by reading from the endpoint-related pop address.
Peripheral Tx FIFOs
The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the endpoint 0 transmit FIFO size register (OTG_DIEPTXF0) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (OTG_DIEPTXFx) for IN endpoint-x.
| (omitted) |
Host Rx FIFO
The host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is used as a receive buffer to hold the received data (payload of the received packet) from the USB until it is transferred to the system memory. Packets received from any remote IN endpoint are stacked back-to-back until free space is available. The status of each received packet with the host channel destination, byte count, data PID and validity of the received data are also stored into the FIFO. The size of the receive FIFO is configured in the receive FIFO size register (OTG_GRXFSIZ).
The single receive FIFO architecture makes it highly efficient for the USB host to fill in the receive data buffer:
The application receives the Rx FIFO not-empty interrupt as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register and finally pops the data off the receive FIFO.
Host Tx FIFOs
The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the host periodic (nonperiodic) transmit FIFO size OTG_HPTXFSIZ / OTG_HNPTXFSIZ) register.
The two Tx FIFO implementation derives from the higher priority granted to the periodic type of traffic over the USB frame. At the beginning of each frame, the built-in host scheduler processes the periodic request queue first, followed by the nonperiodic request queue.
The two transmit FIFO architecture provides the USB host with separate optimization for periodic and nonperiodic transmit data buffer management:
The OTG_FS/OTG_HS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in OTG_GINTSTS) as long as the periodic Tx FIFO is half or completely empty, depending on the value of the periodic Tx FIFO empty level bit in the AHB configuration register (PTXFELVL bit in OTG_GAHBCFG). The application can push the transmission data in advance as long as free space is available in both the periodic Tx FIFO and the periodic request queue. The host periodic transmit FIFO and queue status register (OTG_HPTXSTS) can be read to know how much space is available in both.
OTG_FS/OTG_HS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty depending on the non periodic Tx FIFO empty level bit in the AHB configuration register (TXFELVL bit in OTG_GAHBCFG). The application can push the transmission data as long as free space is available in both the nonperiodic Tx FIFO and nonperiodic request queue. The host nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) can be read to know how much space is available in both.
Device mode
Receive FIFO RAM allocation: the application should allocate RAM for SETUP packets:
Device RxFIFO =
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
Example: The MPS is 1,024 bytes for a periodic USB packet and 512 bytes for a non-periodic USB packet. There are three OUT endpoints, three IN endpoints, one control endpoint, and three host channels.
Device RxFIFO = (5 * 1 + 8) + ((1,024 / 4) +1) + (2 * 4) + 1 = 279
Transmit FIFO RAM allocation: the minimum RAM space required for each IN endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint.
Note: More space allocated in the transmit IN endpoint FIFO results in better performance on the
USB.
Host mode
Receive FIFO RAM allocation:
Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (largest packet size / 4) + 1 must be allocated to receive packets. If multiple isochronous channels are enabled, then at least two (largest packet size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (largest packet size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet.
Along with the last packet in the host channel, transfer complete status information is also pushed to the FIFO. So one location must be allocated for this.
Host RxFIFO = (largest USB packet used / 4) + 1 for status information + 1 transfer complete
Example: Host RxFIFO = ((1,024 / 4) + 1) + 1 = 258
Transmit FIFO RAM allocation:
The minimum amount of RAM required for the host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels.
Typically, two largest packet sizes worth of space is recommended, so that when the current packet is under transfer to the USB, the CPU can get the next packet.
Non-Periodic TxFIFO = largest non-periodic USB packet used / 4
Example: Non-Periodic TxFIFO = (512 / 4) = 128
The minimum amount of RAM required for host periodic Transmit FIFO is the largest maximum packet size out of all the supported periodic OUT channels. If there is at least one isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel.
Host Periodic TxFIFO = largest periodic USB packet used / 4
Example: Host Periodic TxFIFO = (1,024 / 4) = 256
Note: More space allocated in the Transmit Non-periodic FIFO results in better performance on
the USB.
Best USB and system performance is achieved owing to the large RAM buffers, the highly configurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, especially, the advanced FIFO control mechanism. Indeed, this mechanism allows the OTG_FS to fill in the available RAM space at best regardless of the current USB sequence. With these features:
As the OTG_FS core is able to fill in the 1.25-Kbyte RAM buffer very efficiently, and as 1.25-Kbyte of transmit/receive data is more than enough to cover a full speed frame, the USB system is able to withstand the maximum full-speed data rate for up to one USB frame (1 ms) without any CPU intervention.
When the OTG_FS/OTG_HS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset.
Figure 518 shows the interrupt hierarchy.
| (omitted) |
By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS/OTG_HS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_FS/OTG_HS registers must be accessed by words (32 bits).
CSRs are classified as follows:
Only the core global, power and clock-gating, data FIFO access, and host port control and status registers can be accessed in both host and device modes. When the OTG_FS/OTG_HS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset.
The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain.
Global CSR map
These registers are available in both host and device modes.
| Acronym | Address offset | Register name |
|---|---|---|
| OTG_GOTGCTL | 0x000 |
Section 41.15.1: OTG control and status register (OTG_GOTGCTL)
|
| OTG_GOTGINT | 0x004 |
Section 41.15.2: OTG interrupt register (OTG_GOTGINT)
|
| OTG_GAHBCFG | 0x008 |
Section 41.15.3: OTG AHB configuration register (OTG_GAHBCFG)
|
| OTG_GUSBCFG | 0x00C |
Section 41.15.4: OTG USB configuration register (OTG_GUSBCFG)
|
| OTG_GRSTCTL | 0x010 |
Section 41.15.5: OTG reset register (OTG_GRSTCTL)
|
| OTG_GINTSTS | 0x014 |
Section 41.15.6: OTG core interrupt register (OTG_GINTSTS)
|
| OTG_GINTMSK | 0x018 | Section 41.15.7: OTG interrupt mask register (OTG_GINTMSK) |
| OTG_GRXSTSR | 0x01C |
Section 41.15.8: OTG receive status debug read/OTG status read and pop
registers (OTG_GRXSTSR/OTG_GRXSTSP) |
| OTG_GRXSTSP | 0x020 |
|
| OTG_GRXFSIZ | 0x024 |
Section 41.15.9: OTG receive FIFO size register (OTG_GRXFSIZ)
|
| OTG_HNPTXFSIZ/ OTG_DIEPTXF0(1) | 0x028 |
Section 41.15.10: OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) |
| OTG_HNPTXSTS | 0x02C |
Section 41.15.11: OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) |
| OTG_GCCFG | 0x038 |
Section 41.15.12: OTG general core configuration register (OTG_GCCFG)
|
| OTG_CID | 0x03C |
Section 41.15.13: OTG core ID register (OTG_CID)
|
| OTG_GLPMCFG | 0x54 |
Section 41.15.14: OTG core LPM configuration register (OTG_GLPMCFG)
|
| OTG_HPTXFSIZ | 0x100 |
Section 41.15.15: OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) |
| OTG_DIEPTXFx |
0x104 0x108 ... 0x114 |
Section 41.15.16: OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO number) for USB_OTG FS |
| OTG_DIEPTXFx |
0x104 0x108 ... 0x120 |
Section 41.15.16: OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO number) for USB_OTG HS |
Host-mode CSR map
These registers must be programmed every time the core changes to host mode.
| Acronym | Offset address | Register name |
|---|---|---|
| OTG_HCFG | 0x400 |
Section 41.15.18: OTG host configuration register (OTG_HCFG)
|
| OTG_HFIR | 0x404 |
Section 41.15.19: OTG host frame interval register (OTG_HFIR)
|
| OTG_HFNUM | 0x408 |
Section 41.15.20: OTG host frame number/frame time remaining register
(OTG_HFNUM) |
| OTG_HPTXSTS | 0x410 |
Section 41.15.21: OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) |
| OTG_HAINT | 0x414 |
Section 41.15.22: OTG host all channels interrupt register (OTG_HAINT)
|
| OTG_HAINTMSK | 0x418 |
Section 41.15.23: OTG host all channels interrupt mask register
(OTG_HAINTMSK) |
| OTG_HPRT | 0x440 |
Section 41.15.24: OTG host port control and status register (OTG_HPRT)
|
| OTG_HCCHARx |
0x500 0x520 ... 0x660 |
Section 41.15.25: OTG host channel x characteristics register (OTG_HCCHARx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG FS |
| OTG_HCCHARx |
0x500 0x520 ... 0x6E0 |
Section 41.15.25: OTG host channel x characteristics register (OTG_HCCHARx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG HS |
| OTG_HCSPLTx |
0x504 0x524 .... 0x6E4 |
Section 41.15.26: OTG host channel x split control register
(OTG_HCSPLTx) (x = 0..15, where x = Channel number) |
| OTG_HCINTx |
0x508 0x528 .... 0x668 |
Section 41.15.27: OTG host channel x interrupt register (OTG_HCINTx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG FS |
| OTG_HCINTx |
0x508 0x528 .... 0x6E8 |
Section 41.15.27: OTG host channel x interrupt register (OTG_HCINTx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG HS |
| OTG_HCINTMSKx |
0x50C 0x52C .... 0x66C |
Section 41.15.28: OTG host channel x interrupt mask register (OTG_HCINTMSKx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG FS |
| OTG_HCINTMSKx |
0x50C 0x52C .... 0x6EC |
Section 41.15.28: OTG host channel x interrupt mask register (OTG_HCINTMSKx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG HS |
| OTG_HCTSIZx |
0x510 0x530 .... 0x670 |
Section 41.15.29: OTG host channel x transfer size register (OTG_HCTSIZx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG FS |
| OTG_HCTSIZx |
0x510 0x530 .... 0x6F0 |
Section 41.15.29: OTG host channel x transfer size register (OTG_HCTSIZx) (x = 0..15[HS] / 11[FS], where x = Channel number) for USB_OTG HS |
| OTG_HCDMAx |
0x514 0x534 .... 0x6F4 |
Section 41.15.30: OTG host channel x DMA address register
(OTG_HCDMAx) (x = 0..15, where x = Channel number) |
Device-mode CSR map
These registers must be programmed every time the core changes to device mode.
| Acronym | Offset address | Register name |
|---|---|---|
| OTG_DCFG | 0x800 |
Section 41.15.32: OTG device configuration register (OTG_DCFG)
|
| OTG_DCTL | 0x804 |
Section 41.15.33: OTG device control register (OTG_DCTL)
|
| OTG_DSTS | 0x808 |
Section 41.15.34: OTG device status register (OTG_DSTS)
|
| OTG_DIEPMSK | 0x810 |
Section 41.15.35: OTG device IN endpoint common interrupt mask
register (OTG_DIEPMSK) |
| OTG_DOEPMSK | 0x814 |
Section 41.15.36: OTG device OUT endpoint common interrupt mask
register (OTG_DOEPMSK) |
| OTG_DAINT | 0x818 |
Section 41.15.37: OTG device all endpoints interrupt register
(OTG_DAINT) |
| OTG_DAINTMSK | 0x81C |
Section 41.15.38: OTG all endpoints interrupt mask register
(OTG_DAINTMSK) |
| OTG_DVBUSDIS | 0x828 |
Section 41.15.39: OTG device VBUS discharge time register
(OTG_DVBUSDIS) |
| OTG_DVBUSPULSE | 0x82C |
Section 41.15.40: OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) |
| OTG_DTHRCTL | 0x830 |
Section 41.15.41: OTG device threshold control register
(OTG_DTHRCTL) |
| OTG_DIEPEMPMSK | 0x834 |
Section 41.15.42: OTG device IN endpoint FIFO empty interrupt mask
register (OTG_DIEPEMPMSK) |
| OTG_DEACHINT | 0x838 |
Section 41.15.43: OTG device each endpoint interrupt register
(OTG_DEACHINT) |
| OTG_DEACHINTMSK | 0x83C |
Section 41.15.44: OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) |
| OTG_HS_DIEPEACHM SK1 |
0x844 |
Section 41.15.45: OTG device each IN endpoint-1 interrupt mask
register (OTG_HS_DIEPEACHMSK1) |
| OTG_HS_DOEPEACHM SK1 |
0x884 |
Section 41.15.46: OTG device each OUT endpoint-1 interrupt mask
register (OTG_HS_DOEPEACHMSK1) |
| OTG_DIEPCTL0 | 0x900 | Section 41.15.47: OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) for USB_OTG FS |
| OTG_DIEPCTLx |
0x920 0x940 ... 0x9A0 |
Section 41.15.48: OTG device IN endpoint x control register (OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint number) for USB_OTG FS |
| OTG_DIEPCTLx |
0x900 0x920 ... 0xA00 |
Section 41.15.48: OTG device IN endpoint x control register (OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint number) for USB_OTG HS |
| OTG_DIEPINTx |
0x908 0x928 .... 0x988 |
Section 41.15.49: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number) for USB_OTG FS |
| OTG_DIEPINTx |
0x908 0x928 ... 0x9E8 |
Section 41.15.49: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number) for USB_OTG HS |
| OTG_DIEPTSIZ0 | 0x910 |
Section 41.15.50: OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) |
| OTG_DIEPDMAx |
0x914 0x934 ... 0x9F4 |
Section 41.15.51: OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) (x = 0..8, where x = endpoint number) |
| OTG_DTXFSTSx |
0x918 0x938 .... 0x998 |
Section 41.15.52: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint number) for USB_OTG FS |
| OTG_DTXFSTSx |
0x918 0x938 ..... 0x9F8 |
Section 41.15.52: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint number) for USB_OTG HS |
| OTG_DIEPTSIZx |
0x930 0x950 ... 0x9B0 |
Section 41.15.53: OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x = endpoint number) for USB_OTG FS |
| OTG_DIEPTSIZx |
0x930 0x950 ... 0x9F0 |
Section 41.15.53: OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x = endpoint number) for USB_OTG HS |
| OTG_DOEPCTL0 | 0xB00 |
Section 41.15.54: OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) |
| OTG_DOEPINTx |
0xB08 0xB28 ... 0xBA8 |
Section 41.15.55: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number) for USB_OTG FS |
| OTG_DOEPINTx |
0xB08 0XB28 ... 0xC08 |
Section 41.15.55: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number) for USB_OTG HS |
| OTG_DOEPTSIZ0 | 0xB10 |
Section 41.15.56: OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) |
| OTG_DOEPDMAx |
0xB14 0xB34 ... 0xC14 |
Section 41.15.57: OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) (x = 0..8, where x = endpoint number) |
| OTG_DOEPCTLx |
0xB20 0xB40 ... 0xBA0 |
Section 41.15.58: OTG device OUT endpoint x control register (OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number) for USB_OTG FS |
| OTG_DOEPCTLx |
0xB20 0xB40 ... 0xC00 |
Section 41.15.58: OTG device OUT endpoint x control register (OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number) for USB_OTG HS |
| OTG_DOEPTSIZx |
0xB30 0xB50 ... 0xBB0 |
Section 41.15.59: OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number) for USB_OTG FS |
| OTG_DOEPTSIZx |
0xB30 0xB50 .. 0xBF0 |
Section 41.15.59: OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number) for USB_OTG HS |
Data FIFO (DFIFO) access register map
These registers, available in both host and device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.
| FIFO access register section | Offset address | Access |
|---|---|---|
|
Device IN endpoint 0/Host OUT Channel 0: DFIFO write access Device OUT endpoint 0/Host IN Channel 0: DFIFO read access |
0x1000–0x1FFC |
w r |
|
Device IN endpoint 1/Host OUT Channel 1: DFIFO write access Device OUT endpoint 1/Host IN Channel 1: DFIFO read access |
0x2000–0x2FFC |
w r |
| ... | ... | ... |
|
Device IN endpoint x(1)/Host OUT Channel x(1): DFIFO write access Device OUT endpoint x(1)/Host IN Channel x(1): DFIFO read access |
0xX000–0xXFFC |
w r |
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device modes.
| Acronym | Offset address | Register name |
|---|---|---|
| OTG_PCGCCTL | 0xE00–0xE04 |
Section 41.15.60: OTG power and clock gating control
register (OTG_PCGCCTL) |
These registers are available in both host and device modes, and do not need to be reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
Address offset: 0x000
Reset value: 0x0001 0000
The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CUR MOD |
OTG VER |
BSVLD | ASVLD | DBCT | CID STS |
| r | rw | r | r | r | r |
||||||||||
| 15 14 13 12 11 10 9 8 7 6 | 5 | 4 3 2 1 0 |
|||||||||||||
| Res. | Res. | Res. | EHEN | DHNP EN |
HSHNP EN |
HNP RQ |
HNG SCS |
BVALO VAL |
BVALO EN |
AVALO VAL |
AVALO EN |
VBVAL OVAL |
VBVAL OEN |
SRQ | SRQ SCS |
| rw | rw | rw | rw | r | rw | rw | rw | rw | rw | rw | rw | r | |||
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | CURMOD: Current mode of operation |
|
Indicates the current mode (host or device). |
|
| Bit 20 | OTGVER: OTG version |
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Selects the OTG revision. |
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| Bit 19 | BSVLD: B-session valid |
|
Indicates the device mode transceiver status.
Only accessible in device mode.
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| Bit 18 | ASVLD: A-session valid |
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Indicates the host mode transceiver status.
Only accessible in host mode.
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| Bit 17 | DBCT: Long/short debounce time |
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Indicates the debounce time of a detected connection.
Only accessible in host mode.
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| Bit 16 | CIDSTS: Connector ID status |
|
Indicates the connector ID status on a connect event.
Accessible in both device and host modes.
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| Bits 15:13 | Reserved, must be kept at reset value. |
| Bit 12 | EHEN: Embedded host enable |
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It is used to select between OTG A device state machine and embedded host state machine. |
|
| Bit 11 | DHNPEN: Device HNP enabled |
|
The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host. Only accessible in device mode. |
|
| Bit 10 | HSHNPEN: host set HNP enable |
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The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device.
Only accessible in host mode.
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|
| Bit 9 | HNPRQ: HNP request |
|
The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared.
Only accessible in device mode.
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| Bit 8 | HNGSCS: Host negotiation success |
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The core sets this bit when host negotiation is successful. The core clears this bit when the HNP request (HNPRQ) bit in this register is set.
Only accessible in device mode.
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| Bit 7 | BVALOVAL: B-peripheral session valid override value. |
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This bit is used to set override value for Bvalid signal when BVALOEN bit is set.
Only accessible in device mode.
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| Bit 6 | BVALOEN: B-peripheral session valid override enable. |
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This bit is used to enable/disable the software to override the Bvalid signal using the BVALOVAL bit.
Only accessible in device mode.
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| Bit 5 | AVALOVAL: A-peripheral session valid override value. |
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This bit is used to set override value for Avalid signal when AVALOEN bit is set.
Only accessible in host mode.
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| Bit 4 | AVALOEN: A-peripheral session valid override enable. |
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This bit is used to enable/disable the software to override the Avalid signal using the AVALOVAL bit. Only accessible in host mode. |
|
| Bit 3 | VBVALOVAL: VBUS valid override value. |
|
This bit is used to set override value for vbusvalid signal when VBVALOEN bit is set.
Only accessible in host mode.
|
|
| Bit 2 | VBVALOEN: VBUS valid override enable. |
|
This bit is used to enable/disable the software to override the vbusvalid signal using the VBVALOVAL bit.
Only accessible in host mode.
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|
| Bit 1 | SRQ: Session request |
|
The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared.
Only accessible in device mode.
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|
| Bit 0 | SRQSCS: Session request success |
|
The core sets this bit when a session request initiation is successful.
Only accessible in device mode.
|
Address offset: 0x04
Reset value: 0x0000 0000
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ID CHNG |
DBC DNE |
ADTO CHG |
HNG DET |
Res. |
Res. | Res. | Res. | Res. | Res. | Res. | HNSS CHG |
SRSS CHG |
Res. | Res. | Res. | Res. | Res. | SEDET | Res. | Res. |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 |
rc_w1 | rc_w1 | rc_w1 |
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bit 20 | IDCHNG: |
|
This bit when set indicates that there is a change in the value of the ID input pin. |
|
| Bit 19 | DBCDNE: Debounce done |
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The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the OTG_GUSBCFG register (HNPCAP bit or SRPCAP bit in OTG_GUSBCFG, respectively).
Only accessible in host mode.
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| Bit 18 | ADTOCHG: A-device timeout change |
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The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect.
Accessible in both device and host modes.
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| Bit 17 | HNGDET: Host negotiation detected |
|
The core sets this bit when it detects a host negotiation request on the USB.
Accessible in both device and host modes.
|
|
| Bits 16:10 | Reserved, must be kept at reset value. |
| Bit 9 | HNSSCHG: Host negotiation success status change |
|
The core sets this bit on the success or failure of a USB host negotiation request. The application must read the host negotiation success bit of the OTG_GOTGCTL register (HNGSCS bit in OTG_GOTGCTL) to check for success or failure.
Accessible in both device and host modes.
|
|
| Bits 7:3 | Reserved, must be kept at reset value. |
| Bit 8 | SRSSCHG: Session request success status change |
|
The core sets this bit on the success or failure of a session request. The application must read the session request success bit in the OTG_GOTGCTL register (SRQSCS bit in OTG_GOTGCTL) to check for success or failure.
Accessible in both device and host modes.
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|
| Bit 2 | SEDET: Session end detected |
|
The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V.
Accessible in both device and host modes.
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| Bits 1:0 | Reserved, must be kept at reset value. |
Address offset: 0x008
Reset value: 0x0000 0000
This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | PTXFE LVL |
TXFE LVL |
Res. | Res. | Res. | Res. | Res. | Res. | GINT MSK |
| rw | rw | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | PTXFE LVL |
TXFE LVL |
Res. | DMAEN | HBSTLEN[3:0] | GINT MSK |
|||
| rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||||
Note: Configuration register for USB OTG HS
| Bits 31:9 | Reserved, must be kept at reset value. |
| Bit 8 | PTXFELVL: Periodic Tx FIFO empty level |
|
Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered.
Only accessible in host mode.
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| Bit 7 | TXFELVL: Tx FIFO empty level |
|
In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered: |
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| Bits 6:1 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 6 | Reserved, must be kept at reset value for USB OTG HS. |
| Bit 5 | DMAEN: DMA enabled for USB OTG HS |
|
0: The core operates in slave mode |
|
| Bits 4:1 | HBSTLEN[3:0]: Burst length/type for USB OTG HS |
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0000 Single: Bus transactions use single 32 bit accesses (not recommended) 0111 INCR16: Bus transactions based on 16x 32 bit accesses |
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| Bit 0 | GINTMSK: Global interrupt mask |
|
The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit’s setting, the interrupt status registers are updated by the core. Accessible in both device and host modes. |
Address offset: 0x00C
Reset value: 0x0000 1440 for USB OTG FS
Reset value: 0x0000 1400 for USB OTG HS
This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 12 11 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 1 0 |
| Res. | FD MOD |
FH MOD |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | TRDT | HNP CAP |
SRP CAP |
Res. | PHY SEL |
Res. | Res. | Res. | TOCAL |
| rw | rw |
rw | rw | rw | r | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | FD MOD |
FH MOD |
Res. | Res. | Res. | ULPI IPD |
PTCI | PCCI | TSDPS | ULPIE VBUSI |
ULPIE VBUSD |
ULPI CSM |
ULPI AR |
ULPI FSL |
Res. |
PHYL PC |
Res. | TRDT[3:0] | HNP CAP |
SRP CAP |
Res. | PHY SEL |
Res. | Res. | Res. | TOCAL[2:0] |
|||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
Note: Configuration register for USB OTG HS
| Bit 31 | Reserved, must be kept at reset value. |
| Bit 30 | FDMOD: Force device mode |
|
Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin.
Accessible in both device and host modes.
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| Bit 29 | FHMOD: Force host mode |
|
Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin.
Accessible in both device and host modes.
|
|
| Bits 28:26 | Reserved, must be kept at reset value. |
| Bit 25 | ULPIIPD: ULPI interface protect disable for USB OTG HS |
|
This bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri- |
|
| Bit 24 | PTCI: Indicator pass through for USB OTG HS |
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This bit controls whether the complement output is qualified with the internal VBUS valid comparator before being used in the VBUS state in the RX CMD. Refer to the ULPI specification for more details. |
|
| Bit 23 | PCCI: Indicator complement for USB OTG HS |
|
This bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the complement output. Refer to the ULPI specification for more details. |
|
| Bit 22 | TSDPS: TermSel DLine pulsing selection for USB OTG HS |
|
This bit selects utmi_termselect to drive the data line pulse during SRP (session request protocol). |
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| Bit 21 | ULPIEVBUSI: ULPI external VBUS indicator for USB OTG HS |
|
This bit indicates to the ULPI PHY to use an external VBUS overcurrent indicator. |
|
| Bit 20 | ULPIEVBUSD: ULPI External VBUS Drive for USB OTG HS |
|
This bit selects between internal or external supply to drive 5 V on VBUS, in the ULPI PHY. |
|
| Bit 19 | ULPICSM: ULPI clock SuspendM for USB OTG HS |
|
This bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit applies only in the serial and carkit modes. |
|
| Bit 18 | ULPIAR: ULPI Auto-resume for USB OTG HS |
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This bit sets the AutoResume bit in the interface control register on the ULPI PHY. |
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| Bit 17 | ULPIFSLS: ULPI FS/LS select for USB OTG HS |
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The application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is valid only when the FS serial transceiver is selected on the ULPI PHY. 0: ULPI interface |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bit 15 | PHYLPC: PHY Low-power clock select for USB OTG HS |
|
This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power. |
|
| Bit 14 | Reserved, must be kept at reset value. |
| Bits 13:10 | TRDT[3:0]: USB turnaround time |
|
These bits allows to set the turnaround time in PHY clocks. They must be configured according to Table 296: TRDT values (FS) or Table 297: TRDT values (HS), depending on the application AHB frequency. Higher TRDT values allow stretching the USB response time to IN tokens in order to compensate for longer AHB read access latency to the data FIFO.
Only accessible in device mode.
|
|
| Bit 9 | HNPCAP: HNP-capable |
|
The application uses this bit to control the OTG_FS/OTG_HS controller’s HNP capabilities.
Accessible in both device and host modes.
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|
| Bit 8 | SRPCAP: SRP-capable |
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The application uses this bit to control the OTG_FS/OTG_HS controller’s SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session.
Accessible in both device and host modes.
|
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | PHYSEL: Full Speed serial transceiver select for USB OTG FS |
|
This bit is always 1 with read-only access. |
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| Bit 6 | PHYSEL: Full speed serial transceiver select for USB OTG HS |
|
0: USB 2.0 external ULPI high-speed PHY. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | Reserved, must be kept at reset value. |
| Bit 3 | Reserved, must be kept at reset value. |
| Bits 2:0 | TOCAL[2:0]: FS timeout calibration |
|
The number of PHY clocks that the application programs in this field is added to the full- |
| AHB frequency range (MHz) |
TRDT minimum value |
|
|---|---|---|
| Min | Max |
|
| 14.2 | 15 | 0xF |
| 15 | 16 | 0xE |
| 16 | 17.2 | 0xD |
| 17.2 | 18.5 | 0xC |
| 18.5 | 20 | 0xB |
| 20 | 21.8 | 0xA |
| 21.8 | 24 | 0x9 |
| 24 | 27.5 | 0x8 |
| 27.5 | 32 | 0x7 |
| 32 | - | 0x6 |
| AHB frequency range (MHz) |
TRDT minimum value |
|
|---|---|---|
| Min | Max |
|
| 30 | - | 0x9 |
Address offset: 0x10
Reset value: 0x8000 0000
The application uses this register to reset various hardware features inside the core.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 9 8 7 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AHB IDL |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | TXFNUM | TXF FLSH |
RXF FLSH |
Res. | FCRST | PSRST | CSRST |
| r | r |
rw | rs | rs | rs | rs | r |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AHB IDL |
DMAR EQ |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | TXFNUM[4:0] | TXF FLSH |
RXF FLSH |
Res. | Res. | PSRST | CSRST |
||||
| r | r |
rw | rw | rw | rw | rw | rs | rs | rs | rs |
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Note: Configuration register for USB OTG HS
| Bit 31 | AHBIDL: AHB master idle |
|
Indicates that the AHB master state machine is in the Idle condition.
Accessible in both device and host modes.
|
|
| Bits 30:11 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 30 | DMAREQ: DMA request signal enabled for USB OTG HS |
|
This bit indicates that the DMA request is in progress. Used for debug. |
|
| Bits 29:11 | Reserved, must be kept at reset value for USB OTG HS. |
| Bits 10:6 | TXFNUM[4:0]: Tx FIFO number |
|
This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not be changed until the core clears the Tx FIFO Flush bit.
...
Accessible in both device and host modes.
|
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| Bit 5 | TXFFLSH: Tx FIFO flush |
|
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. Accessible in both device and host modes. |
|
| Bit 4 | RXFFLSH: Rx FIFO flush |
|
The application can flush the entire Rx FIFO using this bit, but must first ensure that the core is not in the middle of a transaction.
Accessible in both device and host modes.
|
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bit 2 | FCRST: Host frame counter reset for USB OTG FS |
|
The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0.
Only accessible in host mode.
|
|
| Bit 2 | Reserved, must be kept at reset value for USB OTG HS. |
| Bit 1 | PSRST: Partial soft reset |
|
Resets the internal state machines but keeps the enumeration info. Could be used to recover some specific PHY errors.
Accessible in both device and host modes.
|
|
| Bit 0 | CSRST: Core soft reset |
|
Resets the HCLK and PHY clock domains as follows:
All module state machines (except for the AHB slave unit) are reset to the Idle state, and all the transmit FIFOs and the receive FIFO are flushed. Accessible in both device and host modes. |
Address offset: 0x014
Reset value: 0x1400 0020
This register interrupts the application for system-level events in the current mode (device mode or host mode).
Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit.
The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WKUP INT |
SRQ INT |
DISC INT |
CIDS CHG |
LPM INT |
PTXFE | HCINT | HPRT INT |
RST DET |
Res. |
IPXFR/ IN COMP ISO OUT |
IISOI XFR |
OEP INT |
IEPINT | Res. | Res. |
EOPF | ISOO DRP |
ENUM DNE |
USB RST |
USB SUSP |
ESUSP | Res. | Res. |
GO NAK EFF |
GI NAK EFF |
NPTXF E |
RXF LVL |
SOF | OTG INT |
MMIS | CMOD |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | r | r | r | rc_w1 | rc_w1 | rc_w1 | r | r |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | r | r | r | r | rc_w1 | r | rc_w1 | r |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WKUP INT |
SRQ INT |
DISC INT |
CIDS CHG |
Res. | PTXFE | HCINT | HPRT INT |
Res. | DATAF SUSP |
IPXFR/ IN COMP ISO OUT |
IISOI XFR |
OEP INT |
IEPINT | Res. | Res. |
EOPF | ISOO DRP |
ENUM DNE |
USB RST |
USB SUSP |
ESUSP | Res. | Res. |
GO NAK EFF |
GI NAK EFF |
NPTXF E |
RXF LVL |
SOF | OTG INT |
MMIS | CMOD |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | r | r | r | rc_w1 | rc_w1 | rc_w1 | r | r |
rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | r | r | r | r | rc_w1 | r | rc_w1 | r |
Note: Configuration register for USB OTG HS
| Bit 31 | WKUPINT: Resume/remote wakeup detected interrupt |
|
Wakeup interrupt during suspend(L2) or LPM(L1) state.
|
|
| Bit 30 | SRQINT: Session request/new session detected interrupt |
|
In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. |
|
| Bit 29 | DISCINT: Disconnect detected interrupt |
|
Asserted when a device disconnect is detected.
Only accessible in host mode.
|
|
| Bit 28 | CIDSCHG: Connector ID status change |
|
The core sets this bit when there is a change in connector ID status.
Accessible in both device and host modes.
|
|
| Bit 27 | LPMINT: LPM interrupt |
|
In device mode, this interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. |
|
| Bit 27 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 26 | PTXFE: Periodic Tx FIFO empty |
|
Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG).
Only accessible in host mode.
|
|
| Bit 25 | HCINT: Host channels interrupt |
|
The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit.
Only accessible in host mode.
|
|
| Bit 24 | HPRTINT: Host port interrupt |
|
The core sets this bit to indicate a change in port status of one of the OTG_FS/OTG_HS controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. Only accessible in host mode. |
|
| Bit 23 | RSTDET: Reset detected interrupt |
|
In device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in suspend.
Only accessible in device mode.
|
|
| Bit 23 | Reserved, must be kept at reset value for USB OTG HS. |
| Bit 22 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 22 | DATAFSUSP: Data fetch suspended for USB OTG HS |
|
This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue space. This interrupt is used by the application for an endpoint mismatch algorithm. For example, after detecting an endpoint mismatch, the application:
cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an “IN token received when FIFO empty” interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the “IN token received when FIFO empty” interrupt when clearing a global IN NAK handshake. |
|
| Bit 21 | IPXFR: Incomplete periodic transfer |
|
In host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. INCOMPISOOUT: Incomplete isochronous OUT transfer In device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. |
|
| Bit 20 | IISOIXFR: Incomplete isochronous IN transfer |
|
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register.
Only accessible in device mode.
|
|
| Bit 19 | OEPINT: OUT endpoint interrupt |
|
The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. Only accessible in device mode. |
|
| Bit 18 | IEPINT: IN endpoint interrupt |
|
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit.
Only accessible in device mode.
|
|
| Bits 17:16 | Reserved, must be kept at reset value. |
| Bit 15 | EOPF: End of periodic frame interrupt |
|
Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame.
Only accessible in device mode.
|
|
| Bit 14 | ISOODRP: Isochronous OUT packet dropped interrupt |
|
The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint.
Only accessible in device mode.
|
|
| Bit 13 | ENUMDNE: Enumeration done |
|
The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed.
Only accessible in device mode.
|
|
| Bit 12 | USBRST: USB reset |
|
The core sets this bit to indicate that a reset is detected on the USB.
Only accessible in device mode.
|
|
| Bit 11 | USBSUSP: USB suspend |
|
The core sets this bit to indicate that a suspend was detected on the USB. The core enters the suspended state when there is no activity on the data lines for an extended period of time.
Only accessible in device mode.
|
|
| Bit 10 | ESUSP: Early suspend |
|
The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
Only accessible in device mode.
|
|
| Bits 9:8 | Reserved, must be kept at reset value. |
| Bit 7 | GONAKEFF: Global OUT NAK effective |
|
Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). Only accessible in device mode. |
|
| Bit 6 | GINAKEFF: Global IN non-periodic NAK effective |
|
Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL).
Only accessible in device mode.
|
|
| Bit 5 | NPTXFE: Non-periodic Tx FIFO empty |
|
This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG).
Accessible in host mode only.
|
|
| Bit 4 | RXFLVL: Rx FIFO non-empty |
|
Indicates that there is at least one packet pending to be read from the Rx FIFO.
Accessible in both host and device modes.
|
|
| Bit 3 | SOF: Start of frame |
|
In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. This register may return '1' if read immediately after power on reset. If the register bit Accessible in both host and device modes. |
|
| Bit 2 | OTGINT: OTG interrupt |
|
The core sets this bit to indicate an OTG protocol event. The application must read the OTG interrupt status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit.
Accessible in both host and device modes.
|
|
| Bit 1 | MMIS: Mode mismatch interrupt |
|
The core sets this bit when the application is trying to access:
|
|
| Bit 0 | CMOD: Current mode of operation |
|
Indicates the current mode. Accessible in both host and device modes. |
Address offset: 0x018
Reset value: 0x0000 0000
This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WUIM | SRQIM | DISCIN T |
CIDSC HGM |
LPMIN TM |
PTXFE M |
HCIM | PRTIM | RSTDE TM |
Res. |
IPXFR M/IISO OXFR M |
IISOIX FRM |
OEPIN T |
IEPINT | Res. | Res. |
EOPF M |
ISOOD RPM |
ENUM DNEM |
USBRS T |
USBSU SPM |
ESUSP M |
Res. | Res. | GONA KEFFM |
GINAK EFFM |
NPTXF EM |
RXFLV LM |
SOFM | OTGIN T |
MMISM | Res. |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WUIM | SRQIM | DISCIN T |
CIDSC HGM |
LPMIN TM |
PTXFE M |
HCIM | PRTIM | RSTDE TM |
FSUS PM |
IPXFR M/IISO OXFR M |
IISOIX FRM |
OEPIN T |
IEPINT | Res. | Res. |
EOPF M |
ISOOD RPM |
ENUM DNEM |
USBRS T |
USBSU SPM |
ESUSP M |
Res. | Res. | GONA KEFFM |
GINAK EFFM |
NPTXF EM |
RXFLV LM |
SOFM | OTGIN T |
MMISM | Res. |
| rw | rw | rw | rw | rw | rw | rw | r | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG HS
| Bit 31 | WUIM: Resume/remote wakeup detected interrupt mask |
|
0: Masked interrupt
Accessible in both host and device modes.
|
|
| Bit 30 | SRQIM: Session request/new session detected interrupt mask |
|
0: Masked interrupt
Accessible in both host and device modes.
|
|
| Bit 29 | DISCINT: Disconnect detected interrupt mask |
|
0: Masked interrupt
Only accessible in host mode.
|
|
| Bit 28 | CIDSCHGM: Connector ID status change mask |
|
0: Masked interrupt Accessible in both host and device modes. |
|
| Bit 27 | LPMINTM: LPM interrupt mask |
|
0: Masked interrupt
Accessible in both host and device modes.
|
|
| Bit 26 | PTXFEM: Periodic Tx FIFO empty mask |
|
0: Masked interrupt
Only accessible in host mode.
|
|
| Bit 25 | HCIM: Host channels interrupt mask |
|
0: Masked interrupt
Only accessible in host mode.
|
|
| Bit 24 | PRTIM: Host port interrupt mask |
|
0: Masked interrupt
Only accessible in host mode.
|
|
| Bit 23 | RSTDETM: Reset detected interrupt mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 22 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 22 | FSUSPM: Data fetch suspended mask for USB OTG HS |
|
0: Masked interrupt Only accessible in peripheral mode. |
|
| Bit 21 | IPXFRM: Incomplete periodic transfer mask |
|
0: Masked interrupt
Only accessible in host mode.
IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 20 | IISOIXFRM: Incomplete isochronous IN transfer mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 19 | OEPINT: OUT endpoints interrupt mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 18 | IEPINT: IN endpoints interrupt mask |
|
0: Masked interrupt Only accessible in device mode. |
|
| Bits 17:16 | Reserved, must be kept at reset value. |
| Bit 15 | EOPFM: End of periodic frame interrupt mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 14 | ISOODRPM: Isochronous OUT packet dropped interrupt mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 13 | ENUMDNEM: Enumeration done mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 12 | USBRST: USB reset mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 11 | USBSUSPM: USB suspend mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 10 | ESUSPM: Early suspend mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bits 9:8 | Reserved, must be kept at reset value. |
| Bit 7 | GONAKEFFM: Global OUT NAK effective mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 6 | GINAKEFFM: Global non-periodic IN NAK effective mask |
|
0: Masked interrupt
Only accessible in device mode.
|
|
| Bit 5 | NPTXFEM: Non-periodic Tx FIFO empty mask |
|
0: Masked interrupt
Only accessible in host mode.
|
|
| Bit 4 | RXFLVLM: Receive FIFO non-empty mask |
|
0: Masked interrupt Accessible in both device and host modes. |
|
| Bit 3 | SOFM: Start of frame mask |
|
0: Masked interrupt
Accessible in both device and host modes.
|
|
| Bit 2 | OTGINT: OTG interrupt mask |
|
0: Masked interrupt
Accessible in both device and host modes.
|
|
| Bit 1 | MMISM: Mode mismatch interrupt mask |
|
0: Masked interrupt
Accessible in both device and host modes.
|
|
| Bit 0 | Reserved, must be kept at reset value. |
Address offset for read: 0x01C
Address offset for pop: 0x020
Reset value: 0x0000 0000
A read to the receive status debug read register returns the contents of the top of the receive FIFO. A read to the receive status read and pop register additionally pops the top data entry out of the Rx FIFO.
The receive status contents must be interpreted differently in host and device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x0000 0000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKTSTS[3:0] | DPID |
DPID | BCNT[10:0] | CHNUM[3:0] |
||||||||||||||||
| r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | |||||||||||
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bits 20:17 | PKTSTS[3:0]: Packet status |
|
Indicates the status of the received packet |
|
| Bits 16:15 | DPID: Data PID |
|
Indicates the data PID of the received packet |
|
| Bits 14:4 | BCNT[10:0]: Byte count |
|
Indicates the byte count of the received IN data packet. |
|
| Bits 3:0 | CHNUM[3:0]: Channel number |
|
Indicates the channel number to which the current received packet belongs. |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | STSPH ST |
Res. | Res. | FRMNUM[3:0] | PKTSTS[3:0] | DPID[1] |
DPID[0] | BCNT[10:0] | EPNUM[3:0] |
|||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bit 27 | STSPHST: Status phase start |
|
Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern. |
|
| Bits 26:25 | Reserved, must be kept at reset value. |
| Bits 24:21 | FRMNUM[3:0]: Frame number |
|
This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. |
|
| Bits 20:17 | PKTSTS[3:0]: Packet status |
|
Indicates the status of the received packet |
|
| Bits 16:15 | DPID[1:0]: Data PID |
|
Indicates the data PID of the received OUT data packet |
|
| Bits 14:4 | BCNT[10:0]: Byte count |
|
Indicates the byte count of the received data packet. |
|
| Bits 3:0 | EPNUM[3:0]: Endpoint number |
|
Indicates the endpoint number to which the current received packet belongs. |
Address offset: 0x024
Reset value: 0x0000 0200 for USB OTG FS
Reset value: 0x0000 0400 for USB OTG HS
The application can program the RAM size that must be allocated to the Rx FIFO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
RXFD[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | RXFD[15:0]: Rx FIFO depth |
|
This value is in terms of 32-bit words. |
Address offset: 0x028
Reset value: 0x0200 0200
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NPTXFD/TX0FD[15:0] |
NPTXFSA/TX0FSA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Host mode
| Bits 31:16 | NPTXFD[15:0]: Non-periodic Tx FIFO depth |
|
This value is in terms of 32-bit words. |
|
| Bits 15:0 | NPTXFSA[15:0]: Non-periodic transmit RAM start address |
|
This field configures the memory start address for non-periodic transmit FIFO RAM. |
Device mode
| Bits 31:16 | TX0FD: Endpoint 0 Tx FIFO depth |
|
This value is in terms of 32-bit words. |
|
| Bits 15:0 | TX0FSA: Endpoint 0 transmit RAM start address |
|
This field configures the memory start address for the endpoint 0 transmit FIFO RAM. |
Address offset: 0x02C
Reset value: 0x0008 0200 for USB OTG FS
Reset value: 0x0008 0400 for USB OTG HS
Note: In device mode, this register is not valid.
This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | NPTXQTOP[6:0] | NPTQXSAV[7:0] |
NPTXFSAV[15:0] |
||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | |
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:24 | NPTXQTOP[6:0]: Top of the non-periodic transmit request queue |
|
Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Terminate (last entry for selected channel/endpoint) |
|
| Bits 23:16 | NPTQXSAV[7:0]: Non-periodic transmit request queue space available |
|
Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests. |
|
| Bits 15:0 | NPTXFSAV[15:0]: Non-periodic Tx FIFO space available |
|
Indicates the amount of free space available in the non-periodic Tx FIFO. |
Address offset: 0x038
Reset value: 0x0000 XXXX
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBDEN | SDEN | PDEN | DCD EN |
BCDEN | PWR DWN |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PS2 DET |
SDET | PDET | DCDET |
| rw | rw | rw | rw | rw | rw |
r | r | r | r |
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | VBDEN: USB VBUS detection enable |
|
Enables VBUS sensing comparators to detect VBUS valid levels on the VBUS PAD for USB host and device operation. If HNP and/or SRP support is enabled, VBUS comparators are automatically enabled independently of VBDEN value. |
|
| Bit 20 | SDEN: Secondary detection (SD) mode enable |
|
This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly |
|
| Bit 19 | PDEN: Primary detection (PD) mode enable |
|
This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. |
|
| Bit 18 | DCDEN: Data contact detection (DCD) mode enable |
|
This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. |
|
| Bit 17 | BCDEN: Battery charging detector (BCD) enable |
|
This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to ‘0’ in order to allow the normal USB operation. |
|
| Bit 16 | PWRDWN: Power down control |
|
Used to activate the transceiver in transmission/reception. When reset, the transceiver is kept in power-down. When set, the BCD function must be off (BCDEN=0). |
|
| Bits 15:4 | Reserved, must be kept at reset value. |
| Bit 3 | PS2DET: DM pull-up detection status |
|
This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. |
|
| Bit 2 | SDET: Secondary detection (SD) status |
|
This bit gives the result of SD. |
|
| Bit 1 | PDET: Primary detection (PD) status |
|
This bit gives the result of PD. |
|
| Bit 0 | DCDET: Data contact detection (DCD) status |
|
This bit gives the result of DCD. |
Address offset: 0x03C
Reset value: 0x0000 2000 for USB OTG FS
Reset value: 0x0000 2100 for USB OTG HS
This is a register containing the Product ID as reset value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRODUCT_ID[31:16] |
PRODUCT_ID[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | PRODUCT_ID[31:0]: Product ID field |
|
Application-programmable ID field. |
Address offset: 0x54
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | EN BESL |
LPMRCNTSTS[2:0] | SND LPM |
LPMRCNT[2:0] | LPMCHIDX[3:0] | L1RSM OK |
SLP STS |
LPMRSP[1:0] | L1DS EN |
BESLTHRS[3:0] | L1SS EN |
REM WAKE |
BESL[3:0] | LPM ACK |
LPM EN |
||||||||||||||
| rw | r | r | r | rs | rw | rw | rw | rw | rw | rw | rw | r |
r | r | r | rw | rw | rw | rw | rw | rw | rw/r | rw/r | rw/r | rw/r | rw/r | rw | rw |
|||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bit 28 | ENBESL: Enable best effort service latency |
|
This bit enables the BESL feature as defined in the LPM errata: Only the updated behavior (described in LPM Errata) is considered in this document |
|
| Bits 27:25 | LPMRCNTSTS[2:0]: LPM retry count status |
|
Number of LPM host retries still remaining to be transmitted for the current LPM sequence. Accessible only in host mode. |
|
| Bit 24 | SNDLPM: Send LPM transaction |
|
When the application software sets this bit, an LPM transaction containing two tokens, EXT and LPM is sent. The hardware clears this bit once a valid response (STALL, NYET, or ACK) is received from the device or the core has finished transmitting the programmed number of LPM retries.
This bit must be set only when the host is connected to a local port.
Accessible only in host mode.
|
|
| Bits 23:21 | LPMRCNT:[2:0] LPM retry count |
|
When the device gives an ERROR response, this is the number of additional LPM retries that the host performs until a valid device response (STALL, NYET, or ACK) is received.
Accessible only in host mode.
|
|
| Bits 20:17 | LPMCHIDX[3:0]: LPM Channel Index |
|
The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. Based on the LPM channel index, the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction.
Accessible only in host mode.
|
|
| Bit 16 | L1RSMOK: Sleep state resume OK |
|
Indicates that the device or host can start resume from Sleep state. This bit is valid in LPM sleep (L1) state. It is set in sleep mode after a delay of 50 μs (TL1Residency). |
|
| Bit 15 | SLPSTS: Port sleep status |
|
Device mode:
Host mode:
0: Core not in L1 |
|
| Bits 14:13 | LPMRST[1:0]: LPM response |
|
Device mode: |
|
| Bit 12 | L1DSEN: L1 deep sleep enable |
|
Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. |
|
| Bits 11:8 | BESLTHRS[3:0]: BESL threshold |
|
Device mode: |
|
| Bit 7 | L1SSEN: L1 Shallow Sleep enable |
|
Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. |
|
| Bit 6 | REMWAKE: bRemoteWake value |
|
Host mode: |
|
| Bits 5:2 | BESL[3:0]: Best effort service latency |
|
Host mode: |
|
| Bit 1 | LPMACK: LPM token acknowledge enable |
|
Handshake response to LPM token preprogrammed by device application software.
0: NYET
|
|
| Bit 0 | LPMEN: LPM support enable |
|
The application uses this bit to control the OTG_FS/OTG_HS core LPM capabilities. |
Address offset: 0x100
Reset value: 0x0200 0400
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PTXFSIZ[15:0] |
PTXSA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | PTXFSIZ[15:0]: Host periodic Tx FIFO depth |
|
This value is in terms of 32-bit words. |
|
| Bits 15:0 | PTXSA[15:0]: Host periodic Tx FIFO start address |
|
This field configures the memory start address for periodic transmit FIFO RAM. |
Address offset: 0x104 + (x – 1) * 0x04
Reset value: 0x0200 0200 + (x * 0x200)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INEPTXFD[15:0] |
INEPTXSA[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | INEPTXFD[15:0]: IN endpoint Tx FIFO depth |
|
This value is in terms of 32-bit words. |
|
| Bits 15:0 | INEPTXSA[15:0]: IN endpoint FIFOx transmit RAM start address |
|
This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. |
Bit values in the register descriptions are expressed in binary unless otherwise specified.
Host-mode registers affect the operation of the core in the host mode. Host mode registers must not be accessed in device mode, as the results are undefined. Host mode registers can be categorized as follows:
Address offset: 0x400
Reset value: 0x0000 0000
This register configures the core after power-on. Do not make changes to this register after initializing the host.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSLSS | FSLSPCS[1:0] |
||
| r | rw | rw |
|||||||||||||||||||||||||||||
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | FSLSS: FS- and LS-only support |
|
The application uses this bit to control the core’s enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. |
|
| Bits 1:0 | FSLSPCS[1:0]: FS/LS PHY clock select |
|
When the core is in FS host mode The FSLSPCS must be set on a connection event according to the speed of the |
Address offset: 0x404
Reset value: 0x0000 EA60
This register stores the frame interval information for the current speed to which the OTG_FS/OTG_HS controller has enumerated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RLD CTRL |
FRIVL[15:0] |
|||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | RLDCTRL: Reload control |
|
This bit allows dynamic reloading of the HFIR register during run time. 0: The HFIR can be dynamically reloaded during run time. RLDCTRL = 1 is not recommended. |
|
| Bits 15:0 | FRIVL[15:0]: Frame interval for USB OTG FS |
|
The value that the application programs to this field, specifies the interval between two consecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the port enable bit of the host port control and status register (PENA bit in OTG_HPRT) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY clock select field of the host configuration register (FSLSPCS in OTG_HCFG). Do not change the value of this field after the initial configuration, unless the RLDCTRL bit is set. In such case, the FRIVL is reloaded with each SOF event.
|
|
| Bits 15:0 | FRIVL[15:0]: Frame interval for USB OTG HS |
|
The value that the application programs to this field, specifies the interval between two consecutive micro-SOFs (HS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the port enable bit of the host port control and status register (PENA bit in OTG_HPRT) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY clock select field of the host configuration register (FSLSPCS in OTG_HCFG). Do not change the value of this field after the initial configuration, unless the RLDCTRL bit is set. In such case, the FRIVL is reloaded with each SOF event.
|
Address offset: 0x408
Reset value: 0x0000 3FFF
This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FTREM[15:0] |
FRNUM[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | FTREM[15:0]: Frame time remaining |
|
Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB. |
|
| Bits 15:0 | FRNUM[15:0]: Frame number |
|
This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when it reaches 0x3FFF. |
Address offset: 0x410
Reset value: 0x0008 0100
This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PTXQTOP[7:0] | PTXQSAV[7:0] |
PTXFSAVL[15:0] |
|||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:24 | PTXQTOP[7:0]: Top of the periodic transmit request queue |
|
This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. Odd/Even frame 1: send in odd frame Terminate (last entry for the selected channel/endpoint) |
|
| Bits 23:16 | PTXQSAV[7:0]: Periodic transmit request queue space available |
|
Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. |
|
| Bits 15:0 | PTXFSAVL[15:0]: Periodic transmit data FIFO space available |
|
Indicates the number of free locations available to be written to in the periodic Tx FIFO. |
Address offset: 0x414
Reset value: 0x0000 0000
When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure 518. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
HAINT[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | HAINT[15:0]: Channel interrupts |
|
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 |
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
HAINTM[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | HAINTM[15:0]: Channel interrupt mask |
|
0: Masked interrupt |
Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in host mode. Currently, the OTG host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure 518. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSPD[1:0] | PTCTL [3] |
PTCTL[2:0] | PPWR | PLSTS[1:0] | Res. | PRST | PSUSP | PRES | POC CHNG |
POCA | PEN CHNG |
PENA | PCDET | PCSTS |
||||
| r | r | rw |
rw | rw | rw | rw | r | r | rw | rs | rw | rc_w1 | r | rc_w1 | rc_w1 | rc_w1 | r |
||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bits 18:17 | PSPD[1:0]: Port speed |
|
Indicates the speed of the device attached to this port. |
|
| Bits 16:13 | PTCTL[3:0]: Port test control |
|
The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. |
|
| Bit 12 | PPWR: Port power |
|
The application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. |
|
| Bits 11:10 | PLSTS[1:0]: Port line status |
|
Indicates the current logic level USB data lines Logic level of OTG_DP Logic level of OTG_DM |
|
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | PRST: Port reset |
|
When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. |
|
| Bit 7 | PSUSP: Port suspend |
|
The application sets this bit to put this port in suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set the port clock stop bit, which asserts the suspend input pin of the PHY. |
|
| Bit 6 | PRES: Port resume |
|
The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit.
|
|
| Bit 5 | POCCHNG: Port overcurrent change |
|
The core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. |
|
| Bit 4 | POCA: Port overcurrent active |
|
Indicates the overcurrent condition of the port. |
|
| Bit 3 | PENCHNG: Port enable/disable change |
|
The core sets this bit when the status of the port enable bit 2 in this register changes. |
|
| Bit 2 | PENA: Port enable |
|
A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port. This bit does not trigger any interrupt to the application. |
|
| Bit 1 | PCDET: Port connect detected |
|
The core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit in the core interrupt register (HPRTINT bit in OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt. |
|
| Bit 0 | PCSTS: Port connect status |
|
0: No device is attached to the port |
Address offset: 0x500 + (x * 0x20)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHENA | CHDIS | ODD FRM |
DAD[6:0] | MCNT[1:0] | EPTYP[1:0] | LSDEV | Res. |
EPDIR | EPNUM[3:0] | MPSIZ[10:0] |
|||||||||||||||||||||
| rs | rs | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|
| Bit 31 | CHENA: Channel enable |
|
This field is set by the application and cleared by the OTG host. 0: Channel disabled |
|
| Bit 30 | CHDIS: Channel disable |
|
The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. |
|
| Bit 29 | ODDFRM: Odd frame |
|
This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. |
|
| Bits 28:22 | DAD[6:0]: Device address |
|
This field selects the specific device serving as the data source or sink. |
|
| Bits 21:20 | MCNT[1:0]: Multicount |
|
This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used
This field must be set to at least 01.
|
|
| Bits 19:18 | EPTYP[1:0]: Endpoint type |
|
Indicates the transfer type selected. |
|
| Bit 17 | LSDEV: Low-speed device |
|
This field is set by the application to indicate that this channel is communicating to a low- |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bit 15 | EPDIR: Endpoint direction |
|
Indicates whether the transaction is IN or OUT. |
|
| Bits 14:11 | EPNUM[3:0]: Endpoint number |
|
Indicates the endpoint number on the device serving as the data source or sink. |
|
| Bits 10:0 | MPSIZ[10:0]: Maximum packet size |
|
Indicates the maximum packet size of the associated endpoint. |
Address offset: 0x504 + (x * 0x20)
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPLIT EN |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMP LSPLT |
XACTPOS[1:0] | HUBADDR[6:0] | PRTADDR[6:0] |
|||||||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||
| Bit 31 | SPLITEN: Split enable |
|
The application sets this bit to indicate that this channel is enabled to perform split transactions. |
|
| Bits 30:17 | Reserved, must be kept at reset value. |
| Bit 16 | COMPLSPLT: Do complete split |
|
The application sets this bit to request the OTG host to perform a complete split transaction. |
|
| Bits 15:14 | XACTPOS[1:0]: Transaction position |
|
This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. |
|
| Bits 13:7 | HUBADDR[6:0]: Hub address |
|
This field holds the device address of the transaction translator’s hub. |
|
| Bits 6:0 | PRTADDR[6:0]: Port address |
|
This field is the port number of the recipient transaction translator. |
Address offset: 0x508 + (x * 0x20)
Reset value: 0x0000 0000
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure 518. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | DTERR | FRM OR |
BBERR | TXERR | Res. | ACK | NAK | STALL | Res. | CHH | XFRC |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG FS.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | DTERR | FRM OR |
BBERR | TXERR | NYET | ACK | NAK | STALL | AHB ERR |
CHH | XFRC |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG HS.
| Bits 31:11 | Reserved, must be kept at reset value. |
| Bit 10 | DTERR: Data toggle error. |
| Bit 9 | FRMOR: Frame overrun. |
| Bit 8 | BBERR: Babble error. |
| Bit 7 | TXERR: Transaction error. |
|
Indicates one of the following errors occurred on the USB. |
|
| Bit 6 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 6 | NYET: Not yet ready response received interrupt for USB OTG HS. |
| Bit 5 | ACK: ACK response received/transmitted interrupt. |
| Bit 4 | NAK: NAK response received interrupt. |
| Bit 3 | STALL: STALL response received interrupt. |
| Bit 2 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 2 | AHBERR: AHB error for USB OTG HS |
|
This error is generated only in Internal DMA mode when an AHB error occurs during an AHB |
|
| Bit 1 | CHH: Channel halted. |
|
Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. |
|
| Bit 0 | XFRC: Transfer completed. |
|
Transfer completed normally without any errors. |
Address offset: 0x50C + (x * 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | DTERR M |
FRM ORM |
BBERR M |
TXERR M |
Res. | ACKM | NAKM | STALL M |
Res. | CHHM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | DTERR M |
FRM ORM |
BBERR M |
TXERR M |
NYET | ACKM | NAKM | STALL M |
AHB ERRM |
CHHM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG HS
| Bits 31:11 | Reserved, must be kept at reset value. |
| Bit 10 | DTERRM: Data toggle error mask. |
|
0: Masked interrupt |
|
| Bit 9 | FRMORM: Frame overrun mask. |
|
0: Masked interrupt |
|
| Bit 8 | BBERRM: Babble error mask. |
|
0: Masked interrupt |
|
| Bit 7 | TXERRM: Transaction error mask. |
|
0: Masked interrupt |
|
| Bit 6 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 6 | NYET: response received interrupt mask for USB OTG HS. |
|
0: Masked interrupt |
|
| Bit 5 | ACKM: ACK response received/transmitted interrupt mask. |
|
0: Masked interrupt |
|
| Bit 4 | NAKM: NAK response received interrupt mask. |
|
0: Masked interrupt |
|
| Bit 3 | STALLM: STALL response received interrupt mask. |
|
0: Masked interrupt |
|
| Bit 2 | AHBERRM: AHB error for USB OTG HS. |
|
0: Masked interrupt |
|
| Bit 2 | Reserved, must be kept at reset value for USB OTG FS. |
| Bit 1 | CHHM: Channel halted mask |
|
0: Masked interrupt |
|
| Bit 0 | XFRCM: Transfer completed mask |
|
0: Masked interrupt |
Address offset: 0x510 + (x * 0x20)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | DPID[1:0] | PKTCNT[9:0] | XFRSIZ[18:16] |
XFRSIZ[15:0] |
|||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:29 | DPID[1:0]: Data PID |
|
The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. |
|
| Bits 28:19 | PKTCNT[9:0]: Packet count |
|
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). |
|
| Bits 18:0 | XFRSIZ[18:0]: Transfer size |
|
For an OUT, this field is the number of data bytes the host sends during the transfer. |
Address offset: 0x514 + (x * 0x20)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMAADDR[31:16] |
DMAADDR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DMAADDR[31:0]: DMA address |
|
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. |
These registers must be programmed every time the core changes to device mode
Address offset: 0x800
Reset value: 0x0220 0000
This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
ERRAT IM |
Res. | Res. | PFIVL[1:0] | DAD[6:0] | Res. | NZLSO HSK |
DSPD[1:0] |
||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | PERSCHIVL[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
ERRAT IM |
XCVR DLY |
Res. | PFIVL[1:0] | DAD[6:0] | Res. | NZLSO HSK |
DSPD[1:0] |
|||||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
Note: Configuration register for USB OTG HS
| Bits 31:16 | Reserved, must be kept at reset value for USB OTG FS. |
| Bits 31:26 | Reserved, must be kept at reset value for USB OTG HS. |
| Bits 25:24 | PERSCHIVL[1:0]: Periodic schedule interval for USB OTG HS |
|
This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25, 50 or 75% of the (micro) frame.
00: 25% of (micro)frame |
|
| Bits 23:16 | Reserved, must be kept at reset value for USB OTG HS. |
| Bit 15 | ERRATIM: Erratic error interrupt mask |
|
1: Mask early suspend interrupt on erratic error |
|
| Bit 14 | XCVRDLY: Transceiver delay |
|
Enables or disables delay in ULPI timing during device chirp. |
|
| Bit 13 | Reserved, must be kept at reset value. |
| Bits 12:11 | PFIVL[1:0]: Periodic frame interval |
|
Indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. This can be used to determine if all the isochronous traffic for that frame is complete. |
|
| Bits 10:4 | DAD[6:0]: Device address |
|
The application must program this field after every SetAddress control command. |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bit 2 | NZLSOHSK: Non-zero-length status OUT handshake |
|
The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer’s status stage. |
|
| Bits 1:0 | DSPD[1:0]: Device speed |
|
Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. |
|
| Bits 1:0 | DSPD[1:0]: Device speed |
|
Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. |
Address offset: 0x804
Reset value: 0x0000 0002
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DS BESL RJCT |
Res. | Res. |
Res. | Res. | Res. | Res. |
PO PRG DNE |
CGO NAK |
SGO NAK |
CGI NAK |
SGI NAK |
TCTL[2:0] | GON STS |
GIN STS |
SDIS | RWU SIG |
||
| rw |
rw | w | w | w | w | rw | rw | rw | r | r | rw | rw |
|||||||||||||||||||
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bit 18 | DSBESLRJCT: Deep sleep BESL reject |
|
Core rejects LPM request with BESL value greater than BESL threshold programmed. NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By default, the deep sleep BESL reject feature is disabled. |
|
| Bits 17:12 | Reserved, must be kept at reset value. |
| Bit 11 | POPRGDNE: Power-on programming done |
|
The application uses this bit to indicate that register programming is completed after a wakeup from power down mode. |
|
| Bit 10 | CGONAK: Clear global OUT NAK |
|
Writing 1 to this field clears the Global OUT NAK. |
|
| Bit 9 | SGONAK: Set global OUT NAK |
|
Writing 1 to this field sets the Global OUT NAK. |
|
| Bit 8 | CGINAK: Clear global IN NAK |
|
Writing 1 to this field clears the Global IN NAK. |
|
| Bit 7 | SGINAK: Set global IN NAK |
|
Writing 1 to this field sets the Global non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. |
|
| Bits 6:4 | TCTL[2:0]: Test control |
|
000: Test mode disabled |
|
| Bit 3 | GONSTS: Global OUT NAK status |
|
0:A handshake is sent based on the FIFO status and the NAK and STALL bit settings. |
|
| Bit 2 | GINSTS: Global IN NAK status |
|
0:A handshake is sent out based on the data availability in the transmit FIFO. |
|
| Bit 1 | SDIS: Soft disconnect |
|
The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. |
|
| Bit 0 | RWUSIG: Remote wakeup signaling |
|
When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. |
Table 298 contains the minimum duration (according to device state) for which the Soft disconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is recommended that the application add some extra delay to the specified minimum duration.
| Operating speed | Device state | Minimum duration |
|---|---|---|
| Full speed | Suspended | 1 ms + 2.5 µs |
| Full speed | Idle | 2.5 µs |
| Full speed | Not Idle or suspended (Performing transactions) | 2.5 µs |
| High speed | Not Idle or suspended (Performing transactions) | 125 µs |
Address offset: 0x808
Reset value: 0x0000 0010
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DEVLNSTS[1:0] | FNSOF[13:8] |
FNSOF[7:0] | Res. | Res. | Res. | Res. | EERR | ENUMSPD[1:0] | SUSP STS |
||||||||||||||
| r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||
| Bits 31:24 | Reserved, must be kept at reset value. |
| Bits 23:22 | DEVLNSTS[1:0]: Device line status |
|
Indicates the current logic level USB data lines. |
|
| Bits 21:8 | FNSOF[13:0]: Frame number of the received SOF |
| Bits 7:4 | Reserved, must be kept at reset value. |
| Bit 3 | EERR: Erratic error |
|
The core sets this bit to report any erratic errors. |
|
| Bits 2:1 | ENUMSPD[1:0]: Enumerated speed |
|
Indicates the speed at which the OTG_FS/OTG_HS controller has come up after speed detection through a chirp sequence. |
|
| Bit 0 | SUSPSTS: Suspend status |
|
In device mode, this bit is set as long as a suspend condition is detected on the USB. The core enters the suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend:
|
Address offset: 0x810
Reset value: 0x0000 0000
This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | NAKM | Res. | Res. | Res. | Res. | TXFU RM |
Res. | INEPN EM |
INEPN MM |
ITTXFE MSK |
TOM | Res. | EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | NAKM | Res. | Res. | Res. | Res. | TXFU RM |
Res. | INEPN EM |
INEPN MM |
ITTXFE MSK |
TOM | AHB ERRM |
EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG HS
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | NAKM: NAK interrupt mask |
|
0: Masked interrupt |
|
| Bits 12:10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | TXFURM: FIFO underrun mask |
|
0: Masked interrupt |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | INEPNEM: IN endpoint NAK effective mask |
|
0: Masked interrupt |
|
| Bit 5 | INEPNMM: IN token received with EP mismatch mask |
|
0: Masked interrupt |
|
| Bit 4 | ITTXFEMSK: IN token received when Tx FIFO empty mask |
|
0: Masked interrupt |
|
| Bit 3 | TOM: Timeout condition mask (Non-isochronous endpoints) |
|
0: Masked interrupt |
|
| Bit 2 | AHBERRM: AHB error mask for USB OTG HS |
|
0: Masked interrupt |
|
| Bit 1 | EPDM: Endpoint disabled interrupt mask |
|
0: Masked interrupt |
|
| Bit 0 | XFRCM: Transfer completed interrupt mask |
|
0: Masked interrupt |
Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | NYET MSK |
NAK MSK |
BERR M |
Res. | Res. | Res. |
OUT PKT ERRM |
Res. | Res. |
STS PHSR XM |
OTEPD M |
STUPM | Res. | EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | NYET MSK |
NAK MSK |
BERR M |
Res. | Res. | Res. |
OUT PKT ERRM |
Res. | B2B STUPM |
STS PHSR XM |
OTEPD M |
STUPM | AHB ERRM |
EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register for USB OTG HS
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bit 14 | NYETMSK: NYET interrupt mask for USB OTG HS |
|
0: Masked interrupt |
|
| Bit 13 | NAKMSK: NAK interrupt mask |
|
0: Masked interrupt |
|
| Bit 12 | BERRM: Babble error interrupt mask |
|
0: Masked interrupt |
|
| Bits 11:10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | OUTPKTERRM: Out packet error mask |
|
0: Masked interrupt |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | B2BSTUPM: Back-to-back SETUP packets received mask for USB OTG HS |
|
Applies to control OUT endpoints only. |
|
| Bit 5 | STSPHSRXM: Status phase received for control write mask |
|
0: Masked interrupt |
|
| Bit 4 | OTEPDM: OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. |
|
0: Masked interrupt |
|
| Bit 3 | STUPM: STUPM: SETUP phase done mask. Applies to control endpoints only. |
|
0: Masked interrupt |
|
| Bit 2 | AHBERRM: AHB error mask for USB OTG HS |
|
0: Masked interrupt |
|
| Bit 1 | EPDM: Endpoint disabled interrupt mask |
|
0: Masked interrupt |
|
| Bit 0 | XFRCM: Transfer completed interrupt mask |
|
0: Masked interrupt |
Address offset: 0x818
Reset value: 0x0000 0000
When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OEPINT[15:0] |
IEPINT[15:0] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:16 | OEPINT[15:0]: OUT endpoint interrupt bits |
|
One bit per OUT endpoint: for OUT endpoint 0, bit 19 for OUT endpoint 3. |
|
| Bits 15:0 | IEPINT[15:0]: IN endpoint interrupt bits |
|
One bit per IN endpoint: for IN endpoint 0, bit 3 for endpoint 3. |
Address offset: 0x81C
Reset value: 0x0000 0000
The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OEPM[15:0] |
IEPM[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:16 | OEPM[15:0]: OUT EP interrupt mask bits |
|
One per OUT endpoint: for OUT EP 0, bit 19 for OUT EP 3 1: Unmasked interrupt |
|
| Bits 15:0 | IEPM[15:0]: IN EP interrupt mask bits |
|
One bit per IN endpoint: for IN EP 0, bit 3 for IN EP 3 1: Unmasked interrupt |
Address offset: 0x0828
Reset value: 0x0000 17D7
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
VBUSDT[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | VBUSDT[15:0]: Device VBUS discharge time |
|
Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals: |
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the VBUS pulsing time during SRP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
DVBUSP[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | DVBUSP[15:0]: Device VBUS pulsing time. This feature is only relevant to OTG1.3. |
|
Specifies the VBUS pulsing time during SRP. This value equals: |
Address offset: 0x0830
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | ARPEN | Res. | RXTHRLEN[8:0] | RXTH REN |
Res. | Res. | Res. | Res. | Res. | TXTHRLEN[8:0] | ISOT HREN |
NONIS OTH REN |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||
| Bits 31:28 | Reserved, must be kept at reset value. |
| Bit 27 | ARPEN: Arbiter parking enable |
|
This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. |
|
| Bit 26 | Reserved, must be kept at reset value. |
| Bits 25:17 | RXTHRLEN[8:0]: Receive threshold length |
|
This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). |
|
| Bit 16 | RXTHREN: Receive threshold enable |
|
When this bit is set, the core enables thresholding in the receive direction. |
|
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:2 | TXTHRLEN[8:0]: Transmit threshold length |
|
This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). |
|
| Bit 1 | ISOTHREN: ISO IN endpoint threshold enable |
|
When this bit is set, the core enables thresholding for isochronous IN endpoints. |
|
| Bit 0 | NONISOTHREN: Nonisochronous IN endpoints threshold enable |
|
When this bit is set, the core enables thresholding for nonisochronous IN endpoints. |
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
INEPTXFEM[15:0] |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | INEPTXFEM[15:0]: IN EP Tx FIFO empty interrupt mask bits |
|
These bits act as mask bits for OTG_DIEPINTx. for IN endpoint 0, bit 3 for IN endpoint 3 1: Unmasked interrupt |
Address offset: 0x0838
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OEP1 INT |
Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IEP1 INT |
Res. |
| r |
r |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | OEP1INT: OUT endpoint 1 interrupt bit |
| Bits 16:2 | Reserved, must be kept at reset value. |
| Bit 1 | IEP1INT: IN endpoint 1interrupt bit |
| Bit 0 | Reserved, must be kept at reset value. |
Address offset: 0x083C
Reset value: 0x0000 0000
There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OEP1 INTM |
Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IEP1I NTM |
Res. |
| rw |
rw |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | OEP1INTM: OUT endpoint 1 interrupt mask bit |
| Bits 16:2 | Reserved, must be kept at reset value. |
| Bit 1 | IEP1INTM: IN endpoint 1 interrupt mask bit |
| Bit 0 | Reserved, must be kept at reset value. |
Note: Configuration register applies only to USB OTG HS
Address offset: 0x844
Reset value: 0x0000 0000
This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | NAKM | Res. | Res. | Res. | Res. | TXFU RM |
Res. | INEPN EM |
Res. | ITTXFE MSK |
TOM | AHB ERRM |
EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register applies only to USB OTG HS
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | NAKM: NAK interrupt mask |
|
0: Masked interrupt |
|
| Bits 12:10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | TXFURM: FIFO underrun mask |
|
0: Masked interrupt |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | INEPNEM: IN endpoint NAK effective mask |
|
0: Masked interrupt |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | ITTXFEMSK: IN token received when Tx FIFO empty mask |
|
0: Masked interrupt |
|
| Bit 3 | TOM: Timeout condition mask (Non-isochronous endpoints) |
|
0: Masked interrupt |
|
| Bit 2 | AHBERRM: AHB error mask |
|
0: Masked interrupt |
|
| Bit 1 | EPDM: Endpoint disabled interrupt mask |
|
0: Masked interrupt |
|
| Bit 0 | XFRCM: Transfer completed interrupt mask |
|
0: Masked interrupt |
Address offset: 0x884
Reset value: 0x0000 0000
This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | NYET MSK |
NAK MSK |
BERR M |
Res. | Res. | Res. |
OUT PKT ERRM |
Res. | B2B STUPM |
Res. | OTEPD M |
STUPM | AHB ERRM |
EPDM | XFRC M |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Note: Configuration register applies only to USB OTG HS
| Bits 31:15 | Reserved, must be kept at reset value. |
| Bit 14 | NYETMSK: NYET interrupt mask |
|
0: Masked interrupt |
|
| Bit 13 | NAKMSK: NAK interrupt mask |
|
0: Masked interrupt |
|
| Bit 12 | BERRM: Babble error interrupt mask |
|
0: Masked interrupt |
|
| Bits 11:10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | OUTPKTERRM: Out packet error mask |
|
0: Masked interrupt |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | B2BSTUPM: Back-to-back SETUP packets received mask |
|
Applies to control OUT endpoints only. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bit 4 | OTEPDM: OUT token received when endpoint disabled mask |
|
Applies to control OUT endpoints only. |
|
| Bit 3 | STUPM: STUPM: SETUP phase done mask |
|
Applies to control endpoints only. |
|
| Bit 2 | AHBERRM: AHB error mask |
|
0: Masked interrupt |
|
| Bit 1 | EPDM: Endpoint disabled interrupt mask |
|
0: Masked interrupt |
|
| Bit 0 | XFRCM: Transfer completed interrupt mask |
|
0: Masked interrupt |
Address offset: 0x900
Reset value: 0x0000 0000
This section describes the OTG_DIEPCTL0 register for USB_OTG FS. Nonzero control endpoints use registers for endpoints 1–3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EPENA | EPDIS | Res. | Res. | SNAK | CNAK | TXFNUM[3:0] | STALL | Res. | EPTYP | NAK STS |
Res. |
USBA EP |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MPSIZ[1:0] |
|||||
| rs | rs | w | w | rw | rw | rw | rw | rs | r | r | r |
r | rw | rw | |||||||||||||||||
| Bit 31 | EPENA: Endpoint enable |
|
The application sets this bit to start transmitting data on the endpoint 0.
|
|
| Bit 30 | EPDIS: Endpoint disable |
|
The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. |
|
| Bits 29:28 | Reserved, must be kept at reset value. |
| Bit 27 | SNAK: Set NAK |
|
A write to this bit sets the NAK bit for the endpoint. |
|
| Bit 26 | CNAK: Clear NAK |
|
A write to this bit clears the NAK bit for the endpoint. |
|
| Bits 25:22 | TXFNUM[3:0]: Tx FIFO number |
|
This value is set to the FIFO number that is assigned to IN endpoint 0. |
|
| Bit 21 | STALL: STALL handshake |
|
The application can only set this bit, and the core clears it when a SETUP token is received for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit, the STALL bit takes priority. |
|
| Bit 20 | Reserved, must be kept at reset value. |
| Bits 19:18 | EPTYP: Endpoint type |
|
Hardcoded to ‘00’ for control. |
|
| Bit 17 | NAKSTS: NAK status |
|
Indicates the following: |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bit 15 | USBAEP: USB active endpoint |
|
This bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. |
|
| Bits 14:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | MPSIZ[1:0]: Maximum packet size |
|
The application must program this field with the maximum packet size for the current logical endpoint. |
Note: Configuration register applies only to USB OTG FS
Address offset: 0x900 + (x * 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EPENA | EPDIS | SODD FRM |
SD0 PID/ SEVN FRM |
SNAK | CNAK | TXFNUM[3:0] | STALL | Res. | EPTYP[1:0] | NAK STS |
EO NUM/ DPID |
USBA EP |
Res. | Res. | Res. | Res. | MPSIZ[10:0] |
||||||||||||||
| rs | rs | w | w | w | w | rw | rw | rw | rw | rw/rs | rw | rw | r | r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||
| Bit 31 | EPENA: Endpoint enable |
|
The application sets this bit to start transmitting data on an endpoint.
|
|
| Bit 30 | EPDIS: Endpoint disable |
|
The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. |
|
| Bit 29 | SODDFRM: Set odd frame |
|
Applies to isochronous IN and OUT endpoints only. |
|
| Bit 28 | SD0PID: Set DATA0 PID |
|
Applies to interrupt/bulk IN endpoints only. SEVNFRM: Set even frame Applies to isochronous IN endpoints only. |
|
| Bit 27 | SNAK: Set NAK |
|
A write to this bit sets the NAK bit for the endpoint. |
|
| Bit 26 | CNAK: Clear NAK |
|
A write to this bit clears the NAK bit for the endpoint. |
|
| Bits 25:22 | TXFNUM: Tx FIFO number |
|
These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. |
|
| Bit 21 | STALL: STALL handshake |
|
Applies to non-control, non-isochronous IN endpoints only (access type is rw). Applies to control endpoints only (access type is rs). |
|
| Bit 20 | Reserved, must be kept at reset value. |
| Bits 19:18 | EPTYP[1:0]: Endpoint type |
|
This is the transfer type supported by this logical endpoint. |
|
| Bit 17 | NAKSTS: NAK status |
|
It indicates the following: |
|
| Bit 16 | EONUM: Even/odd frame |
|
Applies to isochronous IN endpoints only. DPID: Endpoint data PID Applies to interrupt/bulk IN endpoints only. |
|
| Bit 15 | USBAEP: USB active endpoint |
|
Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. |
|
| Bits 14:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | MPSIZ[10:0]: Maximum packet size |
|
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. |
Address offset: 0x908 + (x * 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 518. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | NAK | Res. | PKTD RPSTS |
Res. | Res. |
TXFIF OUD RN |
TXFE | IN EPNE |
IN EPNM |
ITTXFE | TOC | Res. | EP DISD |
XFRC |
| rc_w1 | rc_w1 | rc_w1 | r | r | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG FS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | NAK | Res. | PKTD RPSTS |
Res. | Res. |
TXFIF OUD RN |
TXFE | IN EPNE |
IN EPNM |
ITTXFE | TOC | AHB ERR |
EP DISD |
XFRC |
| rc_w1 | rc_w1 | rc_w1 | r | r | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG HS
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | NAK: NAK input |
|
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. |
|
| Bit 12 | Reserved, must be kept at reset value. |
| Bit 11 | PKTDRPSTS: Packet dropped status |
|
This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. |
|
| Bit 10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn) |
|
The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled |
|
| Bit 7 | TXFE: Transmit FIFO empty |
|
This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). |
|
| Bit 6 | INEPNE: IN endpoint NAK effective |
|
This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. |
|
| Bit 5 | INEPNM: IN token received with EP mismatch |
|
Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. |
|
| Bit 4 | ITTXFE: IN token received when Tx FIFO is empty |
|
Indicates that an IN token was received when the associated Tx FIFO (periodic/non- |
|
| Bit 3 | TOC: Timeout condition |
|
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. |
|
| Bit 2 | AHBERR: AHB error for USB OTG HS |
|
This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. |
|
| Bit 1 | EPDISD: Endpoint disabled interrupt |
|
This bit indicates that the endpoint is disabled per the application’s request. |
|
| Bit 0 | XFRC: Transfer completed interrupt |
|
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. |
Address offset: 0x910
Reset value: 0x0000 0000
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (EPENA in OTG_DIEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
Nonzero endpoints use the registers for endpoints 1–3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKTCNT[1:0] | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | XFRSIZ[6:0] |
|||||||
| rw | rw |
rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||||||||||
| Bits 31:21 | Reserved, must be kept at reset value. |
| Bits 20:19 | PKTCNT[1:0]: Packet count |
|
Indicates the total number of USB packets that constitute the transfer size amount of data for endpoint 0. |
|
| Bits 18:7 | Reserved, must be kept at reset value. |
| Bits 6:0 | XFRSIZ[6:0]: Transfer size |
|
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. |
Address offset: 0x914 + (x * 0x20)
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMAADDR[31:16] |
DMAADDR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DMAADDR[31:0]: DMA Address |
|
This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. |
Address offset for IN endpoints: 0x918 + (x * 0x20) This read-only register contains the free space information for the device IN endpoint Tx FIFO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
INEPTFSAV[15:0] |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | INEPTFSAV[15:0]: IN endpoint Tx FIFO space available |
|
Indicates the amount of free space available in the endpoint Tx FIFO. |
Address offset: 0x910 + (x * 0x20)
Reset value: 0x0000 0000
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | MCNT[1:0] | PKTCNT[9:0] | XFRSIZ[18:16] |
XFRSIZ[15:0] |
|||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:29 | MCNT[1:0]: Multi count |
|
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. |
|
| Bits 28:19 | PKTCNT[9:0]: Packet count |
|
Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. |
|
| Bits 18:0 | XFRSIZ[18:0]: Transfer size |
|
This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. |
Address offset: 0xB00
Reset value: 0x0000 8000
This section describes the OTG_DOEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EPENA | EPDIS | Res. | Res. | SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EPTYP[1:0] | NAK STS |
Res. |
USBA EP |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MPSIZ[1:0] |
||
| w | r | w | w | rs | rw | r | r | r |
r | r | r |
||||||||||||||||||||
| Bit 31 | EPENA: Endpoint enable |
|
The application sets this bit to start transmitting data on endpoint 0.
|
|
| Bit 30 | EPDIS: Endpoint disable |
|
The application cannot disable control OUT endpoint 0. |
|
| Bits 29:28 | Reserved, must be kept at reset value. |
| Bit 27 | SNAK: Set NAK |
|
A write to this bit sets the NAK bit for the endpoint. |
|
| Bit 26 | CNAK: Clear NAK |
|
A write to this bit clears the NAK bit for the endpoint. |
|
| Bits 25:22 | Reserved, must be kept at reset value. |
| Bit 21 | STALL: STALL handshake |
|
The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. |
|
| Bit 20 | SNPM: Snoop mode |
|
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. |
|
| Bits 19:18 | EPTYP[1:0]: Endpoint type |
|
Hardcoded to 2’b00 for control. |
|
| Bit 17 | NAKSTS: NAK status |
|
Indicates the following: |
|
| Bit 16 | Reserved, must be kept at reset value. |
| Bit 15 | USBAEP: USB active endpoint |
|
This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. |
|
| Bits 14:2 | Reserved, must be kept at reset value. |
| Bits 1:0 | MPSIZ[1:0]: Maximum packet size |
|
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0. |
Address offset: 0xB08 + (x * 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 518. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | NYET | NAK | BERR | Res. | Res. | Res. |
OUT PKT ERR |
Res. | Res. | STSPH SRX |
OTEP DIS |
STUP | Res. | EP DISD |
XFRC |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG FS.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
STPK TRX |
NYET | NAK | BERR | Res. | Res. | Res. |
OUT PKT ERR |
Res. | B2B STUP |
STSPH SRX |
OTEP DIS |
STUP | AHB ERR |
EP DISD |
XFRC |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
Note: Configuration register for USB OTG HS.
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bit 15 | STPKTRX: Setup packet received. |
|
Applicable for control OUT endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one setup packet per buffer. On receiving a setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the control transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. |
|
| Bit 14 | NYET: NYET interrupt |
|
This interrupt is generated when a NYET response is transmitted for a non isochronous OUT endpoint. |
|
| Bit 13 | NAK: NAK input |
|
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. |
|
| Bit 12 | BERR: Babble error interrupt |
|
The core generates this interrupt when babble is received for the endpoint. |
|
| Bits 11:10 | Reserved, must be kept at reset value. |
| Bit 9 | Reserved, must be kept at reset value. |
| Bit 8 | OUTPKTERR: OUT packet error |
|
This interrupt is asserted when the core detects an overflow or a CRC error for an OUT packet. This interrupt is valid only when thresholding is enabled. |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bit 6 | B2BSTUP: Back-to-back SETUP packets received for USB OTG HS |
|
Applies to control OUT endpoint only. |
|
| Bit 5 | STSPHSRX: Status phase received for control write |
|
This interrupt is valid only for control OUT endpoints. This interrupt is generated only after OTG_FS/OTG_HS has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a control write transfer. The application can use this interrupt to ACK or STALL the status phase, after it has decoded the data phase. |
|
| Bit 4 | OTEPDIS: OUT token received when endpoint disabled |
|
Applies only to control OUT endpoints. |
|
| Bit 3 | STUP: SETUP phase done |
|
Applies to control OUT endpoint only. |
|
| Bit 2 | AHBERR: AHB error for USB OTG HS |
|
This is generated only in internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address. |
|
| Bit 1 | EPDISD: Endpoint disabled interrupt |
|
This bit indicates that the endpoint is disabled per the application’s request. |
|
| Bit 0 | XFRC: Transfer completed interrupt |
|
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. |
Address offset: 0xB10
Reset value: 0x0000 0000
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the OTG_DOEPCTL0 registers (EPENA bit in OTG_DOEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
Nonzero endpoints use the registers for endpoints 1–5[FS] /8[HS].
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | STUPCNT[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
PKTCNT | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | XFRSIZ[6:0] |
|||||||
| rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:29 | STUPCNT[1:0]: SETUP packet count |
|
This field specifies the number of back-to-back SETUP data packets the endpoint can receive. |
|
| Bits 28:20 | Reserved, must be kept at reset value. |
| Bit 19 | PKTCNT: Packet count |
|
This field is decremented to zero after a packet is written into the Rx FIFO. |
|
| Bits 18:7 | Reserved, must be kept at reset value. |
| Bits 6:0 | XFRSIZ[6:0]: Transfer size |
|
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. |
Address offset: 0xB14 + (x * 0x20)
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMAADDR[31:16] |
DMAADDR[15:0] |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | DMAADDR[31:0]: DMA Address |
|
This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. |
Address offset for OUT endpoints: 0xB00 + (x * 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EPENA | EPDIS |
SD1 PID/ SODD FRM |
SD0 PID/ SEVN FRM |
SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EPTYP[1:0] | NAK STS |
EO NUM/ DPID |
USBA EP |
Res. | Res. | Res. | Res. | MPSIZ[10:0] |
|||||||||||
| rs | rs | w | w | w | w | rw/rs | rw | rw | rw | r | r |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bit 31 | EPENA: Endpoint enable |
|
Applies to IN and OUT endpoints.
|
|
| Bit 30 | EPDIS: Endpoint disable |
|
The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the endpoint disabled interrupt. The application must set this bit only if endpoint enable is already set for this endpoint. |
|
| Bit 29 | SD1PID: Set DATA1 PID |
|
Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. SODDFRM: Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. |
|
| Bit 28 | SD0PID: Set DATA0 PID |
|
Applies to interrupt/bulk OUT endpoints only. SEVNFRM: Set even frame Applies to isochronous OUT endpoints only. |
|
| Bit 27 | SNAK: Set NAK |
|
A write to this bit sets the NAK bit for the endpoint. |
|
| Bit 26 | CNAK: Clear NAK |
|
A write to this bit clears the NAK bit for the endpoint. |
|
| Bits 25:22 | Reserved, must be kept at reset value. |
| Bit 21 | STALL: STALL handshake |
|
Applies to non-control, non-isochronous OUT endpoints only (access type is rw). Applies to control endpoints only (access type is rs). |
|
| Bit 20 | SNPM: Snoop mode |
|
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. |
|
| Bits 19:18 | EPTYP[1:0]: Endpoint type |
|
This is the transfer type supported by this logical endpoint. |
|
| Bit 17 | NAKSTS: NAK status |
|
Indicates the following: |
|
| Bit 16 | EONUM: Even/odd frame |
|
Applies to isochronous IN and OUT endpoints only. DPID: Endpoint data PID Applies to interrupt/bulk OUT endpoints only. |
|
| Bit 15 | USBAEP: USB active endpoint |
|
Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. |
|
| Bits 14:11 | Reserved, must be kept at reset value. |
| Bits 10:0 | MPSIZ[10:0]: Maximum packet size |
|
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. |
Address offset: 0xB10 + (x * 0x20)
Reset value: 0x0000 0000
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | RXDPID/ STUPCNT[1:0] |
PKTCNT[9:0] | XFRSIZ |
XFRSIZ |
|||||||||||||||||||||||||||
| r/rw | r/rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|
| Bit 31 | Reserved, must be kept at reset value. |
| Bits 30:29 | RXDPID[1:0]: Received data PID |
|
Applies to isochronous OUT endpoints only. |
STUPCNT[1:0]: SETUP packet count
Applies to control OUT endpoints only.
This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
01: 1 packet
10: 2 packets
11: 3 packets
| Bits 28:19 | PKTCNT[9:0]: Packet count |
|
Indicates the total number of USB packets that constitute the transfer size amount of data for this endpoint. |
|
| Bits 18:0 | XFRSIZ: Transfer size |
|
This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. |
Address offset: 0xE00
Reset value: 0x200B 8000
This register is available in host and device modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SUSP | PHY SLEEP |
ENL1 GTG |
PHY SUSP |
Res. | Res. | GATE HCLK |
STPP CLK |
| r | r | rw | r | rw | rw |
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bit 7 | SUSP: Deep Sleep |
|
This bit indicates that the PHY is in Deep Sleep when in L1 state. |
|
| Bit 6 | PHYSLEEP: PHY in Sleep |
|
This bit indicates that the PHY is in the Sleep state. |
|
| Bit 5 | ENL1GTG: Enable sleep clock gating |
|
When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. |
|
| Bit 4 | PHYSUSP: PHY suspended |
|
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended after the application has set the STPPCLK bit. |
|
| Bits 3:2 | Reserved, must be kept at reset value. |
| Bit 1 | GATEHCLK: Gate HCLK |
|
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. |
|
| Bit 0 | STPPCLK: Stop PHY clock |
|
The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. |
The table below gives the USB OTG register map and reset values.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 |
OTG_ GOTGCTL |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | CURMOD | OTGVER | BSVLD | ASVLD | DBCT | CIDSTS | Res. | Res. | Res. | EHEN | DHNPEN | HSHNPEN | HNPRQ | HNGSCS | BVALOVAL | BVALOEN | AVALOVAL | AVALOEN | VBVALOVA | VBVALOEN | SRQ | SRQSCS |
| Reset value | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x004 |
OTG_ GOTGINT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IDCHNG | DBCDNE | ADTOCHG | HNGDET | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HNSSCHG | SRSSCHG | Res. | Res. | Res. | Res. | Res. | SEDET | Res. | Res. |
| Reset value | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x008 |
OTG_ GAHBCFG |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PTXFELVL | TXFELVL | Res. | Res. | Res. | Res. | Res. | Res. | GINTMSK |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x008 |
OTG_ GAHBCFG |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PTXFELVL | TXFELVL | Res. | DMAEN | HBSTLEN |
GINTMSK | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x00C |
OTG_ GUSBCFG |
Res. | FDMOD | FHMOD | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TRDT |
HNPCA | SRPCAP | Res. | PHYSEL | Res. | Res. | Res. | TOCAL |
|||||
| Reset value | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x00C |
OTG_ GUSBCFG |
Res. | FDMOD | FHMOD | Res. | Res. | Res. | ULPIIPD | PTCI | PCCI | TSDPS | ULPIEVBUSI | ULPIEVBUSD | ULPICSM | ULPIAR | ULPIFSL | Res. | PHYLPC | Res. | TRDT |
HNPCAP | SRPCAP | Res. | PHYSEL | Res. | Res. | Res. | TOCAL |
|||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | |||||||||||
| 0x010 |
OTG_ GRSTCTL |
AHBIDL | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXFNUM |
TXFFLSH | RXFFLSH | Res. | FCRST | PSRST | CSRST | ||||
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x010 |
OTG_ GRSTCTL |
AHBIDL | DMAREQ | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXFNUM |
TXFFLSH | RXFFLSH | Res. | Res. | PSRST | CSRST | ||||
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x014 |
OTG_ GINTSTS |
WKUPINT | SRQINT | DISCINT | CIDSCHG | LPMINT | PTXFE | HCINT | HPRTINT | RSTDET | Res. | IPXFR/INCOMPISOOUT | IISOIXFR | OEPINT | IEPINT | Res. | Res. | EOPF | ISOODRP | ENUMDNE | USBRST | USBSUSP | ESUSP | Res. | Res. | GONAKEFF | GINAKEFF | NPTXFE | RXFLVL | SOF | OTGINT | MMIS | CMOD |
| Reset value | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x014 |
OTG_ GINTSTS |
WKUPINT | SRQINT | DISCINT | CIDSCHG | Res. | PTXFE | HCINT | HPRTINT | Res. | DATAFSUSP | IPXFR/INCOMPISOOUT | IISOIXFR | OEPINT | IEPINT | Res. | Res. | EOPF | ISOODRP | ENUMDNE | USBRST | USBSUSP | ESUSP | Res. | Res. | GONAKEFF | GINAKEFF | NPTXFE | RXFLVL | SOF | OTGINT | MMIS | CMOD |
| Reset value | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x018 |
OTG_ GINTMSK |
WUIM | SRQIM | DISCINT | CIDSCHGM | LPMINTM | PTXFEM | HCIM | PRTIM | RSTDETM | Res. | IPXFRM/IISOOXFRM | IISOIXFRM | OEPINT | IEPINT | Res. | Res. | EOPFM | ISOODRPM | ENUMDNEM | USBRST | USBSUSPM | ESUSPM | Res. | Res. | GONAKEFFM | GINAKEFFM | NPTXFEM | RXFLVLM | SOFM | OTGINT | MMISM | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x018 |
OTG_ GINTMSK |
WUIM | SRQIM | DISCINT | CIDSCHGM | LPMINTM | PTXFEM | HCIM | PRTIM | RSTDETM | FSUSPM | IPXFRM/IISOOXFRM | IISOIXFRM | OEPINT | IEPINT | Res. | Res. | EOPFM | ISOODRPM | ENUMDNEM | USBRST | USBSUSPM | ESUSPM | Res. | Res. | GONAKEFFM | GINAKEFFM | NPTXFEM | RXFLVLM | SOFM | OTGINT | MMISM | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x01C |
OTG_ GRXSTSR (host mode) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKTSTS | DPID | BCNT | CHNUM |
|||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| OTG_ GRXSTSR (Device mode) |
Res. | Res. | Res. | Res. | STSPHST | Res. | Res. | FRMNUM | PKTSTS | DPID | BCNT | EPNUM |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x020 |
OTG_ GRXSTSP (host mode) |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKTSTS | DPID | BCNT | CHNUM |
|||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||
| OTG_ GRXSTSP (Device mode) |
Res. | Res. | Res. | Res. | STSPHST | Res. | Res. | FRMNUM | PKTSTS | DPID | BCNT | EPNUM |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||
| 0x024 |
OTG_ GRXFSIZ |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RXFD |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x028 |
OTG_ HNPTXFSIZ/ OTG_ DIEPTXF0 |
NPTXFD/TX0FD | NPTXFSA/TX0FSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x02C |
OTG_ HNPTXSTS |
Res. | NPTXQTOP | NPTQXSAV | NPTXFSAV |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x038 |
OTG_ GCCFG |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBDEN | SDEN | PDEN | DCDEN | BCDEN | PWRDWN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PS2DET | SDET | PDET | DCDET |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | X | X | X | X |
|||||||||||||||||||||||
| 0x03C |
OTG_CID | PRODUCT_ID (for USB OTG FS) |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x03C |
OTG_CID | PRODUCT_ID (for USB OTG HS) |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x054 |
OTG_ GLPMCFG |
Res. | Res. | Res. | ENBESL | LPMR CNTSTS |
SNDLPM | LPM RCNT |
LPMCHIDX |
L1RSMOK | SLPSTS | LPM RSP |
L1DSEN | BESLTHRS |
L1SSEN | REMWAKE | BESL |
LPMACK | LPMEN | ||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x100 |
OTG_ HPTXFSIZ |
PTXFSIZ | PTXSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x104 |
OTG_ DIEPTXF1 |
INEPTXFD | INEPTXSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x108 |
OTG_ DIEPTXF2 |
INEPTXFD | INEPTXSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x114 |
OTG_ DIEPTXF5 |
INEPTXFD | INEPTXSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x120 |
OTG_ DIEPTXF7 |
INEPTXFD | INEPTXSA |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x400 |
OTG_ HCFG |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | FSLSS | FSL S PCS |
|
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x404 |
OTG_ HFIR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RLDCTR | FRIVL |
|||||||||||||||
| Reset value | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x408 |
OTG_ HFNUM |
FTREM | FRNUM |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x410 |
OTG_ HPTXSTS |
PTXQTOP | PTXQSAV | PTXFSAVL |
|||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x414 |
OTG_ HAINT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HAINT |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x418 |
OTG_ HAINTMSK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HAINTM |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x440 |
OTG_ HPRT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PSP D |
PTCTL |
PPWR | PLSTS | Res. | PRST | PSUSP | PRES | POCCHNG | POCA | PENCHNG | PENA | PCDET | PCSTS | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x500 |
OTG_ HCCHAR0 |
CHENA | CHDIS | ODDFRM | DAD |
MCNT | EPTYP | LSDEV | Res. | EPDIR | EPNUM | MPSIZ |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x504 |
OTG_ HCSPLT0 |
SPLITEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMPLSPLT | XAC TPO S |
HUBADDR | PRTADDR |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x508 |
OTG_ HCINT0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERR | FRMOR | BBERR | TXERR | Res. | ACK | NAK | STALL | Res. | CHH | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x50C |
OTG_ HCINTMSK0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERRM | FRMORM | BBERRM | TXERRM | NYET | ACKM | NAKM | STALLM | Res. | CHHM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x510 |
OTG_ HCTSIZ0 |
Res. | DPID | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x514 |
OTG_ HCDMA0 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x520 |
OTG_ HCCHAR1 |
CHENA | CHDIS | ODDFRM | DAD |
MCNT | EPTYP | LSDEV | Res. | EPDIR | EPNUM | MPSIZ |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x524 |
OTG_ HCSPLT1 |
SPLITEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMPLSPLT | XAC TPO S |
HUBADDR | PRTADDR |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x528 |
OTG_ HCINT1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERR | FRMOR | BBERR | TXERR | Res. | ACK | NAK | STALL | Res. | CHH | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x52C |
OTG_ HCINTMSK1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERRM | FRMORM | BBERRM | TXERRM | NYET | ACKM | NAKM | STALLM | Res. | CHHM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x530 |
OTG_ HCTSIZ1 |
Res. | DPID | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x534 |
OTG_ HCDMA1 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x660 |
OTG_ HCCHAR11 |
CHENA | CHDIS | ODDFRM | DAD |
MCNT | EPTYP | LSDEV | Res. | EPDIR | EPNUM | MPSIZ |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x664 |
OTG_ HCSPLT11 |
SPLITEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMPLSPLT | XAC TPO S |
HUBADDR | PRTADDR |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x668 |
OTG_ HCINT11 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERR | FRMOR | BBERR | TXERR | Res. | ACK | NAK | STALL | Res. | CHH | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x66C |
OTG_ HCINTMSK11 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERRM | FRMORM | BBERRM | TXERRM | NYET | ACKM | NAKM | STALLM | Res. | CHHM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x670 |
OTG_ HCTSIZ11 |
Res. | DPID | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x674 |
OTG_ HCDMA11 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x6E0 |
OTG_ HCCHAR15 |
CHENA | CHDIS | ODDFRM | DAD |
MCNT | EPTYP | LSDEV | Res. | EPDIR | EPNUM | MPSIZ |
|||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x6E4 |
OTG_ HCSPLT15 |
SPLITEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | COMPLSPLT | XAC TPO S |
HUBADDR | PRTADDR |
|||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||
| 0x6E8 |
OTG_ HCINT15 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERR | FRMOR | BBERR | TXERR | Res. | ACK | NAK | STALL | Res. | CHH | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x6EC |
OTG_ HCINTMSK15 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DTERRM | FRMORM | BBERRM | TXERRM | NYET | ACKM | NAKM | STALLM | Res. | CHHM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x6F0 |
OTG_ HCTSIZ15 |
Res. | DPID | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x6F4 |
OTG_ HCDMA15 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x800 |
OTG_ DCFG |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ERRATIM | XCVRDLY | Res. | PFIVL | DAD | Res. | NZLSOHSK | DSPD | ||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x804 |
OTG_ DCTL |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DSBESLRJCT | Res. | Res. | Res. | Res. | Res. | Res. | POPRGDNE | CGONAK | SGONAK | CGINAK | SGINAK | TCTL | GONSTS | GINSTS | SDIS | RWUSIG | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
||||||||||||||||||||
| 0x808 |
OTG_ DSTS |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DEV LN STS |
FNSOF |
Res. | Res. | Res. | Res. | EERR | ENUMSPD | SUSPSTS | |||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0x810 |
OTG_ DIEPMSK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAKM | Res. | Res. | Res. | Res. | TXFURM | Res. | INEPNEM | INEPNMM | ITTXFEMSK | TOM | AHBERRM | EPDM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x814 |
OTG_ DOEPMSK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NYETMSK | NAKMSK | BERRM | Res. | Res. | Res. | OUTPKTERRM | Res. | B2BSTUPM | Res. | OTEPDM | STUPM | AHBERRM | EPDM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x818 |
OTG_ DAINT |
OEPINT | IEPINT |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x81C |
OTG_ DAINTMSK |
OEPM | IEPM |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x828 |
OTG_ DVBUSDIS |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VBUSDT |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
|||||||||||||||||
| 0x82C |
OTG_DVB USPULSE |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DVBUSP |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 |
|||||||||||||||||
| 0x830 |
OTG_ DTHRCTL |
Res. | Res. | Res. | Res. | ARPEN | Res. | RXTHRLEN |
RXTHREN | Res. | Res. | Res. | Res. | TXTHRLEN |
ISOTHREN | NONISOTHREN | |||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||
| 0x834 |
OTG_DIE PEMPMSK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INEPTXFEM |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x838 |
OTG_ DEACHINT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OEP1INT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IEP1INT | Res. |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x83C |
OTG_DEACHI NTMSK |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | OEP1INTM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | IEP1INTM | Res. |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x844 |
OTG_HS_ DIEPEACH MSK1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAKM | Res. | Res. | Res. | Res. | TXFURM | Res. | INEPNEM | Res. | ITTXFEMSK | TOM | AHBERRM | EPDM | XFRCM |
| Reset value | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x884 |
OTG_HS_ DOEPEACH MSK1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NYETMSK | NAKMSK | BERRM | Res. | Res. | Res. | OUTPKTERRM | Res. | B2BSTUPM | Res. | OTEPDM | STUPM | AHBERRM | EPDM | XFRCM |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0x900 |
OTG_ DIEPCTL0 |
EPENA | EPDIS | Res. | Res. | SNAK | CNAK | TXFNUM |
STALL | Res. | EPTYP | NAKSTS | Res. | USBAEP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MPSIZ | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
||||||||||||||||||
| 0x900 |
OTG_ DIEPCTL0 |
EPENA | EPDIS | SODDFRM/SD1PID | SD0PID/SEVNFRM | SNAK | CNAK | TXFNUM |
STALL | Res. | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x908 |
OTG_ DIEPINT0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAK | Res. | PKTDRPSTS | Res. | Res. | TXFIFOUDRN | TXFE | INEPNE | INEPNM | ITTXFE | TOC | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x910 |
OTG_ DIEPTSIZ0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKT CNT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | XFRSIZ |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||
| 0x914 |
OTG_ DIEPDMA |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x918 |
OTG_ DTXFSTS0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INEPTFSAV |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x920 |
OTG_ DIEPCTL1 |
EPENA | EPDIS | SODDFRM/SD1PID | SD0PID/SEVNFRM | SNAK | CNAK | TXFNUM |
STALL | Res. | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x928 |
OTG_ DIEPINT1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAK | Res. | PKTDRPSTS | Res. | Res. | TXFIFOUDRN | TXFE | INEPNE | INEPNM | ITTXFE | TOC | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0x930 |
OTG_ DIEPTSIZ1 |
Res. | MCN T |
PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x938 |
OTG_ DTXFSTS1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INEPTFSAV |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x940 |
OTG_ DIEPCTL2 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | TXFNUM |
STALL | Res. | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9A0 |
OTG_ DIEPCTL5 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | TXFNUM |
STALL | Res. | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9A8 |
OTG_ DIEPINT5 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAK | Res. | PKTDRPSTS | Res. | Res. | TXFIFOUDRN | TXFE | INEPNE | INEPNM | ITTXFE | TOC | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9B8 |
OTG_ DTXFSTS5 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INEPTFSAV |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9E0 |
OTG_ DIEPCTL7 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | TXFNUM |
STALL | Res. | EPT YP |
NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9B0 |
OTG_ DIEPTSIZ5 |
Res. | MCNT | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0x9E8 |
OTG_ DIEPINT7 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NAK | Res. | PKTDRPSTS | Res. | Res. | TXFIFOUDRN | TXFE | INEPNE | INEPNM | ITTXFE | TOC | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9F0 |
OTG_ DIEPTSIZ7 |
Res. | MCN T |
PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0x9F8 |
OTG_ DTXFSTS7 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | INEPTFSAV |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0xB00 |
OTG_ DOEPCTL0 |
EPENA | EPDIS | Res. | Res. | SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EPTYP | NAKSTS | Res. | USBAEP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MPSIZ | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|||||||||||||||||||||
| 0xB08 |
OTG_ DOEPINT0 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STPKTRX | NYET | NAK | BERR | Res. | Res. | Res. | OUTPKTERR | Res. | B2BSTUP | STSPHSRX | OTEPDIS | STUP | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xB10 |
OTG_ DOEPTSIZ0 |
Res. | STU P CNT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PKTCNT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | XFRSIZ |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||
| 0xB14 |
OTG_ DOEPDMA0 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0xB20 |
OTG_ DOEPCTL1 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EP TYP |
NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0xB28 |
OTG_ DOEPINT1 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STPKTRX | NYET | NAK | BERR | Res. | Res. | Res. | OUTPKTERR | Res. | B2BSTUP | STSPHSRX | OTEPDIS | STUP | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0xB30 |
OTG_ DOEPTSIZ1 |
Res. | SRTXUDPPCIDN/T | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0xB34 |
OTG_ DOEPDMA1 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0xBA0 |
OTG_ DOEPCTL5 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0xBA8 |
OTG_ DOEPINT5 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STPKTRX | NYET | NAK | BERR | Res. | Res. | Res. | OUTPKTERR | Res. | B2BSTUP | STSPHSRX | OTEPDIS | STUP | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0xBB0 |
OTG_ DOEPTSIZ5 |
Res. | SRTXUDPPCIDN/T | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| . . . . |
. . . . |
. . . . |
|||||||||||||||||||||||||||||||
| 0xC00 |
OTG_ DOEPCTL8 |
EPENA | EPDIS | SODDFRM | SD0PID/SEVNFRM | SNAK | CNAK | Res. | Res. | Res. | Res. | STALL | SNPM | EPTYP | NAKSTS | EONUM/DPID | USBAEP | Res. | Res. | Res. | Res. | MPSIZ |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||
| 0xC08 |
OTG_ DOEPINT8 |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STPKTRX | NYET | NAK | BERR | Res. | Res. | Res. | OUTPKTERR | Res. | B2BSTUP | STSPHSRX | OTEPDIS | STUP | AHBERR | EPDISD | XFRC |
| Reset value | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0xC10 |
OTG_ DOEPTSIZ8 |
Res. | SRTXUDPPCINDT/ | PKTCNT | XFRSIZ |
||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||
| 0xC14 |
OTG_ DOEPDMA8 |
DMAADDR |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0xE00 |
OTG_ PCGCCTL |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SUSP | PHYSLEEP | ENL1GTG | PHYSUSP | Res. | Res. | GATEHCLK | STPPCLK |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the OTG_GINTSTS (CMOD bit in OTG_GINTSTS) reflects the mode. The OTG_FS/OTG_HS controller enters host mode when an “A” plug is connected or device mode when a “B” plug is connected.
This section explains the initialization of the OTG_FS/OTG_HS controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized according to the core’s configuration:
The software must unmask the following bits in the OTG_GINTMSK register:
OTG interrupt mask
Mode mismatch interrupt mask
To initialize the core as host, the application must perform the following steps:
To communicate with devices, the system software must initialize and enable at least one channel.
The application must perform the following steps to initialize the core as a device on power-up or after a mode change from host to device.
Wait for the ENUMDNE interrupt in OTG_GINTSTS. This interrupt indicates the end of reset on the USB. On receiving this interrupt, the application must read the OTG_DSTS register to determine the enumeration speed and perform the steps listed in Endpoint initialization on
enumeration completion on page 1738.
At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.
The OTG host uses the AHB master interface to fetch the transmit packet data (AHB to USB) and receive the data update (USB to AHB). The AHB master uses the programmed DMA address (OTG_HCDMAx register in host mode and OTG_DIEPDMAx/OTG_DOEPDMAx register in peripheral mode) to access the data buffers.
Channel initialization
The application must initialize one or more channels before it can communicate with connected devices. To initialize and enable a channel, the application must perform the following steps:
Halting a channel
The application can disable any channel by programming the OTG_HCCHARx register with the CHDIS and CHENA bits set to 1. This enables the OTG_FS/OTG_HS host to flush the posted requests (if any) and generates a channel halted interrupt. The application must wait for the CHH interrupt in OTG_HCINTx before reallocating the channel for other transactions. The OTG_FS/OTG_HS host does not interrupt the transaction that has already been started on the USB.
To disable a channel in DMA mode operation, the application does not need to check for space in the request queue. The OTG_HS host checks for space to write the disable
request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are dropped from the request queue when the CHDIS bit in OTG_HCCHARx is set to 1.
Before disabling a channel, the application must ensure that there is at least one free space available in the non-periodic request queue (when disabling a non-periodic channel) or the periodic request queue (when disabling a periodic channel). The application can simply flush the posted requests when the request queue is full (before disabling the channel), by programming the OTG_HCCHARx register with the CHDIS bit set to 1, and the CHENA bit cleared to 0.
The application is expected to disable a channel on any of the following conditions:
Ping protocol
When the OTG_HS host operates in high speed, the application must initiate the ping protocol when communicating with high-speed bulk or control (data and status stage) OUT endpoints.The application must initiate the ping protocol when it receives a NAK/NYET/TXERR interrupt. When the OTG_HS host receives one of the above responses, it does not continue any transaction for a specific endpoint, drops all posted or fetched OUT requests (from the request queue), and flushes the corresponding data (from the transmit FIFO).This is valid in slave mode only. In Slave mode, the application can send a ping token either by setting the DOPING bit in OTG_HCTSIZx before enabling the channel or by just writing the OTG_HCTSIZx register with the DOPING bit set when the channel is already enabled. This enables the OTG_HS host to write a ping request entry to the request queue. The application must wait for the response to the ping token (a NAK, ACK, or TXERR interrupt) before continuing the transaction or sending another ping token. The application can continue the data transaction only after receiving an ACK from the OUT endpoint for the requested ping. In DMA mode operation, the application does not need to set the DOPING bit in OTG_HCTSIZx for a NAK/NYET response in case of bulk/control OUT. The OTG_HS host automatically sets the DOPING bit in OTG_HCTSIZx, and issues the ping tokens for bulk/control OUT. The OTG_HS host continues sending ping tokens until it receives an ACK, and then switches automatically to the data transaction.
Operational model
The application must initialize a channel before communicating to the connected device. This section explains the sequence of operation to be performed for different types of USB transactions.
Writing the transmit FIFO
The OTG_FS/OTG_HS host automatically writes an entry (OUT request) to the periodic/non-periodic request queue, along with the last 32-bit word write of a packet. The application must ensure that at least one free space is available in the periodic/non-periodic request queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in 32-bit words. If the packet size is non-32-bit word aligned, the application must use padding. The OTG_FS/OTG_HS
host determines the actual packet size based on the programmed maximum packet size and transfer size.
| (omitted) |
Reading the receive FIFO
The application must ignore all packet statuses other than IN data packet (bx0010).
| (omitted) |
Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in Figure 521. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control SETUP transaction operates in the same way but has only one packet. The assumptions are:
Normal bulk and control OUT/SETUP operations
The sequence of operations in (channel 1) is as follows:
| (omitted) |
The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions is shown in the following code samples.
Unmask (NAK/TXERR/STALL/XFRC)
if (XFRC)
{
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (STALL)
{
Transfer Done = 1
Unmask CHH
Disable Channel
}
else if (NAK or TXERR )
{
Rewind Buffer Pointers
Unmask CHH
Disable Channel
if (TXERR)
{
Increment Error Count
Unmask ACK
}
else
{
Reset Error Count
}
}
else if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the data packets into the transmit FIFO when the space is available in the transmit FIFO and the request queue. The application can make use of the NPTXFE interrupt in OTG_GINTSTS to find the transmit FIFO space.
Unmask (TXERR/XFRC/BBERR/STALL/DTERR)
if (XFRC)
{
Reset Error Count
Unmask CHH
Disable Channel
Reset Error Count
Mask ACK
}
else if (TXERR or BBERR or STALL)
{
Unmask CHH
Disable Channel
if (TXERR)
{
Increment Error Count
Unmask ACK
}
}
else if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
else if (DTERR)
{
Reset Error Count
}
The application is expected to write the requests as and when the request queue space is available and until the XFRC interrupt is received.
Bulk and control IN transactions
A typical bulk or control IN pipelined transaction-level operation is shown in Figure 522. See channel 2 (ch_2). The assumptions are:
| (omitted) |
The sequence of operations is as follows:
Control transactions
Setup, data, and status stages of a control transfer must be performed as three separate transfers. setup-, data- or status-stage OUT transactions are performed similarly to the bulk OUT transactions explained previously. Data- or status-stage IN transactions are performed similarly to the bulk IN transactions explained previously. For all three stages, the application is expected to set the EPTYP field in OTG_HCCHAR1 to control. During the setup stage, the application is expected to set the PID field in OTG_HCTSIZ1 to SETUP.
Interrupt OUT transactions
A typical interrupt OUT operation is shown in Figure 523. The assumptions are:
The sequence of operations is as follows:
| (omitted) |
Unmask (NAK/TXERR/STALL/XFRC/FRMOR)
if (XFRC)
{
Reset Error Count
Mask ACK
De-allocate Channel
}
else
if (STALL or FRMOR)
{
Mask ACK
Unmask CHH
Disable Channel
if (STALL)
{
Transfer Done = 1
}
}
else
if (NAK or TXERR)
{
Rewind Buffer Pointers
Reset Error Count
Mask ACK
Unmask CHH
Disable Channel
}
else
if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else
if (ACK)
{
Reset Error Count
Mask ACK
}
The application uses the NPTXFE interrupt in OTG_GINTSTS to find the transmit FIFO space.
Interrupt IN
Unmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR)
if (XFRC)
{
Reset Error Count
Mask ACK
if (OTG_HCTSIZx.PKTCNT == 0)
{
De-allocate Channel
}
else
{
Transfer Done = 1
Unmask CHH
Disable Channel
}
}
else
if (STALL or FRMOR or NAK or DTERR or BBERR)
{
Mask ACK
Unmask CHH
Disable Channel
if (STALL or BBERR)
{
Reset Error Count
Transfer Done = 1
}
else
if (!FRMOR)
{
Reset Error Count
}
}
else
if (TXERR)
{
Increment Error Count
Unmask ACK
Unmask CHH
Disable Channel
}
else
if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
Re-initialize Channel (in next b_interval - 1 /Frame)
}
}
else
if (ACK)
{
Reset Error Count
Mask ACK
}
Interrupt IN transactions
The assumptions are:
Normal interrupt IN operation
The sequence of operations is as follows:
initializing the channel for the next transfer, if any). If PKTCNT bit in OTG_HCTSIZ2 = 0, reinitialize the channel for the next transfer. This time, the application must reset the ODDFRM bit in OTG_HCCHAR2.
| (omitted) |
Isochronous OUT transactions
A typical isochronous OUT operation is shown in Figure 524. The assumptions are:
packet size), starting with an odd frame. (transfer size = 1 024 bytes).
The sequence of operations is as follows:
| (omitted) |
Interrupt service routine for isochronous OUT/IN transactions
Code sample: isochronous OUT
Unmask (FRMOR/XFRC)
if (XFRC)
{
De-allocate Channel
}
else
if (FRMOR)
{
Unmask CHH
Disable Channel
}
else
if (CHH)
{
Mask CHH
De-allocate Channel
}
Code sample: Isochronous IN
Unmask (TXERR/XFRC/FRMOR/BBERR)
if (XFRC or FRMOR)
{
if (XFRC and (OTG_HCTSIZx.PKTCNT == 0))
{
Reset Error Count
De-allocate Channel
}
else
{
Unmask CHH
Disable Channel
}
}
else
if (TXERR or BBERR)
{
Increment Error Count
Unmask CHH
Disable Channel
}
else
if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
Isochronous IN transactions
The assumptions are:
The sequence of operations is as follows:
| (omitted) |
Selecting the queue depth
Choose the periodic and non-periodic request queue depths carefully to match the number of periodic/non-periodic endpoints accessed.
The non-periodic request queue depth affects the performance of non-periodic
transfers. The deeper the queue (along with sufficient FIFO size), the more often the core is able to pipeline non-periodic transfers. If the queue size is small, the core is able to put in new requests only when the queue space is freed up.
The core’s periodic request queue depth is critical to perform periodic transfers as scheduled. Select the periodic queue depth, based on the number of periodic transfers scheduled in a microframe. If the periodic request queue depth is smaller than the periodic transfers scheduled in a microframe, a frame overrun condition occurs.
Handling babble conditions
OTG_FS/OTG_HS controller handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more data than the maximum packet size for the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF).
When OTG_FS/OTG_HS controller detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already written data in the Rx buffer and generates a Babble interrupt to the application.
When OTG_FS/OTG_HS controller detects a port babble, it flushes the Rx FIFO and disables the port. The core then generates a port disabled interrupt (HPRTINT in OTG_GINTSTS, PENCHNG in OTG_HPRT). On receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the port disabled interrupt) by checking POCA in OTG_HPRT, then perform a soft reset. The core does not send any more tokens after it has detected a port babble condition.
Note: The following paragraphs, ranging from here to the beginning of Section 41.16, and
covering DMA configurations, apply only to USB OTG HS.
Bulk and control OUT/SETUP transactions in DMA mode
The sequence of operations is as follows:
| (omitted) |
The core does not generate a separate interrupt when NAK or NYET is received by the host functionality.
Bulk and control IN transactions in DMA mode
The sequence of operations is as follows:
| (omitted) |
| (omitted) |
Interrupt IN transactions in DMA mode
The sequence of operations (channelx) is as follows:
| (omitted) |
transfers, the OTG_HS host continues fetching the next packet (up to the value specified in the MC field) before switching to the next channel.
| (omitted) |
Isochronous IN transactions in DMA mode
The sequence of operations ((channel x) is as follows:
| (omitted) |
Bulk and control OUT/SETUP split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
Bulk/control IN split transactions in DMA mode
The sequence of operations (channel x) is as follows:
Interrupt OUT split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
Interrupt IN split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
Isochronous OUT split transactions in DMA mode
The sequence of operations (channel x) is as follows:
Isochronous IN split transactions in DMA mode
The sequence of operations (channel x) is as follows:
As soon as the packet is received successfully, the OTG_HS host starts writing the data to the system memory.
The OTG_HS host generates the CHH interrupt after transferring the received data to the system memory. In response to the CHH interrupt, de-allocate the channel or reinitialize the channel for the next start split.
Endpoint initialization on USB reset
At this point, all initialization required to receive SETUP packets is done.
Endpoint initialization on enumeration completion
At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0.
Endpoint initialization on SetAddress command
This section describes what the application must do when it receives a SetAddress command in a SETUP packet.
Endpoint initialization on SetConfiguration/SetInterface command
This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet.
At this point, the device core is configured to receive and transmit any type of data packet.
Endpoint activation
This section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type.
Endpoint deactivation
This section describes the steps required to deactivate an existing endpoint.
Note: The application must meet the following conditions to set up the device core to handle
traffic:
NPTXFEM and RXFLVLM in the OTG_GINTMSK register must be cleared.
Operational model
SETUP and OUT data transfers:
This section describes the internal data flow and application-level operations during data OUT transfers and SETUP transactions.
This section describes how to read packets (OUT data and SETUP packets) from the receive FIFO.
Figure 533 provides a flowchart of the above procedure.
| (omitted) |
SETUP transactions
This section describes how the core handles SETUP packets and the application’s sequence for handling SETUP transactions.
receive data FIFO to write SETUP data only, and never uses this space for data packets.
| (omitted) |
Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host can send to the same endpoint. When this condition occurs, the OTG_FS/OTG_HS controller generates an interrupt (B2BSTUP in OTG_DOEPINTx).
Internal data flow:
Application programming sequence:
The application must use this sequence to disable an OUT endpoint that it has enabled.
Application programming sequence:
This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt).
Application requirements:
Internal data flow:
Application programming sequence:
This section describes a regular isochronous OUT data transfer.
Application requirements:
Internal data flow:
Application programming sequence:
Read the OTG_DOEPTSIZx register to determine the size of the received transfer and to determine the validity of the data received in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met:
RXDPID = D2 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 3[HS]
The number of USB packets in which this payload was received =
Application programmed initial packet count – core updated final packet count
The application can discard invalid data packets.
This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core.
Internal data flow:
this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB.
Application programming sequence:
This section describes how the application can stall a non-isochronous endpoint.
When disabling the endpoint, instead of setting the SNAK bit in OTG_DOEPCTL, set STALL = 1 (in OTG_DOEPCTL).
The STALL bit always takes precedence over the NAK bit.
Examples
This section describes and depicts some fundamental transfer types and scenarios.
Figure 535 depicts the reception of a single Bulk OUT data packet from the USB to the AHB and describes the events involved in the process.
| (omitted) |
After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting CNAK = 1 and EPENA = 1 (in OTG_DOEPCTLx), and setting a suitable XFRSIZ and PKTCNT in the OTG_DOEPTSIZx register.
IN data transfers
This section describes how the application writes data packets to the endpoint FIFO when dedicated transmit FIFOs are enabled.
The application can write multiple packets for the same endpoint into the transmit FIFO, if space is available. For periodic IN endpoints, the application must write packets only for one microframe. It can write packets for the next periodic transaction only after getting transfer complete for the previous transaction.
Internal data flow:
Application programming sequence:
Use the following sequence to disable a specific IN endpoint that has been previously enabled.
Application programming sequence:
The application must poll the OTG_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point.
Application requirements:
To transmit a few maximum-packet-size packets and a short packet at the end of the transfer:
Transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp
If (sp > 0), then packet count[EPNUM] = x + 1. Otherwise, packet count[EPNUM] = x
Transfer size[EPNUM] = 0
Packet count[EPNUM] = 1
To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer into two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data packet alone.
First transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n;
Second transfer: transfer size[EPNUM] = 0; packet count = 1;
Internal data flow:
Application programming sequence:
This section describes a typical periodic IN data transfer.
Application requirements:
The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met:
transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp
(where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM])
If (sp > 0), packet count[EPNUM] = x + 1
Otherwise, packet count[EPNUM] = x;
MCNT[EPNUM] = packet count[EPNUM]
transfer size[EPNUM] = 0
packet count[EPNUM] = 1
MCNT[EPNUM] = packet count[EPNUM]
Internal data flow:
Application programming sequence:
This section describes what the application must do on an incomplete isochronous IN data transfer.
Internal data flow:
The application is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO. In this case, the application detects an IN token received when Tx FIFO empty interrupt in OTG_DIEPINTx. The application can ignore this interrupt, as it eventually results in an incomplete isochronous IN transfer interrupt (IISOIXFR in OTG_GINTSTS) at the end of periodic frame.
The core transmits a zero-length data packet on the USB in response to the received IN token.
Application programming sequence:
This section describes how the application can stall a non-isochronous endpoint.
Application programming sequence:
Special case: stalling the control OUT endpoint
The core must stall IN/OUT tokens if, during the data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must enable the ITTXFE interrupt in OTG_DIEPINTx and the OTEPDIS interrupt in OTG_DOEPINTx during the data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt.
When the OTG_FS/OTG_HS controller acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case response time depends on the AHB clock frequency.
The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token could come sooner. This worst case value is 7 PHY clocks when the AHB clock is the same as the PHY clock. When the AHB clock is faster, this value is smaller.
If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens. The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete isochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer interrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were dropped.
Choosing the value of TRDT in OTG_GUSBCFG
The value in TRDT (OTG_GUSBCFG) is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to get the FIFO status, and thus the first data from the PFC block. This time involves the synchronization delay between the PHY and AHB clocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. In this case, the delay is 5 clocks.
Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from the SPRAM and writes them into the dual clock source buffer. The MAC then reads the data out of the source buffer (4 deep).
If the AHB is running at a higher frequency than the PHY, the application can use a smaller value for TRDT (in OTG_GUSBCFG).
Figure 536 has the following signals:
To calculate the value of TRDT, refer to Table 296: TRDT values (FS) or Table 297: TRDT
values (HS).
| (omitted) |
The OTG_FS/OTG_HS controller is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When the core is connected to a “B” plug it is referred to as a B-device. In host mode, the OTG_FS/OTG_HS controller turns off VBUS to conserve power. SRP is a method by which the B-device signals the A-device to turn on VBUS power. A device must perform both data-line pulsing and VBUS
pulsing, but a host can detect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the B-device negotiates and switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role.
A-device session request protocol
The application must set the SRP-capable bit in the core USB configuration register. This enables the OTG_FS/OTG_HS controller to detect SRP as an A-device.
| (omitted) |
The following points refer and describe the signal numeration shown in the Figure 537:
B-device session request protocol
The application must set the SRP-capable bit in the core USB configuration register. This enables the OTG_FS/OTG_HS controller to initiate SRP as a B-device. SRP is a means by which the OTG_FS/OTG_HS controller can request a new session from the host.
| (omitted) |
The following points refer and describe the signal numeration shown in the Figure 538:
success status change bit in the OTG interrupt status register. The application reads the session request success bit in the OTG control and status register.
A-device host negotiation protocol
HNP switches the USB host role from the A-device to the B-device. The application must set the HNP-capable bit in the core USB configuration register to enable the OTG_FS/OTG_HS controller to perform HNP as an A-device.
| (omitted) |
The following points refer and describe the signal numeration shown in the Figure 539:
control and status register to indicate to the OTG_FS/OTG_HS controller that the B-device supports HNP.
When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP. The B-device initiates HNP only when it must switch to the host role; otherwise, the bus continues to be suspended.
The OTG_FS/OTG_HS controller sets the host negotiation detected interrupt in the OTG interrupt status register, indicating the start of HNP.
The OTG_FS/OTG_HS controller deasserts the DM pull down and DM pull down in the PHY to indicate a device role. The PHY enables the OTG_DP pull-up resistor to indicate a connect for B-device.
The application must read the current mode bit in the OTG control and status register to determine device mode operation.
The B-device continues the host role, initiating traffic, and suspends the bus when done.
The OTG_FS/OTG_HS controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. Following this, the OTG_FS/OTG_HS controller sets the USB suspend bit in the core interrupt register.
B-device host negotiation protocol
HNP switches the USB host role from B-device to A-device. The application must set the HNP-capable bit in the core USB configuration register to enable the OTG_FS/OTG_HS controller to perform HNP as a B-device.
| (omitted) |
The following points refer and describe the signal numeration shown in the Figure 540:
The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The OTG_FS/OTG_HS controller’s ACK response indicates that it supports HNP. The application must set the device HNP enable bit in the OTG control and status register to indicate HNP support.
The application sets the HNP request bit in the OTG control and status register to indicate to the OTG_FS/OTG_HS controller to initiate HNP.
When it has finished using the bus, the A-device suspends by writing the port suspend bit in the host port control and status register.
The OTG_FS/OTG_HS controller sets the Early suspend bit in the core interrupt register after 3 ms of bus idleness. Following this, the OTG_FS/OTG_HS controller sets the USB suspend bit in the core interrupt register.
The OTG_FS/OTG_HS controller disconnects and the A-device detects SE0 on the bus, indicating HNP. The OTG_FS/OTG_HS controller asserts the DP pull down and DM pull down in the PHY to indicate its assumption of the host role.
The A-device responds by activating its OTG_DP pull-up resistor within 3 ms of detecting SE0. The OTG_FS/OTG_HS controller detects this as a connect.
The OTG_FS/OTG_HS controller sets the host negotiation success status change interrupt in the OTG interrupt status register, indicating the HNP status. The application must read the host negotiation success bit in the OTG control and status register to
determine host negotiation success. The application must read the current Mode bit in the core interrupt register (OTG_GINTSTS) to determine host mode operation.
Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission.
The Ethernet peripheral enables the STM32F76xxx and STM32F77xxx to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard.
The Ethernet provides a configurable, flexible peripheral to meet the needs of various applications and customers. It supports two industry standard interfaces to the external physical layer (PHY): the default media independent interface (MII) defined in the IEEE 802.3 specifications and the reduced media independent interface (RMII). It can be used in number of applications such as switches, network interface cards, etc.
The Ethernet is compliant with the following standards:
The Ethernet (ETH) peripheral includes the following features, listed by category:
Store-and-Forward mode
Table 300 shows the MAC signals and the corresponding MII/RMII signal mapping. All MAC signals are mapped onto AF11, some signals are mapped onto different I/O pins, and should be configured in Alternate function mode (for more details, refer to Section 6.3.2: I/O
pin alternate function multiplexer and mapping and the corresponding datasheet).
| AF11 |
|---|
| ETH |
| ETH_MII_CRS |
| ETH_MII _RX_CLK / ETH_RMII _REF_CLK |
| ETH _MDIO |
| ETH _MII_COL |
| ETH_MII _RX_DV / ETH_RMII _CRS_DV |
| ETH _MII_RXD2 |
| ETH _MII_RXD3 |
| ETH _PPS_OUT |
| ETH _MII_TXD3 |
| ETH_ MII_RX_ER |
| ETH _MII_TX_EN / ETH _RMII_TX_EN |
| ETH _MII_TXD0 / ETH _RMII_TXD0 |
| ETH _MII_TXD1 / ETH _RMII_TXD1 |
| ETH _MDC |
| ETH _MII_TXD2 |
| ETH _MII_TX_CLK |
| ETH_MII_RXD0 / ETH_RMII_RXD0 |
| ETH _MII_RXD1/ ETH _RMII_RXD1 |
| ETH_MII_TXD3 |
| ETH_PPS_OUT |
| ETH _MII_TX_EN / ETH _RMII_TX_EN |
| ETH _MII_TXD0 / ETH _RMII_TXD0 |
| ETH _MII_TXD1 / ETH _RMII_TXD1 |
| ETH _MII_CRS |
| ETH _MII_COL |
| ETH _MII_RXD2 |
| ETH _MII_RXD3 |
| ETH _MII_RX_ER |
The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated DMA controller. It supports both default media-independent interface (MII) and reduced media-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC register).
The DMA controller interfaces with the Core and memories through the AHB Master and Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of configuration registers permit the user to select the desired mode and features for the MAC and the DMA controller.
Note: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
| (omitted) |
The station management interface (SMI) allows the application to access any PHY registers through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
The application can select one of the 32 PHYs and one of the 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be addressed at any given time.
Both the MDC clock line and the MDIO data line are implemented as alternate function I/O in the microcontroller:
160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI management interface drives the MDC clock signal low.
| (omitted) |
SMI frame format
The frame structure related to a read or write operation is shown in Table 301, the order of bit transmission must be from left to right.
| - |
Management frame fields |
|||||||
|---|---|---|---|---|---|---|---|---|
| Preamble (32 bits) | Start | Operation | PADDR | RADDR | TA | Data (16 bits) | Idle |
|
| Read | 1... 1 | 01 | 10 | ppppp | rrrrr | Z0 | ddddddddddddddd | Z |
| Write | 1... 1 | 01 | 01 | ppppp | rrrrr | 10 | ddddddddddddddd | Z |
The management frame consists of eight fields:
For a write transaction, the MAC controller drives a <10> pattern during the TA field. The PHY device must drive a high-impedance state for the 2 bits of TA.
SMI write operation
When the application sets the MII Write and Busy bits (in Ethernet MAC MII address register
(ETH_MACMIIAR)), the SMI initiates a write operation into the PHY registers by transferring the PHY address, the register address in PHY, and the write data (in Ethernet MAC MII data
register (ETH_MACMIIDR). The application should not change the MII Address register contents or the MII Data register while the transaction is ongoing. Write operations to the MII Address register or the MII Data Register during this period are ignored (the Busy bit is high), and the transaction is completed without any error. After the Write operation has completed, the SMI indicates this by resetting the Busy bit.
Figure 543 shows the frame format for the write operation.
| (omitted) |
SMI read operation
When the user sets the MII Busy bit in the Ethernet MAC MII address register (ETH_MACMIIAR) with the MII Write bit at 0, the SMI initiates a read operation in the PHY registers by transferring the PHY address and the register address in PHY. The application should not change the MII Address register contents or the MII Data register while the transaction is ongoing. Write operations to the MII Address register or MII Data Register during this period are ignored (the Busy bit is high) and the transaction is completed without any error. After the read operation has completed, the SMI resets the Busy bit and then updates the MII Data register with the data read from the PHY.
Figure 544 shows the frame format for the read operation.
| (omitted) |
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock whose source is the application clock (AHB clock). The divide factor depends on the clock range setting in the MII Address register.
Table 302 shows how to set the clock ranges.
| Selection | HCLK clock | MDC clock |
|---|---|---|
| 000 | 60-100 MHz | AHB clock / 42 |
| 001 | 100-150 MHz | AHB clock / 62 |
| 010 | 20-35 MHz | AHB clock / 16 |
| 011 | 35-60 MHz | AHB clock / 26 |
| 100 | 150-216 MHz | AHB clock / 102 |
| 101, 110, 111 | Reserved | - |
The media-independent interface (MII) defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
| (omitted) |
deasserted and MII_RX_ER is asserted, a specific MII_RXD[3:0] value is used to transfer specific information from the PHY (see Table 304).
| MII_TX_EN | MII_TXD[3:0] | Description |
|---|---|---|
| 0 | 0000 through 1111 | Normal inter-frame |
| 1 | 0000 through 1111 | Normal data transmission |
| MII_RX_DV | MII_RX_ERR | MII_RXD[3:0] | Description |
|---|---|---|---|
| 0 | 0 | 0000 through 1111 | Normal inter-frame |
| 0 | 1 | 0000 | Normal inter-frame |
| 0 | 1 | 0001 through 1101 | Reserved |
| 0 | 1 | 1110 | False carrier indication |
| 0 | 1 | 1111 | Reserved |
| 1 | 0 | 0000 through 1111 | Normal data reception |
| 1 | 1 | 0000 through 1111 | Data reception with errors |
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked with an external 25 MHz as shown in Figure 546. Instead of using an external 25 MHz quartz to provide this clock, the STM32F76xxx and STM32F77xxx microcontrollers can output this signal on its MCO pin. In this case, the PLL multiplier has to be configured so as to get the desired frequency on the MCO pin, from the 25 MHz external quartz.
| (omitted) |
The reduced media-independent interface (RMII) specification reduces the pin count between the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s. According to the IEEE 802.3u standard, an MII contains 16 pins for data and control. The RMII specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin count).
The RMII is instantiated between the MAC and the PHY. This helps translation of the MAC’s MII into the RMII. The RMII block has the following characteristics:
| (omitted) |
RMII clock sources
Either clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to generate the 50 MHz frequency.
| (omitted) |
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the SYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s operations is described in Figure 549.
| (omitted) |
To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed on the same GPIO pin.
The IEEE 802.3 International Standard for local area networks (LANs) employs the CSMA/CD (carrier sense multiple access with collision detection) as the access method.
The Ethernet peripheral consists of a MAC 802.3 (media access control) controller with media independent interface (MII) and a dedicated DMA controller.
The MAC block implements the LAN CSMA/CD sublayer for the following families of systems: 10 Mbit/s and 100 Mbit/s of data rates for baseband and broadband systems. Half- and full-duplex operation modes are supported. The collision detection access method is applied only to the half-duplex operation mode. The MAC control frame sublayer is supported.
The MAC sublayer performs the following functions associated with a data link control procedure:
Basically there are two operating modes of the MAC sublayer:
The MAC block implements the MAC sublayer and the optional MAC control sublayer (10/100 Mbit/s) as specified by the IEEE 802.3-2002 standard.
Two frame formats are specified for data communication systems using the CSMA/CD MAC:
Figure 551 and Figure 552 describe the frame structure (untagged and tagged) that includes the following fields:
Preamble: 7-byte field used for synchronization purposes (PLS circuitry)
Hexadecimal value: 55-55-55-55-55-55-55
Bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission)
Start frame delimiter (SFD): 1-byte field used to indicate the start of a frame. Hexadecimal value: D5
Bit pattern: 11010101 (right-to-left bit transmission)
The address designation is based on the following types:
| (omitted) |
hexadecimal). This constant field is used to distinguish tagged and untagged MAC frames.
MAC client length/type: 2-byte field with different meaning (mutually exclusive), depending on its value:
Regardless of the interpretation of the length/type field, if the length of the data field is less than the minimum required for proper operation of the protocol, a PAD field is added after the data field but prior to the FCS (frame check sequence) field. The length/type field is transmitted and received with the higher-order byte first.
For length/type field values in the range between maxValidLength and minTypeValue (boundaries excluded), the behavior of the MAC sublayer is not specified: they may or may not be passed by the MAC sublayer.
Data and PAD fields: n-byte data field. Full data transparency is provided, it means that any arbitrary sequence of byte values may appear in the data field. The size of the PAD, if any, is determined by the size of the data field. Max and min length of the data and PAD field are:
When the data field length is less than the minimum required, the PAD field is added to match the minimum length (42 bytes for tagged frames, 46 bytes for untagged frames).
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
The CRC value of a frame is computed as follows:
| (omitted) |
| (omitted) |
Each byte of the MAC frame, except the FCS field, is transmitted low-order bit first.
An invalid MAC frame is defined by one of the following conditions:
The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frames are then popped out and transferred to the MAC core. When the end-of-frame is transferred, the status of the transmission is taken from the MAC core and transferred back to the DMA. The Transmit FIFO has a depth of 2 Kbyte. FIFO-fill level is indicated to the DMA so that it can initiate a data fetch in required bursts from the system memory, using the AHB interface. The data from the AHB Master interface is pushed into the FIFO.
When the SOF is detected, the MAC accepts the data and begins transmitting to the MII. The time required to transmit the frame data to the MII after the application initiates transmission is variable, depending on delay factors like IFG delay, time to transmit preamble/SFD, and any back-off delays for Half-duplex mode. After the EOF is transferred to the MAC core, the core completes normal transmission and then gives the status of transmission back to the DMA. If a normal collision (in Half-duplex mode) occurs during transmission, the MAC core makes the transmit status valid, then accepts and drops all further data until the next SOF is received. The same frame should be retransmitted from SOF on observing a Retry request (in the Status) from the MAC. The MAC issues an underflow status if the data are not provided continuously during the transmission. During the normal transfer of a frame, if the MAC receives an SOF without getting an EOF for the previous frame, then the SOF is ignored and the new frame is considered as the continuation of the previous frame.
There are two modes of operation for popping data towards the MAC core:
The application can flush the Transmit FIFO of all contents by setting the FTF (ETH_DMAOMR register [20]) bit. This bit is self-clearing and initializes the FIFO pointers to the default state. If the FTF bit is set during a frame transfer to the MAC core, then transfer is stopped as the FIFO is considered to be empty. Hence an underflow event occurs at the MAC transmitter and the corresponding Status word is forwarded to the DMA.
Automatic CRC and pad generation
When the number of bytes received from the application falls below 60 (DA+SA+LT+Data), zeros are appended to the transmitting frame to make the data length exactly 46 bytes to meet the minimum data field requirement of IEEE 802.3. The MAC can be programmed not to append any padding. The cyclic redundancy check (CRC) for the frame check sequence (FCS) field is calculated and appended to the data being transmitted. When the MAC is programmed to not append the CRC value to the end of Ethernet frames, the computed CRC is not transmitted. An exception to this rule is that when the MAC is programmed to append pads for frames (DA+SA+LT+Data) less than 60 bytes, CRC will be appended at the end of the padded frames.
The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following polynomial.
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
Transmit protocol
The MAC controls the operation of Ethernet frame transmission. It performs the following functions to meet the IEEE 802.3/802.3z specifications. It:
When a new frame transmission is requested, the MAC sends out the preamble and SFD, followed by the data. The preamble is defined as 7 bytes of 0b10101010 pattern, and the SFD is defined as 1 byte of 0b10101011 pattern. The collision window is defined as 1 slot time (512 bit times for 10/100 Mbit/s Ethernet). The jam pattern generation is applicable only to Half-duplex mode, not to Full-duplex mode.
In MII mode, if a collision occurs at any time from the beginning of the frame to the end of the CRC field, the MAC sends a 32-bit jam pattern of 0x5555 5555 on the MII to inform all other stations that a collision has occurred. If the collision is seen during the preamble transmission phase, the MAC completes the transmission of the preamble and SFD and then sends the jam pattern.
A jabber timer is maintained to cut off the transmission of Ethernet frames if more than 2048 (default) bytes have to be transferred. The MAC uses the deferral mechanism for flow control (back pressure) in Half-duplex mode. When the application requests to stop receiving frames, the MAC sends a JAM pattern of 32 bytes whenever it senses the reception of a frame, provided that transmit flow control is enabled. This results in a collision and the remote station backs off. The application requests flow control by setting the BPA bit (bit 0) in the ETH_MACFCR register. If the application requests a frame to be transmitted, then it is scheduled and transmitted even when back pressure is activated. Note that if back pressure is kept activated for a long time (and more than 16 consecutive collision events occur) then the remote stations abort their transmissions due to excessive collisions. If IEEE 1588 time stamping is enabled for the transmit frame, this block takes a snapshot of the system time when the SFD is put onto the transmit MII bus.
Transmit scheduler
The MAC is responsible for scheduling the frame transmission on the MII. It maintains the interframe gap between two transmitted frames and follows the truncated binary exponential backoff algorithm for Half-duplex mode. The MAC enables transmission after satisfying the IFG and backoff delays. It maintains an idle period of the configured interframe gap (IFG bits in the ETH_MACCR register) between any two transmitted frames. If frames to be transmitted arrive sooner than the configured IFG time, the MII waits for the enable signal from the MAC before starting the transmission on it. The MAC starts its IFG counter as soon as the carrier signal of the MII goes inactive. At the end of the programmed IFG value, the MAC enables transmission in Full-duplex mode. In Half-duplex mode and when IFG is
configured for 96 bit times, the MAC follows the rule of deference specified in Section 4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval. If the carrier is detected during the final one third of the IFG interval, the MAC continues the IFG count and enables the transmitter after the IFG interval. The MAC implements the truncated binary exponential backoff algorithm when it operates in Half-duplex mode.
Transmit flow control
When the Transmit Flow Control Enable bit (TFE bit in ETH_MACFCR) is set, the MAC generates Pause frames and transmits them as necessary, in Full-duplex mode. The Pause frame is appended with the calculated CRC, and is sent. Pause frame generation can be initiated in two ways.
A pause frame is sent either when the application sets the FCB bit in the ETH_MACFCR register or when the receive FIFO is full (packet buffer).
Single-packet transmit operation
The general sequence of events for a transmit operation is as follows:
Transmit operation—Two packets in the buffer
frame is being transmitted. As soon as the first frame has been transferred and the status is received from the MAC, it is pushed to the DMA. If the DMA has already completed sending the second packet to the FIFO, the second transmission must wait for the status of the first packet before proceeding to the next frame.
Retransmission during collision
While a frame is being transferred to the MAC, a collision event may occur on the MAC line interface in Half-duplex mode. The MAC would then indicate a retry attempt by giving the status even before the end of frame is received. Then the retransmission is enabled and the frame is popped out again from the FIFO. After more than 96 bytes have been popped towards the MAC core, the FIFO controller frees up that space and makes it available to the DMA to push in more data. This means that the retransmission is not possible after this threshold is crossed or when the MAC core indicates a late collision event.
Transmit FIFO flush operation
The MAC provides a control to the software to flush the Transmit FIFO through the use of Bit 20 in the Operation mode register. The Flush operation is immediate and the Tx FIFO and the corresponding pointers are cleared to the initial state even if the Tx FIFO is in the middle of transferring a frame to the MAC Core. This results in an underflow event in the MAC transmitter, and the frame transmission is aborted. The status of such a frame is marked with both underflow and frame flush events (TDES0 bits 13 and 1). No data are coming to the FIFO from the application (DMA) during the Flush operation. Transfer transmit status words are transferred to the application for the number of frames that is flushed (including partial frames). Frames that are completely flushed have the Frame flush status bit (TDES0 13) set. The Flush operation is completed when the application (DMA) has accepted all of the Status words for the frames that were flushed. The Transmit FIFO Flush control register bit is then cleared. At this point, new frames from the application (DMA) are accepted. All data presented for transmission after a Flush operation are discarded unless they start with an SOF marker.
Transmit status word
At the end of the Ethernet frame transfer to the MAC core and after the core has completed the transmission of the frame, the transmit status is given to the application. The detailed description of the Transmit Status is the same as for bits [23:0] in TDES0. If IEEE 1588 time stamping is enabled, a specific frames’ 64-bit time stamp is returned, along with the transmit status.
Transmit checksum offload
Communication protocols such as TCP and UDP implement checksum fields, which helps determine the integrity of data transmitted over a network. Because the most widespread use of Ethernet is to encapsulate TCP and UDP over IP datagrams, the Ethernet controller has a transmit checksum offload feature that supports checksum calculation and insertion in the transmit path, and error detection in the receive path. This section explains the operation of the checksum offload feature for transmitted frames.
Note: The checksum for TCP, UDP or ICMP is calculated over a complete frame, then inserted
into its corresponding header field. Due to this requirement, this function is enabled only
when the Transmit FIFO is configured for Store-and-forward mode (that is, when the TSF bit
is set in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut-through) mode, the Transmit checksum offload is bypassed.
The user must make sure the Transmit FIFO is deep enough to store a complete frame
before that frame is transferred to the MAC Core transmitter. If the FIFO depth is less than
the input Ethernet frame size, the payload (TCP/UDP/ICMP) checksum insertion function is
bypassed and only the frame’s IPv4 Header checksum is modified, even in Store-and-forward mode.
The transmit checksum offload supports two types of checksum calculation and insertion. This checksum can be controlled for each frame by setting the CIC bits (Bits 28:27 in TDES1, described in TDES1: Transmit descriptor Word1 on page 1818).
See IETF specifications RFC 791, RFC 793, RFC 768, RFC 792, RFC 2460 and RFC 4443 for IPv4, TCP, UDP, ICMP, IPv6 and ICMPv6 packet header specifications, respectively.
IP header checksum
In IPv4 datagrams, the integrity of the header fields is indicated by the 16-bit header checksum field (the eleventh and twelfth bytes of the IPv4 datagram). The checksum offload detects an IPv4 datagram when the Ethernet frame’s Type field has the value 0x0800 and the IP datagram’s Version field has the value 0x4. The input frame’s checksum field is ignored during calculation and replaced by the calculated value. IPv6 headers do not have a checksum field; thus, the checksum offload does not modify IPv6 header fields. The result of this IP header checksum calculation is indicated by the IP Header Error status bit in the Transmit status (Bit 16). This status bit is set whenever the values of the Ethernet Type field and the IP header’s Version field are not consistent, or when the Ethernet frame does not have enough data, as indicated by the IP header Length field. In other words, this bit is set when an IP header error is asserted under the following circumstances:
TCP/UDP/ICMP checksum
The TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including extension headers) and determines whether the encapsulated payload is TCP, UDP or ICMP.
that:
The checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its corresponding field in the header. It can work in the following two modes:
that: for ICMP-over-IPv4 packets, the checksum field in the ICMP packet must
always be 0x0000 in both modes, because pseudo-headers are not defined for such packets. If it does not equal 0x0000, an incorrect checksum may be inserted into the packet.
The result of this operation is indicated by the payload checksum error status bit in the Transmit Status vector (bit 12). The payload checksum error status bit is set when either of the following is detected:
When the packet is longer than the indicated payload length, the bytes are ignored as stuff bytes, and no error is reported. When the first type of error is detected, the TCP, UDP or ICMP header is not modified. For the second error type, still, the calculated checksum is inserted into the corresponding header field.
MII/RMII transmit bit order
Each nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit transmission shown in Figure 553. Lower order bits (D1 and D0) are transmitted first followed by higher order bits (D2 and D3).
| (omitted) |
MII/RMII transmit timing diagrams
| (omitted) |
| (omitted) |
Figure 556 shows a frame transmission in MII and RMII.
| (omitted) |
The MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is indicated to the DMA once it crosses the configured receive threshold (RTC in the ETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers towards the AHB interface.
In the default Cut-through mode, when 64 bytes (configured with the RTC bits in the ETH_DMAOMR register) or a full packet of data are received into the FIFO, the data are popped out and the DMA is notified of its availability. Once the DMA has initiated the transfer to the AHB interface, the data transfer continues from the FIFO until a complete
packet has been transferred. Upon completion of the EOF frame transfer, the status word is popped out and sent to the DMA controller.
In Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR register), a frame is read out only after being written completely into the Receive FIFO. In this mode, all error frames are dropped (if the core is configured to do so) such that only valid frames are read out and forwarded to the application. In Cut-through mode, some error frames are not dropped, because the error status is received at the end of the frame, by which time the start of that frame has already been read out of the FIFO.
A receive operation is initiated when the MAC detects an SFD on the MII. The core strips the preamble and SFD before proceeding to process the frame. The header fields are checked for the filtering and the FCS field used to verify the CRC for the frame. The frame is dropped in the core if it fails the address filter.
Receive protocol
The received frame preamble and SFD are stripped. Once the SFD has been detected, the MAC starts sending the Ethernet frame data to the receive FIFO, beginning with the first byte following the SFD (destination address). If IEEE 1588 time stamping is enabled, a snapshot of the system time is taken when any frame's SFD is detected on the MII. Unless the MAC filters out and drops the frame, this time stamp is passed on to the application.
If the received frame length/type field is less than 0x600 and if the MAC is programmed for the auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to the count specified in the length/type field, then starts dropping bytes (including the FCS field). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received Ethernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip option. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes (DA + SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by programming the watchdog disable (WD) bit in the MAC configuration register. However, even if the watchdog timer is disabled, frames greater than 16 KB in size are cut off and a watchdog timeout status is given.
Receive CRC: automatic CRC and pad stripping
The MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for the received frame that includes the Destination address field through the FCS field. The encoding is defined by the following polynomial.
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
Regardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the CRC check for the received frame.
Receive checksum offload
Both IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for data integrity. The user can enable the receive checksum offload by setting the IPCO bit in the ETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for value 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This identification applies to VLAN-tagged frames as well. The receive checksum offload calculates IPv4 header checksums and checks that they match the received IPv4 header checksums. The IP Header Error bit is set for any mismatch between the indicated payload
type (Ethernet Type field) and the IP header version, or when the received frame does not have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 bytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies a TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications. It includes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation and checks whether the received checksum field matches the calculated value. The result of this operation is given as a Payload Checksum Error bit in the receive status word. This status bit is also set if the length of the TCP, UDP or ICMP payload does not match the expected payload length given in the IP header. As mentioned in TCP/UDP/ICMP checksum on
page 1786, the receive checksum offload bypasses the payload of fragmented IP datagrams, IP datagrams with security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP. This information (whether the checksum is bypassed or not) is given in the receive status, as described in the RDES0: Receive descriptor Word0 section. In this configuration, the core does not append any payload checksum bytes to the received Ethernet frames.
As mentioned in RDES0: Receive descriptor Word0 on page 1825, the meaning of certain register bits changes as shown in Table 305.
|
|
Header checksum error |
Payload checksum error |
Frame status |
|---|---|---|---|
| 0 | 0 | 0 | The frame is an IEEE 802.3 frame (Length field value is less than 0x0600). |
| 1 | 0 | 0 | IPv4/IPv6 Type frame in which no checksum error is detected. |
| 1 | 0 | 1 |
IPv4/IPv6 Type frame in which a payload checksum error (as described for PCE) is detected |
| 1 | 1 | 0 |
IPv4/IPv6 Type frame in which IP header checksum error (as described for IPCO HCE) is detected. |
| 1 | 1 | 1 | IPv4/IPv6 Type frame in which both PCE and IPCO HCE are detected. |
| 0 | 0 | 1 |
IPv4/IPv6 Type frame in which there is no IP HCE and the payload check is bypassed due to unsupported payload. |
| 0 | 1 | 1 |
Type frame which is neither IPv4 or IPv6 (checksum offload bypasses the checksum check completely) |
| 0 | 1 | 0 | Reserved |
Receive frame controller
If the RA bit is reset in the MAC CSR frame filter register, the MAC performs frame filtering based on the destination/source address (the application still needs to perform another level of filtering if it decides not to receive any bad frames like runt, CRC error frames, etc.). On detecting a filter-fail, the frame is dropped and not transferred to the application. When the filtering parameters are changed dynamically, and in case of (DA-SA) filter-fail, the rest of
the frame is dropped and the Rx Status Word is immediately updated (with zero frame length, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down mode, all received frames are dropped, and are not forwarded to the application.
Receive flow control
The MAC detects the receiving Pause frame and pauses the frame transmission for the delay specified within the received Pause frame (only in Full-duplex mode). The Pause frame detection function can be enabled or disabled with the RFCE bit in ETH_MACFCR. Once receive flow control has been enabled, the received frame destination address begins to be monitored for any match with the multicast address of the control frame (0x0180 C200 0001). If a match is detected (the destination address of the received frame matches the reserved control frame destination address), the MAC then decides whether or not to transfer the received control frame to the application, based on the level of the PCF bit in ETH_MACFFR.
The MAC also decodes the type, opcode, and Pause Timer fields of the receiving control frame. If the byte count of the status indicates 64 bytes, and if there is no CRC error, the MAC transmitter pauses the transmission of any data frame for the duration of the decoded Pause time value, multiplied by the slot time (64 byte times for both 10/100 Mbit/s modes). Meanwhile, if another Pause frame is detected with a zero Pause time value, the MAC resets the Pause time and manages this new pause request.
If the received control frame matches neither the type field (0x8808), the opcode (0x00001), nor the byte length (64 bytes), or if there is a CRC error, the MAC does not generate a Pause.
In the case of a pause frame with a multicast destination address, the MAC filters the frame based on the address match.
For a pause frame with a unicast destination address, the MAC filtering depends on whether the DA matched the contents of the MAC address 0 register and whether the UPDF bit in ETH_MACFCR is set (detecting a pause frame even with a unicast destination address). The PCF register bits (bits [7:6] in ETH_MACFFR) control filtering for control frames in addition to address filtering.
Receive operation multiframe handling
Since the status is available immediately following the data, the FIFO is capable of storing any number of frames into it, as long as it is not full.
Error handling
If the Rx FIFO is full before it receives the EOF data from the MAC, an overflow is declared and the whole frame is dropped, and the overflow counter in the (ETH_DMAMFBOCR register) is incremented. The status indicates a partial frame due to overflow. The Rx FIFO can filter error and undersized frames, if enabled (using the FEF and FUGF bits in ETH_DMAOMR).
If the Receive FIFO is configured to operate in Store-and-forward mode, all error frames can be filtered and dropped.
In Cut-through mode, if a frame's status and length are available when that frame's SOF is read from the Rx FIFO, then the complete erroneous frame can be dropped. The DMA can flush the error frame being read from the FIFO, by enabling the receive frame flash bit. The data transfer to the application (DMA) is then stopped and the rest of the frame is internally read and dropped. The next frame transfer can then be started, if available.
Receive status word
At the end of the Ethernet frame reception, the MAC outputs the receive status to the application (DMA). The detailed description of the receive status is the same as for bits[31:0] in RDES0, given in RDES0: Receive descriptor Word0.
Frame length interface
In case of switch applications, data transmission and reception between the application and MAC happen as complete frame transfers. The application layer should be aware of the length of the frames received from the ingress port in order to transfer the frame to the egress port. The MAC core provides the frame length of each received frame inside the status at the end of each frame reception.
Note: A frame length value of 0 is given for partial frames written into the Rx FIFO due to overflow.
MII/RMII receive bit order
Each nibble is transmitted to the MII from the dibit received from the RMII in the nibble transmission order shown in Figure 557. The lower-order bits (D0 and D1) are received first, followed by the higher-order bits (D2 and D3).
| (omitted) |
| (omitted) |
| (omitted) |
| (omitted) |
Interrupts can be generated from the MAC core as a result of various events.
The ETH_MACSR register describes the events that can cause an interrupt from the MAC core. The user can prevent each event from asserting the interrupt by setting the corresponding mask bits in the Interrupt Mask register.
The interrupt register bits only indicate the block from which the event is reported. The user has to read the corresponding status registers and other registers to clear the interrupt. For example, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on-LAN frame is received in Power-down mode. The user must read the ETH_MACPMTCSR Register to clear this interrupt event.
| (omitted) |
Address filtering
Address filtering checks the destination and source addresses on all received frames and the address filtering status is reported accordingly. Address checking is based on different parameters (Frame filter register) chosen by the application. The filtered frame can also be identified: multicast or broadcast frame.
Address filtering uses the station's physical (MAC) address and the Multicast Hash table for address checking purposes.
Unicast destination address filter
The MAC supports up to 4 MAC addresses for unicast perfect filtering. If perfect filtering is selected (HU bit in the Frame filter register is reset), the MAC compares all 48 bits of the received unicast address with the programmed MAC address for any match. Default MacAddr0 is always enabled, other addresses MacAddr1–MacAddr3 are selected with an individual enable bit. Each byte of these other addresses (MacAddr1–MacAddr3) can be masked during comparison with the corresponding received DA byte by setting the corresponding Mask Byte Control bit in the register. This helps group address filtering for the DA. In Hash filtering mode (when HU bit is set), the MAC performs imperfect filtering for unicast addresses using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper CRC (see note 1 below) bits of the received destination address to index the content of the Hash table. A value of 000000 selects bit 0 in the selected register, and a value of 111111 selects bit 63 in the Hash Table register. If the corresponding bit (indicated by the 6-bit CRC)
is set to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has failed the Hash filter.
Note: This CRC is a 32-bit value coded by the following polynomial (for more details refer to
Section 42.5.3: MAC frame reception):
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
Multicast destination address filter
The MAC can be programmed to pass all multicast frames by setting the PAM bit in the Frame filter register. If the PAM bit is reset, the MAC performs the filtering for multicast addresses based on the HM bit in the Frame filter register. In Perfect filtering mode, the multicast address is compared with the programmed MAC destination address registers (1–3). Group address filtering is also supported. In Hash filtering mode, the MAC performs imperfect filtering using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper CRC (see note 1 below) bits of the received multicast address to index the content of the Hash table. A value of 000000 selects bit 0 in the selected register and a value of 111111 selects bit 63 in the Hash Table register. If the corresponding bit is set to 1, then the multicast frame is said to have passed the Hash filter; otherwise, the frame has failed the Hash filter.
Note: This CRC is a 32-bit value coded by the following polynomial (for more details refer to
Section 42.5.3: MAC frame reception):
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
Hash or perfect address filter
The DA filter can be configured to pass a frame when its DA matches either the Hash filter or the Perfect filter by setting the HPF bit in the Frame filter register and setting the corresponding HU or HM bits. This configuration applies to both unicast and multicast frames. If the HPF bit is reset, only one of the filters (Hash or Perfect) is applied to the received frame.
Broadcast address filter
The MAC does not filter any broadcast frames in the default mode. However, if the MAC is programmed to reject all broadcast frames by setting the BFD bit in the Frame filter register, any broadcast frames are dropped.
Unicast source address filter
The MAC can also perform perfect filtering based on the source address field of the received frames. By default, the MAC compares the SA field with the values programmed in the SA registers. The MAC address registers [1:3] can be configured to contain SA instead of DA for comparison, by setting bit 30 in the corresponding register. Group filtering with SA is also supported. The frames that fail the SA filter are dropped by the MAC if the SAF bit in the Frame filter register is set. Otherwise, the result of the SA filter is given as a status bit in the Receive Status word (see RDES0: Receive descriptor Word0).
When the SAF bit is set, the result of the SA and DA filters is AND’ed to decide whether the frame needs to be forwarded. This means that either of the filter fail result will drop the frame. Both filters have to pass the frame for the frame to be forwarded to the application.
Inverse filtering operation
For both destination and source address filtering, there is an option to invert the filter-match result at the final output. These are controlled by the DAIF and SAIF bits in the Frame filter register, respectively. The DAIF bit is applicable for both Unicast and Multicast DA frames. The result of the unicast/multicast destination address filter is inverted in this mode. Similarly, when the SAIF bit is set, the result of the unicast SA filter is inverted. Table 306
and Table 307 summarize destination and source address filtering based on the type of frame received.
| Frame type | PM | HPF | HU | DAIF | HM | PAM | DB | DA filter operation |
|---|---|---|---|---|---|---|---|---|
| Broadcast |
1 | X | X | X | X | X | X | Pass |
| 0 | X | X | X | X | X | 0 | Pass |
|
| 0 | X | X | X | X | X | 1 | Fail |
|
| Unicast |
1 | X | X | X | X | X | X | Pass all frames |
| 0 | X | 0 | 0 | X | X | X | Pass on perfect/group filter match |
|
| 0 | X | 0 | 1 | X | X | X | Fail on perfect/Group filter match |
|
| 0 | 0 | 1 | 0 | X | X | X | Pass on hash filter match |
|
| 0 | 0 | 1 | 1 | X | X | X | Fail on hash filter match |
|
| 0 | 1 | 1 | 0 | X | X | X | Pass on hash or perfect/Group filter match |
|
| 0 | 1 | 1 | 1 | X | X | X | Fail on hash or perfect/Group filter match |
|
| Multicast |
1 | X | X | X | X | X | X | Pass all frames |
| X | X | X | X | X | 1 | X | Pass all frames |
|
| 0 | X | X | 0 | 0 | 0 | X | Pass on Perfect/Group filter match and drop PAUSE control frames if PCF = 0x |
|
| 0 | 0 | X | 0 | 1 | 0 | X | Pass on hash filter match and drop PAUSE control frames if PCF = 0x |
|
| 0 | 1 | X | 0 | 1 | 0 | X |
Pass on hash or perfect/Group filter match and drop PAUSE control frames if PCF = 0x |
|
| 0 | X | X | 1 | 0 | 0 | X | Fail on perfect/Group filter match and drop PAUSE control frames if PCF = 0x |
|
| 0 | 0 | X | 1 | 1 | 0 | X | Fail on hash filter match and drop PAUSE control frames if PCF = 0x |
|
| 0 | 1 | X | 1 | 1 | 0 | X |
Fail on hash or perfect/Group filter match and drop PAUSE control frames if PCF = 0x |
| Frame type | PM | SAIF | SAF | SA filter operation |
|---|---|---|---|---|
| Unicast |
1 | X | X | Pass all frames |
| 0 | 0 | 0 | Pass status on perfect/Group filter match but do not drop frames that fail |
|
| 0 | 1 | 0 | Fail status on perfect/group filter match but do not drop frame |
|
| 0 | 0 | 1 | Pass on perfect/group filter match and drop frames that fail |
|
| 0 | 1 | 1 | Fail on perfect/group filter match and drop frames that fail |
The MAC supports loopback of transmitted frames onto its receiver. By default, the MAC loopback function is disabled, but this feature can be enabled by programming the Loopback bit in the MAC ETH_MACCR register.
The MAC management counters (MMC) maintain a set of registers for gathering statistics on the received and transmitted frames. These include a control register for controlling the behavior of the registers, two 32-bit registers containing generated interrupts (receive and transmit), and two 32-bit registers containing masks for the Interrupt register (receive and transmit). These registers are accessible from the application. Each register is 32 bits wide.
Section 42.8: Ethernet register descriptions describes the various counters and lists the addresses of each of the statistics counters. This address is used for read/write accesses to the desired transmit/receive counter.
The Receive MMC counters are updated for frames that pass address filtering. Dropped frames statistics are not updated unless the dropped frames are runt frames of less than 6 bytes (DA bytes are not received fully).
Good transmitted and received frames
Transmitted frames are considered “good” if transmitted successfully. In other words, a transmitted frame is good if the frame transmission is not aborted due to any of the following errors:
+ Jabber Timeout
+ No Carrier/Loss of Carrier
+ Late Collision
+ Frame Underflow
+ Excessive Deferral
+ Excessive Collision
Received frames are considered “good” if none of the following errors exists:
+ CRC error
+ Runt Frame (shorter than 64 bytes)
+ Alignment error (in 10/ 100 Mbit/s only)
+ Length error (non-Type frames only)
+ Out of Range (non-Type frames only, longer than maximum size)
+ MII_RXER Input error
The maximum frame size depends on the frame type, as follows:
+ Untagged frame maxsize = 1518
+ VLAN Frame maxsize = 1522
This section describes the power management (PMT) mechanisms supported by the MAC. PMT supports the reception of network (remote) wakeup frames and Magic Packet frames. PMT generates interrupts for wakeup frames and Magic Packets received by the MAC. The PMT block is enabled with remote wakeup frame enable and Magic Packet enable. These enable bits (WFE and MPE) are in the ETH_MACPMTCSR register and are programmed by the application. When the power down mode is enabled in the PMT, then all received frames are dropped by the MAC and they are not forwarded to the application. The MAC comes out of the power down mode only when either a Magic Packet or a Remote wakeup frame is received and the corresponding detection is enabled.
Remote wakeup frame filter register
There are eight wakeup frame filter registers. To write on each of them, load the wakeup frame filter register value by value. The wanted values of the wakeup frame filter are loaded by sequentially loading eight times the wakeup frame filter register. The read operation is identical to the write operation. To read the eight values, the user has to read eight times the wakeup frame filter register to reach the last register. Each read/write points the wakeup frame filter register to the next filter register.
| (omitted) |
Filter i Byte Mask
This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in order to determine whether or not the frame is a wakeup frame. The MSB (thirty-first bit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is set, then Filter i Offset + j of the incoming frame is processed by the CRC block; otherwise Filter i Offset + j is ignored.
Filter i Command
This 4-bit command controls the filter i operation. Bit 3 specifies the address type, defining the pattern’s destination address type. When the bit is set, the pattern applies to only multicast frames. When the bit is reset, the pattern applies only to unicast frames. Bit 2 and bit 1 are reserved. Bit 0 is the enable bit for filter i; if bit 0 is not set, filter i is disabled.
Filter i Offset
This register defines the offset (within the frame) from which the frames are examined by filter i. This 8-bit pattern offset is the offset for the filter i first byte to be examined. The minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0 refers to the first byte of the frame).
Filter i CRC-16
This register contains the CRC_16 value calculated from the pattern, as well as the byte mask programmed to the wakeup filter register block.
Remote wakeup frame detection
When the MAC is in sleep mode and the remote wakeup bit is enabled in the ETH_MACPMTCSR register, normal operation is resumed after receiving a remote wakeup frame. The application writes all eight wakeup filter registers, by performing a sequential write to the wakeup frame filter register address. The application enables remote wakeup by writing a 1 to bit 2 in the ETH_MACPMTCSR register. PMT supports four programmable filters that provide different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wakeup frame is received. Filter_offset (minimum value 12, which refers to the 13th byte of the frame) determines the offset from which the frame is to be examined. Filter Byte Mask determines which bytes of the frame must be examined. The thirty-first bit of Byte Mask must be set to zero. The wakeup frame is checked only for length error, FCS error, dribble bit error, MII error, collision, and to ensure that it is not a runt frame. Even if the
wakeup frame is more than 512 bytes long, if the frame has a valid CRC value, it is considered valid. Wakeup frame detection is updated in the ETH_MACPMTCSR register for every remote wakeup frame received. If enabled, a PMT interrupt is generated to indicate the reception of a remote wakeup frame.
Magic packet detection
The Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic Packet technology to power up the sleeping device on the network. The MAC receives a specific packet of information, called a Magic Packet, addressed to the node on the network. Only Magic Packets that are addressed to the device or a broadcast address are checked to determine whether they meet the wakeup requirements. Magic Packets that pass address filtering (unicast or broadcast) are checked to determine whether they meet the remote Wake-on-LAN data format of 6 bytes of all ones followed by a MAC address appearing 16 times. The application enables Magic Packet wakeup by writing a 1 to bit 1 in the ETH_MACPMTCSR register. The PMT block constantly monitors each frame addressed to the node for a specific Magic Packet pattern. Each received frame is checked for a 0xFFFF FFFF FFFF pattern following the destination and source address field. The PMT block then checks the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF FFFF pattern is scanned for again in the incoming frame. The 16 repetitions can be anywhere in the frame, but must be preceded by the synchronization stream (0xFFFF FFFF FFFF). The device also accepts a multicast frame, as long as the 16 duplications of the MAC address are detected. If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for the data sequence:
Destination address source address ……………….. FFFF FFFF FFFF
0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455
0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455
0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455
0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455
…CRC
Magic Packet detection is updated in the ETH_MACPMTCSR register for received Magic Packet. If enabled, a PMT interrupt is generated to indicate the reception of a Magic Packet.
System consideration during power-down
The Ethernet PMT block is able to detect frames while the system is in the Stop mode, provided that the EXTI line 19 is enabled.
The MAC receiver state machine should remain enabled during the power-down mode. This means that the RE bit has to remain set in the ETH_MACCR register because it is involved in magic packet/ wake-on-LAN frame detection. The transmit state machine should however be turned off during the power-down mode by clearing the TE bit in the ETH_MACCR register. Moreover, the Ethernet DMA should be disabled during the power-down mode, because it is not necessary to copy the magic packet/wake-on-LAN frame into the SRAM. To disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the receive DMA, respectively) in the ETH_DMAOMR register.
The recommended power-down and wakeup sequences are as follows:
The IEEE 1588 standard defines a protocol that allows precise clock synchronization in measurement and control systems implemented with technologies such as network communication, local computing and distributed objects. The protocol applies to systems that communicate by local area networks supporting multicast messaging, including (but not limited to) Ethernet. This protocol is used to synchronize heterogeneous systems that include clocks of varying inherent precision, resolution and stability. The protocol supports system-wide synchronization accuracy in the submicrosecond range with minimum network and local clock computing resources. The message-based protocol, known as the precision time protocol (PTP), is transported over UDP/IP. The system or network is classified into Master and Slave nodes for distributing the timing/clock information. The protocol’s technique for synchronizing a slave node to a master node by exchanging PTP messages is described in Figure 563.
| (omitted) |
Most of the protocol implementation occurs in the software, above the UDP layer. As described above, however, hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the MII. This timing information has to be captured and returned to the software for a proper, high-accuracy implementation of PTP.
Reference timing source
To get a snapshot of the time, the core requires a reference time in 64-bit format (split into two 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits indicating time in nanoseconds) as defined in the IEEE 1588 specification.
The PTP reference clock input is used to internally generate the reference time (also called the System Time) and to capture time stamps. The frequency of this reference clock must be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns.
The generation, update and modification of the System Time are described in the System
Time correction methods.
The accuracy depends on the PTP reference clock input period, the characteristics of the oscillator (drift) and the frequency of the synchronization procedure.
Due to the synchronization from the Tx and Rx clock input domain to the PTP reference clock domain, the uncertainty on the time stamp latched value is 1 reference clock period. If we add the uncertainty due to resolution, we will add half the period for time stamping.
Transmission of frames with the PTP feature
When a frame’s SFD is output on the MII, a time stamp is captured. Frames for which time stamp capture is required are controllable on a per-frame basis. In other words, each transmitted frame can be marked to indicate whether a time stamp must be captured or not for that frame. The transmitted frames are not processed to identify PTP frames. Frame control is exercised through the control bits in the transmit descriptor. Captured time stamps are returned to the application in the same way as the status is provided for frames. The time stamp is sent back along with the Transmit status of the frame, inside the corresponding transmit descriptor, thus connecting the time stamp automatically to the specific PTP frame. The 64-bit time stamp information is written back to the TDES2 and TDES3 fields, with TDES2 holding the time stamp’s 32 least significant bits.
Reception of frames with the PTP feature
When the IEEE 1588 time stamping feature is enabled, the Ethernet MAC captures the time stamp of all frames received on the MII. The MAC provides the time stamp as soon as the frame reception is complete. Captured time stamps are returned to the application in the same way as the frame status is provided. The time stamp is sent back along with the Receive status of the frame, inside the corresponding receive descriptor. The 64-bit time stamp information is written back to the RDES2 and RDES3 fields, with RDES2 holding the time stamp’s 32 least significant bits.
System Time correction methods
The 64-bit PTP time is updated using the PTP input reference clock, HCLK. This PTP time is used as a source to take snapshots (time stamps) of the Ethernet frames being transmitted or received at the MII. The System Time counter can be initialized or corrected using either the Coarse or the Fine correction method.
In the Coarse correction method, the initial value or the offset value is written to the Time stamp update register (refer to Section 42.8.3: IEEE 1588 time stamp registers on
page 1860). For initialization, the System Time counter is written with the value in the Time stamp update registers, whereas for system time correction, the offset value (Time stamp update register) is added to or subtracted from the system time.
In the Fine correction method, the slave clock (reference clock) frequency drift with respect to the master clock (as defined in IEEE 1588) is corrected over a period of time, unlike in the Coarse correction method where it is corrected in a single clock cycle. The longer correction time helps maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time between PTP Sync message intervals. In this method, an accumulator
sums up the contents of the Addend register as shown in Figure 564. The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-precision frequency multiplier or divider. Figure 564 shows this algorithm.
| (omitted) |
The system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy. The frequency division is the ratio of the reference clock frequency to the required clock frequency. Hence, if the reference clock (HCLK) is, let us say, 66 MHz, the ratio is calculated as 66 MHz/50 MHz = 1.32. Hence, the default addend value to be set in the register is 232/1.32, which is equal to 0xC1F0 7C1F.
If the reference clock drifts lower, to 65 MHz for example, the ratio is 65/50 or 1.3 and the value to set in the addend register is 232/1.30 equal to 0xC4EC 4EC4. If the clock drifts higher, to 67 MHz for example, the addend register must be set to 0xBF0 B7672. When the clock drift is zero, the default addend value of 0xC1F0 7C1F (232/1.32) should be programmed.
In Figure 564, the constant value used to increment the subsecond register is 0d43. This makes an accuracy of 20 ns in the system time (in other words, it is incremented by 20 ns steps).
The software has to calculate the drift in frequency based on the Sync messages, and to update the Addend register accordingly. Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is as follows:
FreqCompensationValue0 = 232 / FreqDivisionRatio
If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, the algorithm described below must be applied. After a few Sync cycles, frequency lock occurs. The slave clock can then determine a precise MasterToSlaveDelay value and re-synchronize with the master using the new value.
The algorithm is as follows:
At time MasterSyncTime (n) the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime (n) and computes MasterClockTime (n) as:
MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n)
The master clock count for current Sync cycle, MasterClockCount (n) is given by:
MasterClockCount (n) = MasterClockTime (n) – MasterClockTime (n – 1) (assuming that MasterToSlaveDelay is the same for Sync cycles n and n – 1)
The slave clock count for current Sync cycle, SlaveClockCount (n) is given by:
SlaveClockCount (n) = SlaveClockTime (n) – SlaveClockTime (n – 1)
The difference between master and slave clock counts for current Sync cycle, ClockDiffCount (n) is given by:
ClockDiffCount (n) = MasterClockCount (n) – SlaveClockCount (n)
The frequency-scaling factor for slave clock, FreqScaleFactor (n) is given by:
FreqScaleFactor (n) = (MasterClockCount (n) + ClockDiffCount (n)) / SlaveClockCount (n)
The frequency compensation value for Addend register, FreqCompensationValue (n) is given by:
FreqCompensationValue (n) = FreqScaleFactor (n) × FreqCompensationValue (n – 1)
In theory, this algorithm achieves lock in one Sync cycle; however, it may take several cycles, due to changing network propagation delays and operating conditions.
This algorithm is self-correcting: if for any reason the slave clock is initially set to a value from the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.
Programming steps for system time generation initialization
The time stamping feature can be enabled by setting bit 0 in the Time stamp control register (ETH__PTPTSCR). However, it is essential to initialize the time stamp counter after this bit is set to start time stamp operation. The proper sequence is the following:
Note: If time stamp operation is disabled by clearing bit 0 in the ETH_PTPTSCR register, the
above steps must be repeated to restart the time stamp operation.
Programming steps for system time update in the Coarse correction method
To synchronize or update the system time in one process (coarse correction method), perform the following steps:
Programming steps for system time update in the Fine correction method
To synchronize or update the system time to reduce system-time jitter (fine correction method), perform the following steps:
PTP trigger internal connection with TIM2
The MAC provides a trigger interrupt when the system time becomes greater than the target time. Using an interrupt introduces a known latency plus an uncertainty in the command execution time.
In order to avoid this uncertainty, a PTP trigger output signal is set high when the system time is greater than the target time. It is internally connected to the TIM2 input trigger. With this signal, the input capture feature, the output compare feature and the waveforms of the timer can be used, triggered by the synchronized PTP system time. No uncertainty is introduced since the clock of the timer (PCLK1: TIM2 APB1 clock) and PTP reference clock (HCLK) are synchronous.
This PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The connection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). Figure 565 shows the connection.
| (omitted) |
PTP pulse-per-second output signal
This PTP pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be connected to an oscilloscope if necessary. The deviation between the two signals can therefore be measured. The pulse width of the PPS output is 125 ms.
The PPS output is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR).
The default frequency of the PPS output is 1 Hz. PPSFREQ[3:0] (in ETH_PTPPPSCR) can be used to set the frequency of the PPS output to 2PPSFREQ Hz.
When set to 1 Hz, the PPS pulse width is 125 ms with binary rollover (TSSSR=0, bit 9 in ETH_PTPTSCR) and 100 ms with digital rollover (TSSSR=1). When set to 2 Hz and higher, the duty cycle of the PPS output is 50% with binary rollover.
With digital rollover (TSSSR=1), it is recommended not to use the PPS output with a frequency other than 1 Hz as it would have irregular waveforms (though its average frequency would always be correct during any one-second window).
| (omitted) |
The DMA has independent transmit and receive engines, and a CSR space. The transmit engine transfers data from system memory into the Tx FIFO while the receive engine transfers data from the Rx FIFO into system memory. The controller utilizes descriptors to efficiently move data from source to destination with minimum CPU intervention. The DMA is designed for packet-oriented data transfers such as frames in Ethernet. The controller can be programmed to interrupt the CPU in cases such as frame transmit and receive transfer completion, and other normal/error conditions. The DMA and the STM32F76xxx and STM32F77xxx communicate through two data structures:
Control and status registers are described in detail in Section 42.8: Ethernet register
descriptions. Descriptors are described in detail in Normal Tx DMA descriptors.
The DMA transfers the received data frames to the receive buffer in the STM32F76xxx and STM32F77xxx memory, and transmits data frames from the transmit buffer in the STM32F76xxx and STM32F77xxx memory. Descriptors that reside in the STM32F76xxx and STM32F77xxx memory act as pointers to these buffers. There are two descriptor lists: one for reception, and one for transmission. The base address of each list is written into DMA Registers 3 and 4, respectively. A descriptor list is forward-linked (either implicitly or explicitly). The last descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is accomplished by configuring the second address chained in both the receive and transmit descriptors (RDES1[14] and TDES0[20]). The descriptor lists reside in the Host’s physical memory space. Each descriptor can point to a maximum of
two buffers. This enables the use of two physically addressed buffers, instead of two contiguous buffers in memory. A data buffer resides in the Host’s physical memory space, and consists of an entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data. The buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to the next frame buffer when the end of frame is detected. Data chaining can be enabled or disabled. The descriptor ring and chain structure is shown in Figure 567.
| (omitted) |
Initialization for the MAC is as follows:
The DMA attempts to execute fixed-length burst transfers on the AHB master interface if configured to do so (FB bit in ETH_DMABMR). The maximum burst length is indicated and
limited by the PBL field (ETH_DMABMR [13:8]). The receive and transmit descriptors are always accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be read.
The Transmit DMA initiates a data transfer only when there is sufficient space in the Transmit FIFO to accommodate the configured burst or the number of bytes until the end of frame (when it is less than the configured burst length). The DMA indicates the start address and the number of transfers required to the AHB Master Interface. When the AHB Interface is configured for fixed-length burst, then it transfers data using the best combination of INCR4, INCR8, INCR16 and SINGLE transactions. Otherwise (no fixed-length burst), it transfers data using INCR (undefined length) and SINGLE transactions.
The Receive DMA initiates a data transfer only when sufficient data for the configured burst is available in Receive FIFO or when the end of frame (when it is less than the configured burst length) is detected in the Receive FIFO. The DMA indicates the start address and the number of transfers required to the AHB master interface. When the AHB interface is configured for fixed-length burst, then it transfers data using the best combination of INCR4, INCR8, INCR16 and SINGLE transactions. If the end of frame is reached before the fixed-burst ends on the AHB interface, then dummy transfers are performed in order to complete the fixed-length burst. Otherwise (FB bit in ETH_DMABMR is reset), it transfers data using INCR (undefined length) and SINGLE transactions.
When the AHB interface is configured for address-aligned beats, both DMA engines ensure that the first burst transfer the AHB initiates is less than or equal to the size of the configured PBL. Thus, all subsequent beats start at an address that is aligned to the configured PBL. The DMA can only align the address for beats up to size 16 (for PBL > 16), because the AHB interface does not support more than INCR16.
The transmit and receive data buffers do not have any restrictions on start address alignment. In our system with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes. However, the DMA always initiates transfers with address aligned to the bus width with dummy data for the byte lanes not required. This typically happens during the transfer of the beginning or end of an Ethernet frame.
Example of buffer read:
If the Transmit buffer address is 0x0000 0FF2, and 15 bytes need to be transferred, then the DMA will read five full words from address 0x0000 0FF0, but when transferring data to the Transmit FIFO, the extra bytes (the first two bytes) will be dropped or ignored. Similarly, the last 3 bytes of the last transfer will also be ignored. The DMA always ensures it transfers a full 32-bit data items to the Transmit FIFO, unless it is the end of frame.
Example of buffer write:
If the Receive buffer address is 0x0000 0FF2, and 16 bytes of a received frame need to be transferred, then the DMA will write five full 32-bit data items from address 0x0000 0FF0. But the first 2 bytes of the first transfer and the last 2 bytes of the third transfer will have dummy data.
The DMA does not update the size fields in the transmit and receive descriptors. The DMA updates only the status fields (xDES0) of the descriptors. The driver has to calculate the sizes. The transmit DMA transfers the exact number of bytes (indicated by buffer size field in
TDES1) towards the MAC core. If a descriptor is marked as first (FS bit in TDES0 is set), then the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is marked as last (LS bit in TDES0), then the DMA marks the last transfer from that data buffer as the end of frame. The receive DMA transfers data to a buffer until the buffer is full or the end of frame is received. If a descriptor is not marked as last (LS bit in RDES0), then the buffer(s) that correspond to the descriptor are full and the amount of valid data in a buffer is accurately indicated by the buffer size field minus the data buffer pointer offset when the descriptor’s FS bit is set. The offset is zero when the data buffer pointer is aligned to the databus width. If a descriptor is marked as last, then the buffer may not be full (as indicated by the buffer size in RDES1). To compute the amount of valid data in this final buffer, the driver must read the frame length (FL bits in RDES0[29:16]) and subtract the sum of the buffer sizes of the preceding buffers in this frame. The receive DMA always transfers the start of next frame with a new descriptor.
Note: Even when the start address of a receive buffer is not aligned to the system databus width
the system should allocate a receive buffer of a size aligned to the system bus width. For
example, if the system allocates a 1024 byte (1 KB) receive buffer starting from address
0x1000, the software can program the buffer start address in the receive descriptor to have
a 0x1002 offset. The receive DMA writes the frame to this buffer with dummy data in the first
two locations (0x1000 and 0x1001). The actual frame is written from location 0x1002. Thus,
the actual useful space in this buffer is 1022 bytes, even though the buffer size is
programmed as 1024 bytes, due to the start address offset.
The arbiter inside the DMA takes care of the arbitration between transmit and receive channel accesses to the AHB master interface. Two types of arbitrations are possible: round-robin, and fixed-priority. When round-robin arbitration is selected (DA bit in ETH_DMABMR is reset), the arbiter allocates the databus in the ratio set by the PM bits in ETH_DMABMR, when both transmit and receive DMAs request access simultaneously. When the DA bit is set, the receive DMA always gets priority over the transmit DMA for data access.
For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops all operations and updates the error bits and the fatal bus error bit in the Status register (ETH_DMASR register). That DMA controller can resume operation only after soft- or hard-resetting the peripheral and re-initializing the DMA.
TxDMA operation: default (non-OSF) mode
The transmit DMA engine in default mode proceeds as follows:
Unavailable (ETH_DMASR register[2]) and Normal Interrupt Summary (ETH_DMASR register[16]) bits are set. The transmit engine proceeds to Step 9.
Figure 568 shows the TxDMA transmission flow in default mode.
| (omitted) |
TxDMA operation: OSF mode
While in the Run state, the transmit process can simultaneously acquire two frames without closing the Status descriptor of the first (if the OSF bit is set in ETH_DMAOMR register[2]). As the transmit process finishes transferring the first frame, it immediately polls the transmit descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the Run-state transmit DMA operates according to the following sequence:
Figure 569 shows the basic flowchart in OSF mode.
| (omitted) |
Transmit frame processing
The transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad insertion, the buffer must have complete Ethernet frames (excluding preamble), including the CRC bytes. Frames can be data-chained and span over several buffers. Frames have to be delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the transmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the frame data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the last descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to acquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this descriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it indicates the last buffer of the frame. After the last buffer of the frame has been transmitted,
the DMA writes back the final status information to the transmit descriptor 0 (TDES0) word of the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]). At this time, if Interrupt on Completion (TDES0[30]) is set, Transmit Interrupt (in ETH_DMASR register [0]) is set, the next descriptor is fetched, and the process repeats. Actual frame transmission begins after the Transmit FIFO has reached either a programmable transmit threshold (ETH_DMAOMR register[16:14]), or a full frame is contained in the FIFO. There is also an option for the Store and forward mode (ETH_DMAOMR register[21]). Descriptors are released (OWN bit TDES0[31] is cleared) when the DMA finishes transferring the frame.
Transmit polling suspended
Transmit polling can be suspended by either of the following conditions:
Normal Tx DMA descriptors
The normal transmit descriptor structure consists of four 32-bit words as shown in Figure 570. The bit descriptions of TDES0, TDES1, TDES2 and TDES3 are given below.
Note that enhanced descriptors must be used if time stamping is activated (ETH_PTPTSCR
bit 0, TSE=1) or if IPv4 checksum offload is activated (ETH_MACCR bit 10, IPCO=1).
| (omitted) |
TDES0: Transmit descriptor Word0
The application software has to program the control bits [30:26]+[23:20] plus the OWN bit [31] during descriptor initialization. When the DMA updates the descriptor (or writes it back), it resets all the control bits plus the OWN bit, and reports only the status bits.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OWN | IC | LS | FS | DC | DP | TTSE | Res. | CIC | TER | TCH | Res. | Res. | TTSS | IHE |
ES | JT | FF | IPE | LCA | NC | LCO | EC | VF | CC | ED | UF | DB |
||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||
| Bit 31 | OWN: Own bit |
|
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the descriptor is owned by the CPU. The DMA clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are read completely. The ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging to the same frame have been set. |
|
| Bit 30 | IC: Interrupt on completion |
|
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been transmitted. |
|
| Bit 29 | LS: Last segment |
|
When set, this bit indicates that the buffer contains the last segment of the frame. |
|
| Bit 28 | FS: First segment |
|
When set, this bit indicates that the buffer contains the first segment of a frame. |
|
| Bit 27 | DC: Disable CRC |
|
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of the transmitted frame. This is valid only when the first segment (TDES0[28]) is set. |
|
| Bit 26 | DP: Disable pad |
|
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first segment (TDES0[28]) is set. |
|
| Bit 25 | TTSE: Transmit time stamp enable |
|
When TTSE is set and when TSE is set (ETH_PTPTSCR bit 0), IEEE1588 hardware time stamping is activated for the transmit frame described by the descriptor. This field is only valid when the First segment control bit (TDES0[28]) is set. |
|
| Bit 24 | Reserved, must be kept at reset value. |
| Bits 23:22 | CIC: Checksum insertion control |
|
These bits control the checksum calculation and insertion. Bit encoding is as shown below: 00: Checksum Insertion disabled |
|
| Bit 21 | TER: Transmit end of ring |
|
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring. |
|
| Bit 20 | TCH: Second address chained |
|
When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care” value. TDES0[21] takes precedence over TDES0[20]. |
|
| Bits 19:18 | Reserved, must be kept at reset value. |
| Bit 17 | TTSS: Transmit time stamp status |
|
This field is used as a status bit to indicate that a time stamp was captured for the described transmit frame. When this bit is set, TDES2 and TDES3 have a time stamp value captured for the transmit frame. This field is only valid when the descriptor’s Last segment control bit (TDES0[29]) is set. that when enhanced descriptors are enabled (EDFE=1 in ETH_DMABMR), TTSS=1 indicates that TDES6 and TDES7 have the time stamp value. |
|
| Bit 16 | IHE: IP header error |
|
When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header. The transmitter checks the header length in the IPv4 packet against the number of header bytes received from the application and indicates an error status if there is a mismatch. For IPv6 frames, a header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet length/type field value for an IPv4 or IPv6 frame must match the IP header version received with the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value less than 0x5. |
|
| Bit 15 | ES: Error summary |
|
Indicates the logical OR of the following bits: |
|
| Bit 14 | JT: Jabber timeout |
|
When set, this bit indicates the MAC transmitter has experienced a jabber timeout. This bit is only set when the MAC configuration register’s JD bit is not set. |
|
| Bit 13 | FF: Frame flushed |
|
When set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush command given by the CPU. |
|
| Bit 12 | IPE: IP payload error |
|
When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP, UDP or ICMP packet bytes received from the application and issues an error status in case of a mismatch. |
|
| Bit 11 | LCA: Loss of carrier |
|
When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the MII_CRS signal was inactive for one or more transmit clock periods during frame transmission). This is valid only for the frames transmitted without collision when the MAC operates in Half-duplex mode. |
|
| Bit 10 | NC: No carrier |
|
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during transmission. |
|
| Bit 9 | LCO: Late collision |
|
When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte times, including preamble, in MII mode). This bit is not valid if the Underflow Error bit is set. |
|
| Bit 8 | EC: Excessive collision |
|
When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the RD (Disable retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted. |
|
| Bit 7 | VF: VLAN frame |
|
When set, this bit indicates that the transmitted frame was a VLAN-type frame. |
|
| Bits 6:3 | CC: Collision count |
|
This 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. The count is not valid when the Excessive collisions bit (TDES0[8]) is set. |
|
| Bit 2 | ED: Excessive deferral |
|
When set, this bit indicates that the transmission has ended because of excessive deferral of over 24 288 bit times if the Deferral check (DC) bit in the MAC Control register is set high. |
|
| Bit 1 | UF: Underflow error |
|
When set, this bit indicates that the MAC aborted the frame because data arrived late from the RAM memory. Underflow error indicates that the DMA encountered an empty transmit buffer while transmitting the frame. The transmission process enters the Suspended state and sets both Transmit underflow (Register 5[5]) and Transmit interrupt (Register 5[0]). |
|
| Bit 0 | DB: Deferred bit |
|
When set, this bit indicates that the MAC defers before transmission because of the presence of the carrier. This bit is valid only in Half-duplex mode. |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | TBS2 |
Res. | Res. | Res. | TBS1 |
||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||
31:29 Reserved, must be kept at reset value.
28:16 TBS2: Transmit buffer 2 size
These bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is set.
15:13 Reserved, must be kept at reset value.
12:0 TBS1: Transmit buffer 1 size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
TDES2: Transmit descriptor Word2
TDES2 contains the address pointer to the first buffer of the descriptor or it contains time stamp data.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBAP1/TBAP/TTSL |
TBAP1/TBAP/TTSL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TBAP1: Transmit buffer 1 address pointer / Transmit frame time stamp low |
|
These bits have two different functions: they indicate to the DMA the location of data in memory, and after all data are transferred, the DMA can then use these bits to pass back time stamp data. |
TDES3: Transmit descriptor Word3
TDES3 contains the address pointer either to the second buffer of the descriptor or the next descriptor, or it contains time stamp data.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBAP2/TBAP2/TTSH |
TBAP2/TBAP2/TTSH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TBAP2: Transmit buffer 2 address pointer (Next descriptor address) / Transmit frame time stamp high |
|
These bits have two different functions: they indicate to the DMA the location of data in memory, and after all data are transferred, the DMA can then use these bits to pass back time stamp data. |
Enhanced Tx DMA descriptors
Enhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time stamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10).
Enhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. TDES0, TDES1, TDES2 and TDES3 have the same definitions as for normal transmit descriptors (refer to Normal Tx DMA descriptors). TDES6 and TDES7 hold the time stamp. TDES4, TDES5, TDES6 and TDES7 are defined below.
When the Enhanced descriptor mode is selected, the software needs to allocate 32-bytes (8 DWORDS) of memory for every descriptor. When time stamping or IPv4 checksum offload are not being used, the enhanced descriptor format may be disabled and the software can use normal descriptors with the default size of 16 bytes.
| (omitted) |
TDES4: Transmit descriptor Word4
Reserved
TDES5: Transmit descriptor Word5
Reserved
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TTSL |
TTSL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TTSL: Transmit frame time stamp low |
|
This field is updated by DMA with the 32 least significant bits of the time stamp captured for the corresponding transmit frame. This field has the time stamp only if the Last segment control bit (LS) in the descriptor is set. |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TTSH |
TTSH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TTSH: Transmit frame time stamp high |
|
This field is updated by DMA with the 32 most significant bits of the time stamp captured for the corresponding transmit frame. This field has the time stamp only if the Last segment control bit (LS) in the descriptor is set. |
The Receive DMA engine’s reception sequence is illustrated in Figure 572 and described below:
The DMA does not acknowledge accepting the status until it has completed the time stamp write-back and is ready to perform status write-back to the descriptor. If software has enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time stamping is not enabled), RDES2 and RDES3 remain unchanged.
| (omitted) |
Receive descriptor acquisition
The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is/are satisfied:
Receive frame processing
The MAC transfers the received frames to the STM32F76xxx and STM32F77xxx memory only when the frame passes the address filter and the frame size is greater than or equal to the configurable threshold bytes set for the Receive FIFO, or when the complete frame is written to the FIFO in Store-and-forward mode. If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive All ETH_MACFFR [31] bit is set). Frames that are shorter than 64 bytes, because of collision or premature termination, can be purged from the Receive FIFO. After 64 (configurable threshold) bytes have been received, the DMA block begins transferring the frame data to the receive buffer pointed to by the current descriptor. The DMA sets the first descriptor (RDES0[9]) after the DMA AHB Interface becomes ready to receive a data transfer (if DMA is not fetching transmit data from the memory), to delimit the frame. The descriptors are released when the OWN (RDES0[31]) bit is reset to 0, either as the data buffer fills up or as the last segment of the frame is transferred to the receive buffer. If the frame is contained in a single descriptor, both the last descriptor (RDES0[8]) and first descriptor (RDES0[9]) bits are set. The DMA fetches the next descriptor, sets the last descriptor (RDES0[8]) bit, and releases the RDES0 status bits in the previous frame descriptor. Then the DMA sets the receive interrupt bit (ETH_DMASR register [6]). The same process repeats unless the DMA encounters a descriptor flagged as being owned by the CPU. If this occurs, the receive process sets the receive buffer unavailable bit (ETH_DMASR register[7]) and then enters the Suspend state. The position in the receive list is retained.
Receive process suspended
If a new receive frame arrives while the receive process is in Suspend state, the DMA re-fetches the current descriptor in the STM32F76xxx and STM32F77xxx memory. If the descriptor is now owned by the DMA, the receive process re-enters the Run state and starts frame reception. If the descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the Rx FIFO and increments the missed frame counter. If more than one frame is stored in the Rx FIFO, the process repeats. The discarding or flushing of the frame at the top of the Rx FIFO can be avoided by setting the DMA Operation mode register bit 24 (DFRF). In such conditions, the receive process sets the receive buffer unavailable status bit and returns to the Suspend state.
Normal Rx DMA descriptors
The normal receive descriptor structure consists of four 32-bit words (16 bytes). These are shown in Figure 573. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given below.
Note that enhanced descriptors must be used if time stamping is activated (TSE=1,
ETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10).
| (omitted) |
RDES0: Receive descriptor Word0
RDES0 contains the received frame status, the frame length and the descriptor ownership information.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OWN | AFM | FL |
ES | DE | SAF | LE | OE | VLAN | FS | LS | IPHCE/TSV | LCO | FT | RWT | RE | DE | CE | PCE/ESA |
|||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | OWN: Own bit |
|
When set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem. When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. |
|
| Bit 30 | AFM: Destination address filter fail |
|
When set, this bit indicates a frame that failed the DA filter in the MAC Core. |
|
| Bits 29:16 | FL: Frame length |
|
These bits indicate the byte length of the received frame that was transferred to host memory (including CRC). This field is valid only when last descriptor (RDES0[8]) is set and descriptor error (RDES0[14]) is reset. |
|
| Bit 15 | ES: Error summary |
|
Indicates the logical OR of the following bits: |
|
| Bit 14 | DE: Descriptor error |
|
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the DMA does not own the next descriptor. The frame is truncated. This field is valid only when the last descriptor (RDES0[8]) is set. |
|
| Bit 13 | SAF: Source address filter fail |
|
When set, this bit indicates that the SA field of frame failed the SA filter in the MAC Core. |
|
| Bit 12 | LE: Length error |
|
When set, this bit indicates that the actual length of the received frame does not match the value in the Length/ Type field. This bit is valid only when the Frame type (RDES0[5]) bit is reset. |
|
| Bit 11 | OE: Overflow error |
|
When set, this bit indicates that the received frame was damaged due to buffer overflow. |
|
| Bit 10 | VLAN: VLAN tag |
|
When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC core. |
|
| Bit 9 | FS: First descriptor |
|
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next descriptor contains the beginning of the frame. |
|
| Bit 8 | LS: Last descriptor |
|
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame. |
|
| Bit 7 | IPHCE/TSV: IPv header checksum error / time stamp valid |
|
If IPHCE is set, it indicates an error in the IPv4 or IPv6 header. This error can be due to inconsistent Ethernet Type field and IP header Version field values, a header checksum mismatch in IPv4, or an Ethernet frame lacking the expected number of IP header bytes. This bit can take on special meaning as specified in Table 308. |
|
| Bit 6 | LCO: Late collision |
|
When set, this bit indicates that a late collision has occurred while receiving the frame in Half- |
|
| Bit 5 | FT: Frame type |
|
When set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater than or equal to 0x0600). When this bit is reset, it indicates that the received frame is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes. When the normal descriptor format is used (ETH_DMABMR EDFE=0), FT can take on special meaning as specified in Table 308. |
|
| Bit 4 | RWT: Receive watchdog timeout |
|
When set, this bit indicates that the Receive watchdog timer has expired while receiving the current frame and the current frame is truncated after the watchdog timeout. |
|
| Bit 3 | RE: Receive error |
|
When set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted during frame reception. |
|
| Bit 2 | DE: Dribble bit error |
|
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is valid only in MII mode. |
|
| Bit 1 | CE: CRC error |
|
When set, this bit indicates that a cyclic redundancy check (CRC) error occurred on the received frame. This field is valid only when the last descriptor (RDES0[8]) is set. |
|
| Bit 0 | PCE/ESA: Payload checksum error / extended status available |
|
When set, it indicates that the TCP, UDP or ICMP checksum the core calculated does not match the received encapsulated TCP, UDP or ICMP segment’s Checksum field. This bit is also set when the received number of payload bytes does not match the value indicated in the Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame. This bit can take on special meaning as specified in Table 308. |
Bits 5, 7, and 0 reflect the conditions discussed in Table 308.
|
|
IPC checksum error |
payload checksum error |
Frame status |
|---|---|---|---|
| 0 | 0 | 0 | IEEE 802.3 Type frame (Length field value is less than 0x0600.) |
| 1 | 0 | 0 | IPv4/IPv6 Type frame, no checksum error detected |
| 1 | 0 | 1 | IPv4/IPv6 Type frame with a payload checksum error (as described for PCE) detected |
| 1 | 1 | 0 | IPv4/IPv6 Type frame with an IP header checksum error (as described for IPC CE) detected |
| 1 | 1 | 1 | IPv4/IPv6 Type frame with both IP header and payload checksum errors detected |
| 0 | 0 | 1 | IPv4/IPv6 Type frame with no IP header checksum error and the payload check bypassed, due to an unsupported payload |
| 0 | 1 | 1 | A Type frame that is neither IPv4 or IPv6 (the checksum offload engine bypasses checksum completely.) |
| 0 | 1 | 0 | Reserved |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIC | Res. | Res. | RBS2 |
RER | RCH | Res. | RBS |
||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||
| Bit 31 | DIC: Disable interrupt on completion |
|
When set, this bit prevents setting the Status register’s RS bit (CSR5[6]) for the received frame ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt to Host due to RS for that frame. |
|
| Bits 30:29 | Reserved, must be kept at reset value. |
| Bits 28:16 | RBS2: Receive buffer 2 size |
|
These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8, or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of RDES3 (buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple of 4, 8 or 16, the resulting behavior is undefined. This field is not valid if RDES1 [14] is set. |
|
| Bit 15 | RER: Receive end of ring |
|
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring. |
|
| Bit 14 | RCH: Second address chained |
|
When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care” value. RDES1[15] takes precedence over RDES1[14]. |
|
| Bit 13 | Reserved, must be kept at reset value. |
| Bits 12:0 | RBS1: Receive buffer 1 size |
|
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8 or 16, depending upon the bus widths (32, 64 or 128), even if the value of RDES2 (buffer1 address pointer) is not aligned. When the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor depending on the value of RCH (bit 14). |
RDES2: Receive descriptor Word2
RDES2 contains the address pointer to the first data buffer in the descriptor, or it contains time stamp data.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RBP1 / RTSL |
RBP1 / RTSL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | RBAP1 / RTSL: Receive buffer 1 address pointer / Receive frame time stamp low |
|
These bits take on two different functions: the application uses them to indicate to the DMA where to store the data in memory, and then after transferring all the data the DMA may use these bits to pass back time stamp data. |
RDES3: Receive descriptor Word3
RDES3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RBP2 / RTSH |
RBP2 / RTSH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame time stamp high |
|
These bits take on two different functions: the application uses them to indicate to the DMA the location of where to store the data in memory, and then after transferring all the data the DMA may use these bits to pass back time stamp data. |
Enhanced Rx DMA descriptors format with IEEE1588 time stamp
Enhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time stamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10).
Enhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. RDES0, RDES1, RDES2 and RDES3 have the same definitions as for normal receive descriptors (refer to Normal Rx DMA descriptors). RDES4 contains extended status while RDES6 and RDES7 hold the time stamp. RDES4, RDES5, RDES6 and RDES7 are defined below.
When the Enhanced descriptor mode is selected, the software needs to allocate 32 bytes (8 DWORDS) of memory for every descriptor. When time stamping or IPv4 checksum offload are not being used, the enhanced descriptor format may be disabled and the software can use normal descriptors with the default size of 16 bytes.
| (omitted) |
The extended status, shown below, is valid only when there is status related to IPv4 checksum or time stamp available as indicated by bit 0 in RDES0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | PV | PFT | PMT | IPV6PR | IPV4PR | IPCB | IPPE | IPHE | IPPT |
|||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||
| Bits 31:14 | Reserved, must be kept at reset value. |
| Bit 13 | PV: PTP version |
|
When set, indicates that the received PTP message uses the IEEE 1588 version 2 format. When cleared, it uses version 1 format. This is valid only if the message type is non-zero. |
|
| Bit 12 | PFT: PTP frame type |
|
When set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit is cleared and the message type is non-zero, it indicates that the PTP message is sent over UDP-IPv4 or UDP-IPv6. The information on IPv4 or IPv6 can be obtained from bits 6 and 7. |
|
| Bits 11:8 | PMT: PTP message type |
|
These bits are encoded to give the type of the message received.
|
|
| Bit 7 | IPV6PR: IPv6 packet received |
|
When set, this bit indicates that the received packet is an IPv6 packet. |
|
| Bit 6 | IPV4PR: IPv4 packet received |
|
When set, this bit indicates that the received packet is an IPv4 packet. |
|
| Bit 5 | IPCB: IP checksum bypassed |
|
When set, this bit indicates that the checksum offload engine is bypassed. |
|
| Bit 4 | IPPE: IP payload error |
|
When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) that the core calculated does not match the corresponding checksum field in the received segment. It is also set when the TCP, UDP, or ICMP segment length does not match the payload length value in the IP Header field. |
|
| Bit 3 | IPHE: IP header error |
|
When set, this bit indicates either that the 16-bit IPv4 header checksum calculated by the core does not match the received checksum bytes, or that the IP datagram version is not consistent with the Ethernet Type value. |
|
| Bits 2:0 | IPPT: IP payload type if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10), these bits indicate the type of payload encapsulated in the IP datagram. These bits are ‘00’ if there is an IP header error or fragmented IP. |
|
RDES5: Receive descriptor Word5
Reserved.
RDES6: Receive descriptor Word6
The table below describes the fields that have different meaning for RDES6 when the receive descriptor is closed and time stamping is enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RTSL |
RTSL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
.
| Bits 31:0 | RTSL: Receive frame time stamp low |
|
The DMA updates this field with the 32 least significant bits of the time stamp captured for the corresponding receive frame. The DMA updates this field only for the last descriptor of the receive frame indicated by last descriptor status bit (RDES0[8]). When this field and the RTSH field in RDES7 show all ones, the time stamp must be treated as corrupt. |
RDES7: Receive descriptor Word7
The table below describes the fields that have a different meaning for RDES7 when the receive descriptor is closed and time stamping is enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RTSH |
RTSH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
.
| Bits 31:0 | RTSH: Receive frame time stamp high |
|
The DMA updates this field with the 32 most significant bits of the time stamp captured for the corresponding receive frame. The DMA updates this field only for the last descriptor of the receive frame indicated by last descriptor status bit (RDES0[8]). |
Interrupts can be generated as a result of various events. The ETH_DMASR register contains all the bits that might cause an interrupt. The ETH_DMAIER register contains an enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in the ETH_DMASR register. Interrupts are cleared by writing a 1 to the corresponding bit position. When all the enabled interrupts within a group are cleared, the corresponding summary bit is cleared. If the MAC core is the cause for assertion of the interrupt, then any of the TSTS or PMTS bits in the ETH_DMASR register is set high.
Interrupts are not queued and if the interrupt event occurs before the driver has responded to it, no additional interrupts are generated. For example, the Receive Interrupt bit (ETH_DMASR register [6]) indicates that one or more frames were transferred to the STM32F76xxx and STM32F77xxx buffer. The driver must scan all descriptors, from the last recorded position to the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan the ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again unless a new interrupting event occurs, after the driver has cleared the appropriate bit in the
ETH_DMASR register. For example, the controller generates a Receive interrupt (ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next, receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive interrupt. Even then, a new interrupt is generated, due to the active or pending Receive buffer unavailable interrupt.
| (omitted) |
The Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet operations and the other, used only for the Ethernet wakeup event (with wakeup frame or Magic Packet detection) when it is mapped on EXTI lIne19.
The first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as listed in the MAC interrupts and DMA interrupts sections.
The second vector is reserved for interrupts generated by the PMT on wakeup events. The mapping of a wakeup event on EXTI line19 causes the STM32F76xxx and STM32F77xxx to exit the low-power mode, and generates an interrupt.
When an Ethernet wakeup event mapped on EXTI Line19 occurs and the MAC PMT interrupt is enabled and the EXTI Line19 interrupt, with detection on rising edge, is also enabled, both interrupts are generated.
A watchdog timer (see ETH_DMARSWTR register) is given for flexible control of the RS bit (ETH_DMASR register). When this watchdog timer is programmed with a non-zero value, it
gets activated as soon as the RxDMA completes a transfer of a received frame to system memory without asserting the Receive Status because it is not enabled in the corresponding Receive descriptor (RDES1[31]). When this timer runs out as per the programmed value, the RS bit is set and the interrupt is asserted if the corresponding RIE is enabled in the ETH_DMAIER register. This timer is disabled before it runs out, when a frame is transferred to memory and the RS is set because it is enabled for that descriptor.
Note: Reading the PMT control and status register automatically clears the Wakeup Frame
Received and Magic Packet Received PMT interrupt flags. However, since the registers for
these flags are in the CLK_RX domain, there may be a significant delay before this update
is visible by the firmware. The delay is especially long when the RX clock is slow (in 10 Mbit
mode) and when the AHB bus is high-frequency.
Since interrupt requests from the PMT to the CPU are based on the same registers in the
CLK_RX domain, the CPU may spuriously call the interrupt routine a second time even after
reading PMT_CSR. Thus, it may be necessary that the firmware polls the Wakeup Frame
Received and Magic Packet Received bits and exits the interrupt service routine only when
they are found to be at ‘0’.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit).
Ethernet MAC configuration register (ETH_MACCR)
Address offset: 0x0000
Reset value: 0x0000 8000
The MAC configuration register is the operation mode register of the MAC. It establishes receive and transmit operating modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | CSTF | Res. | WD | JD | Res. | Res. | IFG | CSD |
Res. | FES | ROD | LM | DM | IPCO | RD | Res. | APCS | BL | DC | TE | RE | Res. | Res. |
| rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:26 | Reserved, must be kept at reset value. |
| Bit 25 | CSTF: CRC stripping for Type frames |
|
When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater than 0x0600) will be stripped and dropped before forwarding the frame to the application. |
|
| Bit 24 | Reserved, must be kept at reset value. |
| Bit 23 | WD: Watchdog disable |
|
When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16 384 bytes. |
|
| Bit 22 | JD: Jabber disable |
|
When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16 384 bytes. |
|
| Bits 21:20 | Reserved, must be kept at reset value. |
| Bits 19:17 | IFG: Interframe gap |
|
These bits control the minimum interframe gap between frames during transmission. 000: 96 bit times In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) |
|
| Bit 16 | CSD: Carrier sense disable |
|
When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier during such transmission. |
|
| Bit 15 | Reserved, must be kept at reset value. |
| Bit 14 | FES: Fast Ethernet speed |
|
Indicates the speed in Fast Ethernet (MII) mode: |
|
| Bit 13 | ROD: Receive own disable |
|
When this bit is set, the MAC disables the reception of frames in Half-duplex mode. |
|
| Bit 12 | LM: Loopback mode |
|
When this bit is set, the MAC operates in loopback mode at the MII. The MII receive clock input (RX_CLK) is required for the loopback to work properly, as the transmit clock is not looped-back internally. |
|
| Bit 11 | DM: Duplex mode |
|
When this bit is set, the MAC operates in a Full-duplex mode where it can transmit and receive simultaneously. |
|
| Bit 10 | IPCO: IPv4 checksum offload |
|
When set, this bit enables IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. When this bit is reset, the checksum offload function in the receiver is disabled and the corresponding PCE and IP HCE status bits (see Table 305) are always cleared. |
|
| Bit 9 | RD: Retry disable |
|
When this bit is set, the MAC attempts only 1 transmission. When a collision occurs on the MII, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status.
This bit is applicable only in the Half-duplex mode.
|
|
| Bit 8 | Reserved, must be kept at reset value. |
| Bit 7 | APCS: Automatic pad/CRC stripping |
|
When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length’s field value is less than or equal to 1 500 bytes. All received frames with length field greater than or equal to 1 501 bytes are passed on to the application without stripping the Pad/FCS field. When this bit is reset, the MAC passes all incoming frames unmodified. |
|
| Bits 6:5 | BL: Back-off limit |
|
The Back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000 Mbit/s and 512 bit times for 10/100 Mbit/s) the MAC waits before rescheduling a transmission attempt during retries after a collision.
This bit is applicable only to Half-duplex mode.
00: k = min (n, 10) |
|
| Bit 4 | DC: Deferral check |
|
When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24 288 bit times in 10/100- |
|
| Bit 3 | TE: Transmitter enable |
|
When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. |
|
| Bit 2 | RE: Receiver enable |
|
When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII. |
|
| Bits 1:0 | Reserved, must be kept at reset value. |
Ethernet MAC frame filter register (ETH_MACFFR)
Address offset: 0x0004
Reset value: 0x0000 0000
The MAC frame filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as pass bad frames and pass control frames.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RA | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | HPF | SAF | SAIF | PCF | BFD | PAM | DAIF | HM | HU | PM |
|
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||
| Bit 31 | RA: Receive all |
|
When this bit is set, the MAC receiver passes all received frames on to the application, irrespective of whether they have passed the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the receive status word. When this bit is reset, the MAC receiver passes on to the application only those frames that have passed the SA/DA address filter. |
|
| Bits 30:11 | Reserved, must be kept at reset value. |
| Bit 10 | HPF: Hash or perfect filter |
|
When this bit is set and if the HM or HU bit is set, the address filter passes frames that match either the perfect filtering or the hash filtering. |
|
| Bit 9 | SAF: Source address filter |
|
The MAC core compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison matches, then the SAMatch bit in the RxStatus word is set high. When this bit is set high and the SA filter fails, the MAC drops the frame. |
|
| Bit 8 | SAIF: Source address inverse filtering |
|
When this bit is set, the address check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA address filter. |
|
| Bits 7:6 | PCF: Pass control frames |
|
These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE in Flow Control Register[2]. |
|
| Bit 5 | BFD: Broadcast frames disable |
|
When this bit is set, the address filters filter all incoming broadcast frames. |
|
| Bit 4 | PAM: Pass all multicast |
|
When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. |
|
| Bit 3 | DAIF: Destination address inverse filtering |
|
When this bit is set, the address check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. |
|
| Bit 2 | HM: Hash multicast |
|
When set, MAC performs destination address filtering of received multicast frames according to the hash table. |
|
| Bit 1 | HU: Hash unicast |
|
When set, MAC performs destination address filtering of unicast frames according to the hash table. |
|
| Bit 0 | PM: Promiscuous mode |
|
When this bit is set, the address filters pass all incoming frames regardless of their destination or source address. The SA/DA filter fails status bits in the receive status word are always cleared when PM is set. |
Ethernet MAC hash table high register (ETH_MACHTHR)
Address offset: 0x0008
Reset value: 0x0000 0000
The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame are passed through the CRC logic, and the upper 6 bits in the CRC register are used to index the contents of the Hash table. This CRC
is a 32-bit value coded by the following polynomial (for more details refer to Section 42.5.3:
MAC frame reception):
G( x ) = x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2 +x+ 1
The most significant bit determines the register to be used (hash table high/hash table low), and the other 5 bits determine which bit within the register. A hash value of 0b0 0000 selects bit 0 in the selected register, and a value of 0b1 1111 selects bit 31 in the selected register.
For example, if the DA of the incoming frame is received as 0x1F52 419C B6AF (0x1F is the first byte received on the MII interface), then the internally calculated 6-bit Hash value is 0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is received as 0xA00A 9800 0045, then the calculated 6-bit Hash value is 0x07 and the HTL register bit[7] is checked for filtering.
If the corresponding bit value in the register is 1, the frame is accepted. Otherwise, it is rejected. If the PAM (pass all multicast) bit is set in the ETH_MACFFR register, then all multicast frames are accepted regardless of the multicast hash values.
The Hash table high register contains the higher 32 bits of the multicast Hash table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HTH |
HTH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | HTH: Hash table high This field contains the upper 32 bits of Hash table. |
Ethernet MAC hash table low register (ETH_MACHTLR)
Address offset: 0x000C
Reset value: 0x0000 0000
The Hash table low register contains the lower 32 bits of the multi-cast Hash table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HTL |
HTL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | HTL: Hash table low |
|
This field contains the lower 32 bits of the Hash table. |
Ethernet MAC MII address register (ETH_MACMIIAR)
Address offset: 0x0010
Reset value: 0x0000 0000
The MII address register controls the management cycles to the external PHY through the management interface.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
PA | MR | Res. | CR | MW | MB |
||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rc_w1 |
|||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:11 | PA: PHY address |
|
This field tells which of the 32 possible PHY devices are being accessed. |
|
| Bits 10:6 | MR: MII register |
|
These bits select the desired MII register in the selected PHY device. |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bits 4:2 | CR: Clock range |
|
The CR clock range selection determines the HCLK frequency and is used to decide the frequency of the MDC clock: |
|
| Bit 1 | MW: MII write |
|
When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register. |
|
| Bit 0 | MB: MII busy |
|
This bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This bit must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, this bit is set to 0b1 by the application to indicate that a read or write access is in progress. ETH_MACMIIDR (MII Data) should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The ETH_MACMIIDR is invalid until this bit is cleared by the MAC during a PHY Read operation. The ETH_MACMIIAR (MII Address) should not be written to until this bit is cleared. |
Ethernet MAC MII data register (ETH_MACMIIDR)
Address offset: 0x0014
Reset value: 0x0000 0000
The MAC MII Data register stores write data to be written to the PHY register located at the address specified in ETH_MACMIIAR. ETH_MACMIIDR also stores read data from the PHY register located at the address specified by ETH_MACMIIAR.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
MD |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||
| Bits 31:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | MD: MII data |
|
This contains the 16-bit data value read from the PHY after a Management Read operation, or the 16-bit data value to be written to the PHY before a Management Write operation. |
Ethernet MAC flow control register (ETH_MACFCR)
Address offset: 0x0018
Reset value: 0x0000 0000
The Flow control register controls the generation and reception of the control (Pause Command) frames by the MAC. A write to a register with the Busy bit set to '1' causes the MAC to generate a pause control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ZQPD | Res. | PLT | UPFD | RFCE | TFCE | FCB/BPA |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rc_w1/rw |
|||||||||
| Bits 31:16 | PT: Pause time |
|
This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive write operations to this register should be performed only after at least 4 clock cycles in the destination clock domain. |
|
| Bits 15:8 | Reserved, must be kept at reset value. |
| Bit 7 | ZQPD: Zero-quanta pause disable |
|
When set, this bit disables the automatic generation of Zero-quanta pause control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-quanta pause control frame generation is enabled. |
|
| Bit 6 | Reserved, must be kept at reset value. |
| Bits 5:4 | PLT: Pause low threshold |
|
This field configures the threshold of the Pause timer at which the Pause frame is automatically retransmitted. The threshold values should always be less than the Pause Time configured in bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if initiated at 228 (256 – 28) slot- |
|
| Bit 3 | UPFD: Unicast pause frame detect |
|
When this bit is set, the MAC detects the Pause frames with the station’s unicast address specified in the ETH_MACA0HR and ETH_MACA0LR registers, in addition to detecting Pause frames with the unique multicast address. |
|
| Bit 2 | RFCE: Receive flow control enable |
|
When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause Time) time. |
|
| Bit 1 | TFCE: Transmit flow control enable |
|
In Full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. |
|
| Bit 0 | FCB/BPA: Flow control busy/back pressure activate |
|
This bit initiates a Pause Control frame in Full-duplex mode and activates the back pressure function in Half-duplex mode if TFCE bit is set. |
Ethernet MAC VLAN tag register (ETH_MACVLANTR)
Address offset: 0x001C
Reset value: 0x0000 0000
The VLAN tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with 0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, the received VLAN bit in the receive frame status is set. The legal length of the frame is increased from 1518 bytes to 1522 bytes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLANTC |
VLANTI |
|||||||||||||||
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
|||||||||||||||
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | VLANTC: 12-bit VLAN tag comparison |
|
When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. |
|
| Bits 15:0 | VLANTI: VLAN tag identifier (for receive frames) |
|
This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the user priority, Bit[12] is the canonical format indicator (CFI) and bits[11:0] are the VLAN tag’s VLAN identifier (VID) field. When the VLANTC bit is set, only the VID (bits[11:0]) is used for comparison. |
Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
Address offset: 0x0028
Reset value: 0x0000 0000
This is the address through which the remote wakeup frame filter registers are written/read by the application. The Wakeup frame filter register is actually a pointer to eight (not transparent) such wakeup frame filter registers. Eight sequential write operations to this address with the offset (0x0028) will write all wakeup frame filter registers. Eight sequential read operations from this address with the offset (0x0028) will read all wakeup frame filter registers. This register contains the higher 16 bits of the 7th MAC address. Refer to Remote
wakeup frame filter register section for additional information.
| (omitted) |
Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
Address offset: 0x002C
Reset value: 0x0000 0000
The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup events.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WFFRPR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | GU | Res. | Res. | WFR | MPR | Res. | Res. | WFE | MPE | PD |
| rs |
rw | rc_r | rc_r | rw | rw | rs |
| Bit 31 | WFFRPR: Wakeup frame filter register pointer reset |
|
When set, it resets the Remote wakeup frame filter register pointer to 0b000. It is automatically cleared after 1 clock cycle. |
|
| Bits 30:10 | Reserved, must be kept at reset value. |
| Bit 9 | GU: Global unicast |
|
When set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be a wakeup frame. |
|
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | WFR: Wakeup frame received |
|
When set, this bit indicates the power management event was generated due to reception of a wakeup frame. This bit is cleared by a read into this register. |
|
| Bit 5 | MPR: Magic packet received |
|
When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a read into this register. |
|
| Bits 4:3 | Reserved, must be kept at reset value. |
| Bit 2 | WFE: Wakeup frame enable |
|
When set, this bit enables the generation of a power management event due to wakeup frame reception. |
|
| Bit 1 | MPE: Magic Packet enable |
|
When set, this bit enables the generation of a power management event due to Magic Packet reception. |
|
| Bit 0 | PD: Power down |
|
When this bit is set, all received frames will be dropped. This bit is cleared automatically when a magic packet or wakeup frame is received, and Power-down mode is disabled. Frames received after this bit is cleared are forwarded to the application. This bit must only be set when either the Magic Packet Enable or Wakeup Frame Enable bit is set high. |
Ethernet MAC debug register (ETH_MACDBGR)
Address offset: 0x0034
Reset value: 0x0000 0000
This debug register gives the status of all the main modules of the transmit and receive data paths and the FIFOs. An all-zero status indicates that the MAC core is in Idle state (and FIFOs are empty) and no activity is going on in the data paths.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | TFF | TFNE | Res. | TFWA | TFRS | MTP | MTFCS | MMTEA |
Res. | Res. | Res. | Res. | Res. | Res. | RFFL | Res. | RFRCS | RFWRA | Res. | MSFRWCS | MMRPEA |
|||||
| ro | ro | ro | ro | ro | ro | ro | ro | ro |
Res. | Res. | Res. | Res. | Res. | Res. | ro | ro | ro | ro | ro | ro | ro | ro |
|||||||||
| Bits 31:26 | Reserved, must be kept at reset value. |
| Bit 25 | TFF: Tx FIFO full |
|
When high, it indicates that the Tx FIFO is full and hence no more frames will be accepted for transmission. |
|
| Bit 24 | TFNE: Tx FIFO not empty |
|
When high, it indicates that the TxFIFO is not empty and has some data left for transmission. |
|
| Bit 23 | Reserved, must be kept at reset value. |
| Bit 22 | TFWA: Tx FIFO write active |
|
When high, it indicates that the TxFIFO write controller is active and transferring data to the TxFIFO. |
|
| Bits 21:20 | TFRS: Tx FIFO read status |
|
This indicates the state of the TxFIFO read controller: |
|
| Bit 19 | MTP: MAC transmitter in pause |
|
When high, it indicates that the MAC transmitter is in Pause condition (in full-duplex mode only) and hence will not schedule any frame for transmission |
|
| Bits 18:17 | MTFCS: MAC transmit frame controller status |
|
This indicates the state of the MAC transmit frame controller: |
|
| Bit 16 | MMTEA: MAC MII transmit engine active |
|
When high, it indicates that the MAC MII transmit engine is actively transmitting data and that it is not in the Idle state. |
|
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bits 9:8 | RFFL: Rx FIFO fill level |
|
This gives the status of the Rx FIFO fill-level: |
|
| Bit 7 | Reserved, must be kept at reset value. |
| Bits 6:5 | RFRCS: Rx FIFO read controller status |
|
It gives the state of the Rx FIFO read controller: |
|
| Bit 4 | RFWRA: Rx FIFO write controller active |
|
When high, it indicates that the Rx FIFO write controller is active and transferring a received frame to the FIFO. |
|
| Bit 3 | Reserved, must be kept at reset value. |
| Bits 2:1 | MSFRWCS: MAC small FIFO read / write controllers status |
|
When high, these bits indicate the respective active state of the small FIFO read and write controllers of the MAC receive frame controller module. |
|
| Bit 0 | MMRPEA: MAC MII receive protocol engine active |
|
When high, it indicates that the MAC MII receive protocol engine is actively receiving data and is not in the Idle state. |
Ethernet MAC interrupt status register (ETH_MACSR)
Address offset: 0x0038
Reset value: 0x0000 0000
The ETH_MACSR register contents identify the events in the MAC that can generate an interrupt.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | TSTS | Res. | Res. | MMCTS | MMCRS | MMCS | PMTS | Res. | Res. | Res. |
| rc_r | r | r | r | r |
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bit 9 | TSTS: Time stamp trigger status |
|
This bit is set high when the system time value equals or exceeds the value specified in the Target time high and low registers. This bit is cleared by reading the ETH_PTPTSSR register. |
|
| Bits 8:7 | Reserved, must be kept at reset value. |
| Bit 6 | MMCTS: MMC transmit status |
|
This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register. This bit is cleared when all the bits in this interrupt register (ETH_MMCTIR) are cleared. |
|
| Bit 5 | MMCRS: MMC receive status |
|
This bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit is cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared. |
|
| Bit 4 | MMCS: MMC status |
|
This bit is set high whenever any of bits 6:5 is set high. It is cleared only when both bits are low. |
|
| Bit 3 | PMTS: PMT status |
|
This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-down mode (See bits 5 and 6 in the ETH_MACPMTCSR register Ethernet MAC PMT control and |
|
| Bits 2:0 | Reserved, must be kept at reset value. |
Ethernet MAC interrupt mask register (ETH_MACIMR)
Address offset: 0x003C
Reset value: 0x0000 0000
The ETH_MACIMR register bits make it possible to mask the interrupt signal due to the corresponding event in the ETH_MACSR register.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | TSTIM | Res. | Res. | Res. | Res. | Res. | PMTIM | Res. | Res. | Res. |
| rw | rw |
| Bits 15:10 | Reserved, must be kept at reset value. |
| Bit 9 | TSTIM: Time stamp trigger interrupt mask |
|
When set, this bit disables the time stamp interrupt generation. |
|
| Bits 8:4 | Reserved, must be kept at reset value. |
| Bit 3 | PMTIM: PMT interrupt mask |
|
When set, this bit disables the assertion of the interrupt signal due to the setting of the PMT Status bit in ETH_MACSR. |
|
| Bits 2:0 | Reserved, must be kept at reset value. |
Ethernet MAC address 0 high register (ETH_MACA0HR)
Address offset: 0x0040
Reset value: 0x8000 FFFF
The MAC address 0 high register holds the upper 16 bits of the 6-byte first MAC address of the station. Note that the first DA byte that is received on the MII interface corresponds to the LS Byte (bits [7:0]) of the MAC address low register. For example, if 0x1122 3344 5566 is received (0x11 is the first byte) on the MII as the destination address, then the MAC address 0 register [47:0] is compared with 0x6655 4433 2211.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MO | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
MACA0H |
|||||||||||||||
| 1 |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||||
| Bit 31 | MO: Always 1. |
| Bits 30:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | MACA0H: MAC address0 high [47:32] |
|
This field contains the upper 16 bits (47:32) of the 6-byte MAC address0. This is used by the MAC for filtering for received frames and for inserting the MAC address in the transmit flow control (Pause) frames. |
Ethernet MAC address 0 low register (ETH_MACA0LR)
Address offset: 0x0044
Reset value: 0xFFFF FFFF
The MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MACA0L |
MACA0L |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MACA0L: MAC address0 low [31:0] |
|
This field contains the lower 32 bits of the 6-byte MAC address0. This is used by the MAC for filtering for received frames and for inserting the MAC address in the transmit flow control (Pause) frames. |
Ethernet MAC address 1 high register (ETH_MACA1HR)
Address offset: 0x0048
Reset value: 0x0000 FFFF
The MAC address 1 high register holds the upper 16 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AE | SA | MBC |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA1H |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||||||
| Bit 31 | AE: Address enable |
|
When this bit is set, the address filters use the MAC address1 for perfect filtering. When this bit is cleared, the address filters ignore the address for filtering. |
|
| Bit 30 | SA: Source address |
|
When this bit is set, the MAC address1[47:0] is used for comparison with the SA fields of the received frame. |
|
| Bits 29:24 | MBC: Mask byte control |
|
These bits are mask control bits for comparison of each of the MAC address1 bytes. When they are set high, the MAC core does not compare the corresponding byte of received DA/SA with the contents of the MAC address1 registers. Each bit controls the masking of the bytes as follows:
…
|
|
| Bits 23:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | MACA1H: MAC address1 high [47:32] |
|
This field contains the upper 16 bits (47:32) of the 6-byte second MAC address. |
Ethernet MAC address1 low register (ETH_MACA1LR)
Address offset: 0x004C
Reset value: 0xFFFF FFFF
The MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MACA1L |
MACA1L |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MACA1L: MAC address1 low [31:0] |
|
This field contains the lower 32 bits of the 6-byte MAC address1. The content of this field is undefined until loaded by the application after the initialization process. |
Ethernet MAC address 2 high register (ETH_MACA2HR)
Address offset: 0x0050
Reset value: 0x0000 FFFF
The MAC address 2 high register holds the upper 16 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AE | SA | MBC |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA2H |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bit 31 | AE: Address enable |
|
When this bit is set, the address filters use the MAC address2 for perfect filtering. When reset, the address filters ignore the address for filtering. |
|
| Bit 30 | SA: Source address |
|
When this bit is set, the MAC address 2 [47:0] is used for comparison with the SA fields of the received frame. |
|
| Bits 29:24 | MBC: Mask byte control |
|
These bits are mask control bits for comparison of each of the MAC address2 bytes. When set high, the MAC core does not compare the corresponding byte of received DA/SA with the contents of the MAC address 2 registers. Each bit controls the masking of the bytes as follows:
…
|
Bits 23:16Reserved, must be kept at reset value.
Bits 15:0MACA2H: MAC address2 high [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte MAC address2.
Ethernet MAC address 2 low register (ETH_MACA2LR)
Address offset: 0x0054
Reset value: 0xFFFF FFFF
The MAC address 2 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MACA2L |
MACA2L |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MACA2L: MAC address2 low [31:0] |
|
This field contains the lower 32 bits of the 6-byte second MAC address2. The content of this field is undefined until loaded by the application after the initialization process. |
Ethernet MAC address 3 high register (ETH_MACA3HR)
Address offset: 0x0058
Reset value: 0x0000 FFFF
The MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AE | SA | MBC |
Rse. | Rse. | Rse. | Rse. | Rse. | Rse. | Rse. | Rse. | MACA3H |
||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
||||||||
| Bit 31 | AE: Address enable |
|
When this bit is set, the address filters use the MAC address3 for perfect filtering. When this bit is cleared, the address filters ignore the address for filtering. |
|
| Bit 30 | SA: Source address |
|
When this bit is set, the MAC address 3 [47:0] is used for comparison with the SA fields of the received frame. |
|
| Bits 29:24 | MBC: Mask byte control |
|
These bits are mask control bits for comparison of each of the MAC address3 bytes. When these bits are set high, the MAC core does not compare the corresponding byte of received DA/SA with the contents of the MAC address 3 registers. Each bit controls the masking of the bytes as follows:
…
|
|
| Bits 23:16 | Reserved, must be kept at reset value. |
| Bits 15:0 | MACA3H: MAC address3 high [47:32] |
|
This field contains the upper 16 bits (47:32) of the 6-byte MAC address3. |
Ethernet MAC address 3 low register (ETH_MACA3LR)
Address offset: 0x005C
Reset value: 0xFFFF FFFF
The MAC address 3 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MACA3L |
MACA3L |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | MACA3L: MAC address3 low [31:0] |
|
This field contains the lower 32 bits of the 6-byte second MAC address3. The content of this field is undefined until loaded by the application after the initialization process. |
Ethernet MMC control register (ETH_MMCCR)
Address offset: 0x0100
Reset value: 0x0000 0000
The Ethernet MMC Control register establishes the operating mode of the management counters.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCFHP | MCP | MCF | ROR | CSR | CR |
| rw | rw | rw | rw | rw | rw |
| Bits 31:6 | Reserved, must be kept at reset value. |
|
MCFHP: MMC counter Full-Half preset When MCFHP is low and bit4 is set, all MMC counters get preset to almost-half value. All |
When MCFHP is high and bit4 is set, all MMC counters get preset to almost-full value. All frame-counters get preset to 0xFFFF_FFF0 (full - 16)
MCP: MMC counter preset
When set, all counters will be initialized or preset to almost full or almost half as per
with bit5 is useful for debugging and testing the assertion of interrupts due to MMC
counter becoming half-full or full.
| Bit 3 | MCF: MMC counter freeze |
|
When set, this bit freezes all the MMC counters to their current value. (None of the MMC counters are updated due to any transmitted or received frame until this bit is cleared to 0. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode.) |
|
| Bit 2 | ROR: Reset on read |
|
When this bit is set, the MMC counters is reset to zero after read (self-clearing after reset). The counters are cleared when the least significant byte lane (bits [7:0]) is read. |
|
| Bit 1 | CSR: Counter stop rollover |
|
When this bit is set, the counter does not roll over to zero after it reaches the maximum value. |
|
| Bit 0 | CR: Counter reset |
|
When it is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. |
Ethernet MMC receive interrupt register (ETH_MMCRIR)
Address offset: 0x0104
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt register maintains the interrupts generated when receive statistic counters reach half their maximum values. (MSB of the counter is set.) It is
a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective counter must be read in order to clear the interrupt bit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RGUFS | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFAES | RFCES | Res. | Res. | Res. | Res. | Res. |
| rc_r |
rc_r | rc_r |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | RGUFS: Received Good Unicast Frames Status |
|
This bit is set when the received, good unicast frames, counter reaches half the maximum value. |
|
| Bits 16:7 | Reserved, must be kept at reset value. |
| Bit 6 | RFAES: Received frames alignment error status |
|
This bit is set when the received frames, with alignment error, counter reaches half the maximum value. |
|
| Bit 5 | RFCES: Received frames CRC error status |
|
This bit is set when the received frames, with CRC error, counter reaches half the maximum value. |
|
| Bits 4:0 | Reserved, must be kept at reset value. |
Ethernet MMC transmit interrupt register (ETH_MMCTIR)
Address offset: 0x0108
Reset value: 0x0000 0000
The Ethernet MMC transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective counter must be read in order to clear the interrupt bit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGFS | Res. | Res. | Res. | Res. | Res. |
TGFMSCS | TGFSCS | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| rc_r |
rc_r | rc_r |
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | TGFS: Transmitted good frames status |
|
This bit is set when the transmitted, good frames, counter reaches half the maximum value. |
|
| Bits 20:16 | Reserved, must be kept at reset value. |
| Bit 15 | TGFMSCS: Transmitted good frames more single collision status |
|
This bit is set when the transmitted, good frames after more than a single collision, counter reaches half the maximum value. |
|
| Bit 14 | TGFSCS: Transmitted good frames single collision status |
|
This bit is set when the transmitted, good frames after a single collision, counter reaches half the maximum value. |
|
| Bits 13:0 | Reserved, must be kept at reset value. |
Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
Address offset: 0x010C
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt mask register maintains the masks for interrupts generated when the receive statistic counters reach half their maximum value. (MSB of the counter is set.) It is a 32-bit wide register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RGUFM | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFAEM | RFCEM | Res. | Res. | Res. | Res. | Res. |
| rw |
rw | rw |
| Bits 31:18 | Reserved, must be kept at reset value. |
| Bit 17 | RGUFM: Received good unicast frames mask |
|
Setting this bit masks the interrupt when the received, good unicast frames, counter reaches half the maximum value. |
|
| Bits 16:7 | Reserved, must be kept at reset value. |
| Bit 6 | RFAEM: Received frames alignment error mask |
|
Setting this bit masks the interrupt when the received frames, with alignment error, counter reaches half the maximum value. |
|
| Bit 5 | RFCEM: Received frame CRC error mask |
|
Setting this bit masks the interrupt when the received frames, with CRC error, counter reaches half the maximum value. |
|
| Bits 4:0 | Reserved, must be kept at reset value. |
Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
Address offset: 0x0110
Reset value: 0x0000 0000
The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts generated when the transmit statistic counters reach half their maximum value. (MSB of the counter is set). It is a 32-bit wide register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGFM | Res. | Res. | Res. | Res. | Res. |
TGFMSCM | TGFSCM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| rw |
rw | rw |
| Bits 31:22 | Reserved, must be kept at reset value. |
| Bit 21 | TGFM: Transmitted good frames mask |
|
Setting this bit masks the interrupt when the transmitted, good frames, counter reaches half the maximum value. |
|
| Bits 20:16 | Reserved, must be kept at reset value. |
| Bit 15 | TGFMSCM: Transmitted good frames more single collision mask |
|
Setting this bit masks the interrupt when the transmitted good frames after more than a single collision counter reaches half the maximum value. |
|
| Bit 14 | TGFSCM: Transmitted good frames single collision mask |
|
Setting this bit masks the interrupt when the transmitted good frames after a single collision counter reaches half the maximum value. |
|
| Bits 13:0 | Reserved, must be kept at reset value. |
Ethernet MMC transmitted good frames after a single collision counter
register (ETH_MMCTGFSCCR)
Address offset: 0x014C
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after a single collision in Half-duplex mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TGFSCC |
TGFSCC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | TGFSCC: Transmitted good frames single collision counter |
|
Transmitted good frames after a single collision counter. |
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a single collision in Half-duplex mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TGFMSCC |
TGFMSCC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | TGFMSCC: Transmitted good frames more single collision counter |
|
Transmitted good frames after more than a single collision counter |
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TGFC |
TGFC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | TGFC: Transmitted good frames counter |
Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFCEC |
RFCEC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | RFCEC: Received frames CRC error counter |
|
Received frames with CRC error counter |
Ethernet MMC received frames with alignment error counter register
(ETH_MMCRFAECR)
Address offset: 0x0198
Reset value: 0x0000 0000
This register contains the number of frames received with alignment (dribble) error.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFAEC |
RFAEC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | RFAEC: Received frames alignment error counter |
|
Received frames with alignment error counter |
MMC received good unicast frames counter register (ETH_MMCRGUFCR)
Address offset: 0x01C4
Reset value: 0x0000 0000
This register contains the number of good unicast frames received.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RGUFC |
RGUFC |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | RGUFC: Received good unicast frames counter |
This section describes the registers required to support precision network clock synchronization functions under the IEEE 1588 standard.
Ethernet PTP time stamp control register (ETH_PTPTSCR)
Address offset: 0x0700
Reset value: 0x0000 2000
This register controls the time stamp generation and update logic.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSPFF MAE |
TSCNT |
TSSMR ME |
TSSEME | TSSIPV 4FE |
TSSIPV 6FE |
TSSPT POEFE |
TSPTP PSV2E |
TSSSR | TSSAR FE |
Res. | Res. | TTSARU | TSITE | TSSTU | TSSTI | TSFCU | TSE |
| rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bit 18 | TSPFFMAE: Time stamp PTP frame filtering MAC address enable |
|
When set, this bit uses the MAC address (except for MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet. |
|
| Bits 17:16 | TSCNT: Time stamp clock node type |
|
The following are the available types of clock node: |
|
| Bit 15 | TSSMRME: Time stamp snapshot for message relevant to master enable |
|
When this bit is set, the snapshot is taken for messages relevant to the master node only. When this bit is cleared the snapshot is taken for messages relevant to the slave node only. This is valid only for the ordinary clock and boundary clock nodes. |
|
| Bit 14 | TSSEME: Time stamp snapshot for event message enable |
|
When this bit is set, the time stamp snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp). When this bit is cleared the snapshot is taken for all other messages except for Announce, Management and Signaling. |
|
| Bit 13 | TSSIPV4FE: Time stamp snapshot for IPv4 frames enable |
|
When this bit is set, the time stamp snapshot is taken for IPv4 frames. |
|
| Bit 12 | TSSIPV6FE: Time stamp snapshot for IPv6 frames enable |
|
When this bit is set, the time stamp snapshot is taken for IPv6 frames. |
|
| Bit 11 | TSSPTPOEFE: Time stamp snapshot for PTP over ethernet frames enable |
|
When this bit is set, the time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP- |
|
| Bit 10 | TSPTPPSV2E: Time stamp PTP packet snooping for version2 format enable |
|
When this bit is set, the PTP packets are snooped using the version 2 format. When the bit is cleared, the PTP packets are snooped using the version 1 format. IEEE 1588 Version 1 and Version 2 formats as indicated in IEEE standard 1588-2008 |
|
| Bit 9 | TSSSR: Time stamp subsecond rollover: digital or binary rollover control |
|
When this bit is set, the Time stamp low register rolls over when the subsecond counter reaches the value 0x3B9A C9FF (999 999 999 in decimal), and increments the Time Stamp (high) seconds. |
|
| Bit 8 | TSSARFE: Time stamp snapshot for all received frames enable |
|
When this bit is set, the time stamp snapshot is enabled for all frames received by the core. |
|
| Bits 7:6 | Reserved, must be kept at reset value. |
| Bit 5 | TSARU: Time stamp addend register update |
|
When this bit is set, the Time stamp addend register’s contents are updated to the PTP block for fine correction. This bit is cleared when the update is complete. This register bit must be read as zero before you can set it. |
|
| Bit 4 | TSITE: Time stamp interrupt trigger enable |
|
When this bit is set, a time stamp interrupt is generated when the system time becomes greater than the value written in the Target time register. When the Time stamp trigger interrupt is generated, this bit is cleared. |
|
| Bit 3 | TSSTU: Time stamp system time update |
|
When this bit is set, the system time is updated (added to or subtracted from) with the value specified in the Time stamp high update and Time stamp low update registers. Both the TSSTU and TSSTI bits must be read as zero before you can set this bit. Once the update is completed in hardware, this bit is cleared. |
|
| Bit 2 | TSSTI: Time stamp system time initialize |
|
When this bit is set, the system time is initialized (overwritten) with the value specified in the Time stamp high update and Time stamp low update registers. This bit must be read as zero before you can set it. When initialization is complete, this bit is cleared. |
|
| Bit 1 | TSFCU: Time stamp fine or coarse update |
|
When set, this bit indicates that the system time stamp is to be updated using the Fine Update method. When cleared, it indicates the system time stamp is to be updated using the Coarse method. |
|
| Bit 0 | TSE: Time stamp enable |
|
When this bit is set, time stamping is enabled for transmit and receive frames. When this bit is cleared, the time stamp function is suspended and time stamps are not added for transmit and receive frames. Because the maintained system time is suspended, you must always initialize the time stamp feature (system time) after setting this bit high. |
The table below indicates the messages for which a snapshot is taken depending on the clock, enable master and enable snapshot for event message register settings.
| TSCNT (bits 17:16) |
TSSMRME (bit 15)(1) |
TSSEME (bit 14) |
Messages for which snapshots are taken |
|---|---|---|---|
| 00 or 01 | X(2) |
0 | SYNC, Follow_Up, Delay_Req, Delay_Resp |
| 00 or 01 | 1 | 1 | Delay_Req |
| 00 or 01 | 0 | 1 | SYNC |
| 10 | N/A | 0 | SYNC, Follow_Up, Delay_Req, Delay_Resp |
| 10 | N/A | 1 | SYNC, Follow_Up |
| 11 | N/A | 0 | SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp |
| 11 | N/A | 1 | SYNC, Pdelay_Req, Pdelay_Resp |
Ethernet PTP subsecond increment register (ETH_PTPSSIR)
Address offset: 0x0704
Reset value: 0x0000 0000
This register contains the 8-bit value by which the subsecond register is incremented. In Coarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to
the system time every clock cycle of HCLK. In Fine update mode, the value in this register is added to the system time whenever the accumulator gets an overflow.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STSSI |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | STSSI: System time subsecond increment |
|
The value programmed in this register is added to the contents of the subsecond value of the system time in every update. For example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2A). |
Ethernet PTP time stamp high register (ETH_PTPTSHR)
Address offset: 0x0708
Reset value: 0x0000 0000
This register contains the most significant (higher) 32 time bits. This read-only register contains the seconds system time value. The Time stamp high register, along with Time stamp low register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS |
STS |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | STS: System time second |
|
The value in this field indicates the current value in seconds of the System Time maintained by the core. |
Ethernet PTP time stamp low register (ETH_PTPTSLR)
Address offset: 0x070C
Reset value: 0x0000 0000
This register contains the least significant (lower) 32 time bits. This read-only register contains the subsecond system time value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STPNS | STSS |
STSS |
|||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bit 31 | STPNS: System time positive or negative sign |
|
This bit indicates a positive or negative time value. When set, the bit indicates that time representation is negative. When cleared, it indicates that time representation is positive. Because the system time should always be positive, this bit is normally zero. |
|
| Bits 30:0 | STSS: System time subseconds |
|
The value in this field has the subsecond time representation, with 0.46 ns accuracy. |
Ethernet PTP time stamp high update register (ETH_PTPTSHUR)
Address offset: 0x0710
Reset value: 0x0000 0000
This register contains the most significant (higher) 32 bits of the time to be written to, added to, or subtracted from the System Time value. The Time stamp high update register, along with the Time stamp update low register, initializes or updates the system time maintained by the MAC. You have to write both of these registers before setting the TSSTI or TSSTU bits in the Time stamp control register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TSUS |
TSUS |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TSUS: Time stamp update second |
|
The value in this field indicates the time, in seconds, to be initialized or added to the system time. |
Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
Address offset: 0x0714
Reset value: 0x0000 0000
This register contains the least significant (lower) 32 bits of the time to be written to, added to, or subtracted from the System Time value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TSUPNS | TSUSS |
TSUSS |
|||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bit 31 | TSUPNS: Time stamp update positive or negative sign |
|
This bit indicates positive or negative time value. When set, the bit indicates that time representation is negative. When cleared, it indicates that time representation is positive. When TSSTI is set (system time initialization) this bit should be zero. If this bit is set when TSSTU is set, the value in the Time stamp update registers is subtracted from the system time. Otherwise it is added to the system time. |
|
| Bits 30:0 | TSUSS: Time stamp update subseconds |
|
The value in this field indicates the subsecond time to be initialized or added to the system time. This value has an accuracy of 0.46 ns (in other words, a value of 0x0000_0001 is 0.46 ns). |
Ethernet PTP time stamp addend register (ETH_PTPTSAR)
Address offset: 0x0718
Reset value: 0x0000 0000
This register is used by the software to readjust the clock frequency linearly to match the master clock frequency. This register value is used only when the system time is configured for Fine update mode (TSFCU bit in ETH_PTPTSCR). This register content is added to a 32-bit accumulator in every clock cycle and the system time is updated whenever the accumulator overflows.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TSA |
TSA |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TSA: Time stamp addend |
|
This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. |
Ethernet PTP target time high register (ETH_PTPTTHR)
Address offset: 0x071C
Reset value: 0x0000 0000
This register contains the higher 32 bits of time to be compared with the system time for interrupt event generation. The Target time high register, along with Target time low register, is used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time exceeds the value programmed in these registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TTSH |
TTSH |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TTSH: Target time stamp high |
|
This register stores the time in seconds. When the time stamp value matches or exceeds both Target time stamp registers, the MAC, if enabled, generates an interrupt. |
Ethernet PTP target time low register (ETH_PTPTTLR)
Address offset: 0x0720
Reset value: 0x0000 0000
This register contains the lower 32 bits of time to be compared with the system time for interrupt event generation.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TTSL |
TTSL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | TTSL: Target time stamp low |
|
This register stores the time in (signed) nanoseconds. When the value of the time stamp matches or exceeds both Target time stamp registers, the MAC, if enabled, generates an interrupt. |
Ethernet PTP time stamp status register (ETH_PTPTSSR)
Address offset: 0x0728
Reset value: 0x0000 0000
This register contains the time stamp status register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSTTR | TSSO |
| ro | ro |
| Bits 31:2 | Reserved, must be kept at reset value. |
| Bit 1 | TSTTR: Time stamp target time reached |
|
When set, this bit indicates that the value of the system time is greater than or equal to the value specified in the Target time high and low registers. This bit is cleared when the ETH_PTPTSSR register is read. |
|
| Bit 0 | TSSO: Time stamp second overflow |
|
When set, this bit indicates that the second value of the time stamp has overflowed beyond 0xFFFF FFFF. |
Ethernet PTP PPS control register (ETH_PTPPPSCR)
Address offset: 0x072C
Reset value: 0x0000 0000
This register controls the frequency of the PPS output.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PPSFREQ |
|||
| rw | rw | rw | rw |
||||||||||||||||||||||||||||
| Bits 31:4 | Reserved, must be kept at reset value. |
| Bits 3:0 | PPSFREQ: PPS frequency selection |
|
The PPS output frequency is set to 2PPSFREQ Hz. If digital rollover is used (TSSSR=1, bit 9 in ETH_PTPTSCR), it is recommended not to |
This section defines the bits for each DMA register. Non-32 bit accesses are allowed as long as the address is word-aligned.
Ethernet DMA bus mode register (ETH_DMABMR)
Address offset: 0x1000
Reset value: 0x0002 0101
The bus mode register establishes the bus operating modes for the DMA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | MB | AAB | FPM | USP | RDP | FB |
PM | PBL | EDFE | DSL | DA | SR |
|||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rs |
|||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | MB: Mixed burst |
|
When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of a length greater than 16 with INCR (undefined burst). When this bit is cleared, it reverts to fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below. |
|
| Bit 25 | AAB: Address-aligned beats |
|
When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer’s start address) is not aligned, but subsequent bursts are aligned to the address. |
|
| Bit 24 | FPM: 4xPBL mode |
|
When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) four times. Thus the DMA transfers data in a maximum of 4, 8, 16, 32, 64 and 128 beats depending on the PBL value. |
|
| Bit 23 | USP: Use separate PBL |
|
When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When this bit is cleared, the PBL value in bits [13:8] is applicable for both DMA engines. |
|
| Bits 22:17 | RDP: Rx DMA PBL |
|
These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This is the maximum value that is used in a single block read/write operation. The RxDMA always attempts to burst as specified in RDP each time it starts a burst transfer on the host bus. RDP can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. |
|
| Bit 16 | FB: Fixed burst |
|
This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB uses only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB uses SINGLE and INCR burst transfer operations. |
|
| Bits 15:14 | PM: Rx Tx priority ratio |
|
RxDMA requests are given priority over TxDMA requests in the following ratio:
00: 1:1 |
|
| Bits 13:8 | PBL: Programmable burst length |
|
These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block read/write operation. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set, this PBL value is applicable for TxDMA transactions only.
|
|
| Bit 7 | EDFE: Enhanced descriptor format enable |
|
When this bit is set, the enhanced descriptor format is enabled and the descriptor size is increased to 32 bytes (8 DWORDS). This is required when time stamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1, ETH_MACCR bit 10). |
|
| Bits 6:2 | DSL: Descriptor skip length |
|
This bit specifies the number of words to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, the descriptor table is taken as contiguous by the DMA, in Ring mode. |
|
| Bit 1 | DA: DMA Arbitration |
|
0: Round-robin with Rx:Tx priority given in bits [15:14] |
|
| Bit 0 | SR: Software reset |
|
When this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. |
Ethernet DMA transmit poll demand register (ETH_DMATPDR)
Address offset: 0x1004
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the transmit descriptor list. The transmit poll demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA. The Transmit Poll Demand command is given to wake up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an underflow error in a transmitted frame or due to the unavailability of descriptors owned by
transmit DMA. User can issue this command anytime and the TxDMA resets it once it starts re-fetching the current descriptor from host memory.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TPD |
TPD |
||||||||||||||||||||||||||||||
| rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt |
rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt |
| Bits 31:0 | TPD: Transmit poll demand |
|
When these bits are written with any value, the DMA reads the current descriptor pointed to by the ETH_DMACHTDR register. If that descriptor is not available (owned by Host), transmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the descriptor is available, transmission resumes. |
EHERNET DMA receive poll demand register (ETH_DMARPDR)
Address offset: 0x1008
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the receive descriptor list. The Receive poll demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from Suspend state. The RxDMA can go into Suspend state only due to the unavailability of descriptors owned by it.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RPD |
RPD |
||||||||||||||||||||||||||||||
| rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt |
rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt | rw_wt |
| Bits 31:0 | RPD: Receive poll demand |
|
When these bits are written with any value, the DMA reads the current descriptor pointed to by the ETH_DMACHRDR register. If that descriptor is not available (owned by Host), reception returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If the descriptor is available, the Receive DMA returns to active state. |
Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)
Address offset: 0x100C
Reset value: 0x0000 0000
The Receive descriptor list address register points to the start of the receive descriptor list. The descriptor list resides in the STM32F76xxx and STM32F77xxx physical memory space and must be word-aligned. The DMA internally converts it to bus-width aligned address by making the corresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted only when reception is stopped. When stopped, the ETH_DMARDLAR register must be written to before the receive Start command is given.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SRL |
SRL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | SRL: Start of receive list |
|
This field contains the base address of the first descriptor in the receive descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the DMA. Hence these LSB bits are read only. |
Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)
Address offset: 0x1010
Reset value: 0x0000 0000
The Transmit descriptor list address register points to the start of the transmit descriptor list. The descriptor list resides in the STM32F76xxx and STM32F77xxx physical memory space and must be word-aligned. The DMA internally converts it to bus-width-aligned address by taking the corresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when transmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register can be written before the transmission Start command is given.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STL |
STL |
||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:0 | STL: Start of transmit list |
|
This field contains the base address of the first descriptor in the transmit descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the DMA. Hence these LSB bits are read-only. |
Ethernet DMA status register (ETH_DMASR)
Address offset: 0x1014
Reset value: 0x0000 0000
The Status register contains all the status bits that the DMA reports to the application. The ETH_DMASR register is usually read by the software driver during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The ETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in ETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0]) can be masked by masking the appropriate bit in the ETH_DMAIER register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | TSTS | PMTS | MMCS | Res. | EBS | TPS | RPS | NIS |
AIS | ERS | FBES | Res. | Res. | ETS | RWTS | RPSS | RBUS | RS | TUS | ROS | TJTS | TBUS | TPSS | TS |
||||||
| r | r | r | r | r | r | r | r | r | r | r | r | rc-w1 |
rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 | rc-w1 |
|||||
| Bits 31:30 | Reserved, must be kept at reset value. |
| Bit 29 | TSTS: Time stamp trigger status |
|
This bit indicates an interrupt event in the MAC core's Time stamp generator block. The software must read the MAC core’s status register, clearing its source (bit 9), to reset this bit to 0. When this bit is high an interrupt is generated if enabled. |
|
| Bit 28 | PMTS: PMT status |
|
This bit indicates an event in the MAC core’s PMT. The software must read the corresponding registers in the MAC core to get the exact cause of interrupt and clear its source to reset this bit to 0. The interrupt is generated when this bit is high if enabled. |
|
| Bit 27 | MMCS: MMC status |
|
This bit reflects an event in the MMC of the MAC core. The software must read the corresponding registers in the MAC core to get the exact cause of interrupt and clear the source of interrupt to make this bit as 0. The interrupt is generated when this bit is high if enabled. |
|
| Bit 26 | Reserved, must be kept at reset value. |
| Bits 25:23 | EBS: Error bits status |
|
These bits indicate the type of error that caused a bus error (error response on the AHB interface). Valid only with the fatal bus error bit (ETH_DMASR register [13]) set. This field does not generate an interrupt. Error during data transfer by TxDMA 0 Error during data transfer by RxDMA 1 Error during read transfer 0 Error during write transfer 1 Error during descriptor access 0 Error during data buffer access |
|
| Bits 22:20 | TPS: Transmit process state |
|
These bits indicate the Transmit DMA FSM state. This field does not generate an interrupt. |
|
| Bits 19:17 | RPS: Receive process state |
|
These bits indicate the Receive DMA FSM state. This field does not generate an interrupt. |
|
| Bit 16 | NIS: Normal interrupt summary |
|
The normal interrupt summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMAIER register:
|
|
| Bit 15 | AIS: Abnormal interrupt summary |
|
The abnormal interrupt summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMAIER register:
|
|
| Bit 14 | ERS: Early receive status |
|
This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt ETH_DMASR [6] automatically clears this bit. |
|
| Bit 13 | FBES: Fatal bus error status |
|
This bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses. |
|
| Bits 12:11 | Reserved, must be kept at reset value. |
| Bit 10 | ETS: Early transmit status |
|
This bit indicates that the frame to be transmitted was fully transferred to the Transmit FIFO. |
|
| Bit 9 | RWTS: Receive watchdog timeout status This bit is asserted when a frame with a length greater than 2 048 bytes is received. |
| Bit 8 | RPSS: Receive process stopped status |
|
This bit is asserted when the receive process enters the Stopped state. |
|
| Bit 7 | RBUS: Receive buffer unavailable status |
|
This bit indicates that the next descriptor in the receive list is owned by the host and cannot be acquired by the DMA. Receive process is suspended. To resume processing receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, receive process resumes when the next recognized incoming frame is received. ETH_DMASR [7] is set only when the previous receive descriptor was owned by the DMA. |
|
| Bit 6 | RS: Receive status |
|
This bit indicates the completion of the frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state. |
|
| Bit 5 | TUS: Transmit underflow status |
|
This bit indicates that the transmit buffer had an underflow during frame transmission. Transmission is suspended and an underflow error TDES0[1] is set. |
|
| Bit 4 | ROS: Receive overflow status |
|
This bit indicates that the receive buffer had an overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. |
|
| Bit 3 | TJTS: Transmit jabber timeout status |
|
This bit indicates that the transmit jabber timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the transmit jabber timeout TDES0[14] flag to be asserted. |
|
| Bit 2 | TBUS: Transmit buffer unavailable status |
|
This bit indicates that the next descriptor in the transmit list is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits [22:20] explain the transmit process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command. |
|
| Bit 1 | TPSS: Transmit process stopped status |
|
This bit is set when the transmission is stopped. |
|
| Bit 0 | TS: Transmit status |
|
This bit indicates that frame transmission is finished and TDES1[31] is set in the first descriptor. |
Ethernet DMA operation mode register (ETH_DMAOMR)
Address offset: 0x1018
Reset value: 0x0000 0000
The operation mode register establishes the Transmit and Receive operating modes and commands. The ETH_DMAOMR register should be the last CSR to be written as part of DMA initialization.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | DTCEFD | RSF | DFRF | Res. | Res. | TSF | FTF | Res. | Res. | Res. | TTC |
TTC | ST | Res. | Res. | Res. | Res. | Res. | FEF | FUGF | Res. | RTC | OSF | SR | Res. |
||
| rw | rw | rw | rw | rs | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||||||||||||
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | DTCEFD: Dropping of TCP/IP checksum error frames disable |
|
When this bit is set, the core does not drop frames that only have errors detected by the receive checksum offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors in the encapsulated payload only. When this bit is cleared, all error frames are dropped if the FEF bit is reset. |
|
| Bit 25 | RSF: Receive store and forward |
|
When this bit is set, a frame is read from the Rx FIFO after the complete frame has been written to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through mode, subject to the threshold specified by the RTC bits. |
|
| Bit 24 | DFRF: Disable flushing of received frames |
|
When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is cleared. (See Receive |
|
| Bits 23:22 | Reserved, must be kept at reset value. |
| Bit 21 | TSF: Transmit store and forward |
|
When this bit is set, transmission starts when a full frame resides in the Transmit FIFO. When this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are ignored. |
|
| Bit 20 | FTF: Flush transmit FIFO |
|
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing operation is complete. The Operation mode register should not be written to until this bit is cleared. |
|
| Bits 19:17 | Reserved, must be kept at reset value. |
| Bits 16:14 | TTC: Transmit threshold control |
|
These three bits control the threshold level of the Transmit FIFO. Transmission starts when the frame size within the Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is cleared. |
|
| Bit 13 | ST: Start/stop transmission |
|
When this bit is set, transmission is placed in the Running state, and the DMA checks the transmit list at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the transmit list base address set by the ETH_DMATDLAR register, or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and the transmit buffer unavailable bit (ETH_DMASR [2]) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA ETH_DMATDLAR register, the DMA behavior is unpredictable. |
|
| Bits 12:8 | Reserved, must be kept at reset value. |
| Bit 7 | FEF: Forward error frames |
|
When this bit is set, all frames except runt error frames are forwarded to the DMA. |
|
| Bit 6 | FUGF: Forward undersized good frames |
|
When this bit is set, the Rx FIFO forwards undersized frames (frames with no error and length less than 64 bytes) including pad-bytes and CRC). |
|
| Bit 5 | Reserved, must be kept at reset value. |
| Bits 4:3 | RTC: Receive threshold control |
|
These two bits control the threshold level of the Receive FIFO. Transfer (request) to DMA starts when the frame size within the Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically.
Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes.
These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is 00: 64 |
|
| Bit 2 | OSF: Operate on second frame |
|
When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained. |
|
| Bit 1 | SR: Start/stop receive |
|
When this bit is set, the receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA ETH_DMARDLAR register or the position retained when the receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and the receive buffer unavailable bit (ETH_DMASR [7]) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA ETH_DMARDLAR register, the DMA behavior is unpredictable. |
|
| Bit 0 | Reserved, must be kept at reset value. |
Ethernet DMA interrupt enable register (ETH_DMAIER)
Address offset: 0x101C
Reset value: 0x0000 0000
The Interrupt enable register enables the interrupts reported by ETH_DMASR. Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NISE |
AISE | ERIE | FBEIE | Res. | Res. | ETIE | RWTIE | RPSIE | RBUIE | RIE | TUIE | ROIE | TJTIE | TBUIE | TPSIE | TIE |
| rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:17 | Reserved, must be kept at reset value. |
| Bit 16 | NISE: Normal interrupt summary enable |
|
When this bit is set, a normal interrupt is enabled. When this bit is cleared, a normal interrupt is disabled. This bit enables the following bits:
|
|
| Bit 15 | AISE: Abnormal interrupt summary enable |
|
When this bit is set, an abnormal interrupt is enabled. When this bit is cleared, an abnormal interrupt is disabled. This bit enables the following bits:
|
|
| Bit 14 | ERIE: Early receive interrupt enable |
|
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]), the early receive interrupt is enabled. |
|
| Bit 13 | FBEIE: Fatal bus error interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the fatal bus error interrupt is enabled. |
|
| Bits 12:11 | Reserved, must be kept at reset value. |
| Bit 10 | ETIE: Early transmit interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register [15]), the early transmit interrupt is enabled. |
|
| Bit 9 | RWTIE: receive watchdog timeout interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive watchdog timeout interrupt is enabled. |
|
| Bit 8 | RPSIE: Receive process stopped interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive stopped interrupt is enabled. When this bit is cleared, the receive stopped interrupt is disabled. |
|
| Bit 7 | RBUIE: Receive buffer unavailable interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive buffer unavailable interrupt is enabled. |
|
| Bit 6 | RIE: Receive interrupt enable |
|
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]), the receive interrupt is enabled. |
|
| Bit 5 | TUIE: Underflow interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the transmit underflow interrupt is enabled. |
|
| Bit 4 | ROIE: Overflow interrupt enable When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive overflow interrupt is enabled. When this bit is cleared, the overflow interrupt is disabled. |
| Bit 3 | TJTIE: Transmit jabber timeout interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the transmit jabber timeout interrupt is enabled. |
|
| Bit 2 | TBUIE: Transmit buffer unavailable interrupt enable |
|
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]), the transmit buffer unavailable interrupt is enabled. |
|
| Bit 1 | TPSIE: Transmit process stopped interrupt enable |
|
When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the transmission stopped interrupt is enabled. |
|
| Bit 0 | TIE: Transmit interrupt enable |
|
When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]), the transmit interrupt is enabled. |
The Ethernet interrupt is generated only when the TSTS or PMTS bits of the DMA Status register is asserted with their corresponding interrupt are unmasked, or when the NIS/AIS Status bit is asserted and the corresponding Interrupt Enable bits (NISE/AISE) are enabled.
Ethernet DMA missed frame and buffer overflow counter register
(ETH_DMAMFBOCR)
Address offset: 0x1020
Reset value: 0x0000 0000
The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits [15:0] indicate missed frames due to the STM32F76xxx and STM32F77xxx buffer being unavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | OFOC | MFA | OMFC |
MFC |
|||||||||||||||||||||||||
| rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r |
rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r | rc_r |
|||
| Bits 31:29 | Reserved, must be kept at reset value. |
| Bit 28 | OFOC: Overflow bit for FIFO overflow counter |
| Bits 27:17 | MFA: Missed frames by the application |
|
Indicates the number of frames missed by the application |
|
| Bit 16 | OMFC: Overflow bit for missed frame counter |
| Bits 15:0 | MFC: Missed frames by the controller |
|
Indicates the number of frames missed by the Controller due to the host receive buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. |
Ethernet DMA receive status watchdog timer register (ETH_DMARSWTR)
Address offset: 0x1024
Reset value: 0x0000 0000
This register, when written with a non-zero value, enables the watchdog timer for the receive status (RS, ETH_DMASR[6]).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RSWTC |
|||||||
| rw | rw | rw | rw | rw | rw | rw | rw |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | RSWTC: Receive status (RS) watchdog timer count |
|
Indicates the number of HCLK clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RS status bit is not set due to the setting of RDES1[31] in the corresponding descriptor. When the watchdog timer runs out, the RS bit is set and the timer is stopped. The watchdog timer is reset when the RS bit is set high due to automatic setting of RS as per RDES1[31] of any received frame. |
Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
Address offset: 0x1048
Reset value: 0x0000 0000
The Current host transmit descriptor register points to the start address of the current transmit descriptor read by the DMA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HTDAP |
HTDAP |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | HTDAP: Host transmit descriptor address pointer |
|
Cleared . Pointer updated by DMA during operation. |
Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
Address offset: 0x104C
Reset value: 0x0000 0000
The Current host receive descriptor register points to the start address of the current receive descriptor read by the DMA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HRDAP |
HRDAP |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | HRDAP: Host receive descriptor address pointer |
|
Cleared On Reset. Pointer updated by DMA during operation. |
Ethernet DMA current host transmit buffer address register
(ETH_DMACHTBAR)
Address offset: 0x1050
Reset value: 0x0000 0000
The Current host transmit buffer address register points to the current transmit buffer address being read by the DMA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HTBAP |
HTBAP |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | HTBAP: Host transmit buffer address pointer |
|
Cleared On Reset. Pointer updated by DMA during operation. |
Ethernet DMA current host receive buffer address register
(ETH_DMACHRBAR)
Address offset: 0x1054
Reset value: 0x0000 0000
The current host receive buffer address register points to the current receive buffer address being read by the DMA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HRBAP |
HRBAP |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | HRBAP: Host receive buffer address pointer |
|
Cleared On Reset. Pointer updated by DMA during operation. |
Table 310 gives the ETH register map and reset values.
| Off- set |
Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
ETH_MACCR |
Res. | Res. | Res. | Res. | Res. | Res. | CSTF | Res. | WD | JD | Res. | Res. | IFG |
CSD | Res. | FES | ROD | LM | DM | IPCO | RD | Res. | APCS | BL | DC | TE | RE | Res. | Res. | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||
| 0x04 |
ETH_MACFFR | RA |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HPF | SAF | SAIF | PCF | BFD | PAM | DAIF | HM | HU | PM | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||
| 0x08 | ETH_MACHTHR | HTH[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x0C | ETH_MACHTLR | HTL[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x10 |
ETH_MACMIIAR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | PA | MR |
CR | M W |
MB |
|||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x14 |
ETH_MACMIIDR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MD |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||
| 0x18 |
ETH_MACFCR | PT |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ZQPD | Res. | PLT |
UPFD | RFCE | TFCE | FCB/BPA | ||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||
| 0x1C |
ETH_MACVLANT R |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | VLANTC | VLANTI |
|||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x28 |
ETH_MACRWUF FR |
Frame filter reg0\Frame filter reg1\Frame filter reg2\Frame filter reg3\Frame filter reg4\...\Frame filter reg7 |
|||||||||||||||||||||||||||||||
| Reset value | 0 |
||||||||||||||||||||||||||||||||
| 0x2C | ETH_MACPMTC SR |
WFFRPR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GU | Res. | Res. | WFR | MPR | Res. | Res. | WFE | MPE | PD |
| - | Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x34 |
ETH_MACDBGR |
Res. | Res. | Res. | Res. | Res. | Res. | TFF | TFNEGU | Res. | TFWA | TFRS | MTP | MTFCS | MMTEA | Res. | Res. | Res. | Res. | Res. | Res. | RFFL | Res. | RFRCS | RFWRA | Res. | MSFRWCS | MMRPEA | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x38 |
ETH_MACSR |
- |
Res. | Res. | Res. | Res. | Res. | Res. | TSTS | Res. | Res. | MMCTS | MMCRS | MMCS | PMTS | Res. | Res. | Res. | |||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
| 0x3C |
ETH_MACIMR |
- | Res. | Res. | Res. | Res. | Res. | Res. | TSTIM | Res. | Res. | Res. | Res. | Res. | PMTIM | Res. | Res. | Res. | |||||||||||||||
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x40 | ETH_MACA0HR |
MO | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA0H |
|||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | ||||||||||||||||
| 0x44 | ETH_MACA0LR | MACA0L |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x48 |
ETH_MACA1HR | AE | SA | MBC[6:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA1H |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||
| 0x4C | ETH_MACA1LR | MACA1L |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x50 |
ETH_MACA2HR | AE | SA | MBC |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA2H |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||
| 0x54 | ETH_MACA2LR | MACA2L |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x58 |
ETH_MACA3HR | AE | SA | MBC |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MACA3H |
||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|||||||||
| 0x5C | ETH_MACA3LR | MACA3L |
|||||||||||||||||||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|
| 0x100 |
ETH_MMCCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MCFHP | MCP | MCF | ROR | CSR | CR |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||||
| 0x104 |
ETH_MMCRIR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RGUFS | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFAES | RFCES | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x108 |
ETH_MMCTIR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGFS | Res. | Res. | Res. | Res. | Res. | TGFMSCS | TGFSCS | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x10C |
ETH_MMCRIMR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RGUFM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RFAEM | RFCEM | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x110 |
ETH_MMCTIMR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TGFM | Res. | Res. | Res. | Res. | Res. | TGFMSCM | TGFSCM | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x14C |
ETH_MMCTGFS CCR |
TGFSCC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x150 |
ETH_MMCTGFM SCCR |
TGFMSCC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x168 |
ETH_MMCTGFC R |
TGFC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x194 |
ETH_MMCRFCE CR |
RFCEC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x198 |
ETH_MMCRFAE CR |
RFAEC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1C4 |
ETH_MMCRGUF CR |
RGUFC |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x700 |
ETH_PTPTSCR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSPFFMAE | TSCNT | TSSMRME | TSSEME | TSSIPV4FE | TSSIPV6FE | TSSPTPOEFE | TSPTPPSV2E | TSSSR | TSSARFE | Res. | Res. | TTSARU | TSITE | TSSTU | TSSTI | TSFCU | TSE | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||
| 0x704 |
ETH_PTPSSIR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | STSSI |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x708 | ETH_PTPTSHR | STS[31:0] |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x70C | ETH_PTPTSLR |
STPNS | STSS |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x710 | ETH_PTPTSHUR | TSUS |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x714 | ETH_PTPTSLUR |
TSUPNS | TSUSS |
||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x718 | ETH_PTPTSAR | TSA |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x71C | ETH_PTPTTHR | TTSH |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x720 | ETH_PTPTTLR | TTSL |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x728 |
ETH_PTPTSSR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSTTR | TSSO |
| Reset value | 0 | 0 |
|||||||||||||||||||||||||||||||
| 0x1000 |
ETH_DMABMR |
Res. | Res. | Res. | Res. | Res. | MB | AAB | FPM | USP | RDP |
FB | PM | PBL |
EDFE | DSL |
DA | SR | |||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
||||||
| 0x1004 | ETH_DMATPDR | TPD |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1008 | ETH_DMARPDR | RPD |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x100C |
ETH_DMARDLA R |
SRL |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1010 | ETH_DMATDLAR | STL |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1014 |
ETH_DMASR |
Res. | Res. | TSTS | PMTS | MMCS | Res. | EBS | TPS | RPS | NIS | AIS | ERS | FBES | Res. | Res. | ETS | RWTS | RPSS | RBUS | RS | TUS | ROS | TJTS | TBUS | TPSS | TS | ||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||
| 0x1018 |
ETH_DMAOMR |
Res. | Res. | Res. | Res. | Res. | DTCEFD | RSF | DFRF | Res. | Res. | TSF | FTF | Res. | Res. | Res. | TTC | ST | Res. | Res. | Res. | Res. | Res. | FEF | FUGF | Res. | RTC | OSF | SR | Res. | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x101C |
ETH_DMAIER |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | NISE | AISE | ERIE | FBEIE | Res. | Res. | ETIE | RWTIE | RPSIE | RBUIE | RIE | TUIE | ROIE | TJTIE | TBUIE | TPSIE | TIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||
| 0x1020 |
ETH_DMAMFBO CR |
Res. | Res. | Res. | OFOC | MFA | OMFC | MFC |
|||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||
| 0x1024 |
ETH_ DMARSWTR |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RSWTC |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x1048 |
ETH_ DMACHTDR |
HTDAP |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x104C |
ETH_ DMACHRDR |
HRDAP |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1050 |
ETH_ DMACHTBAR |
HTBAP |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
| 0x1054 |
ETH_ DMACHRBAR |
HRBAP |
|||||||||||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
Consumer electronics control (CEC) is part of HDMI (high-definition multimedia interface) standard as appendix supplement 1. It contains a protocol that provides high-level control functions between various audiovisual products. CEC operates at low speeds, with minimum processing and memory overhead.
The HDMI-CEC controller provides hardware support for this protocol.
The CEC bus consists of a single bidirectional line that is used to transfer data in and out of the device. It is connected to a +3.3 V supply voltage via a 27 kΩ pull-up resistor. The output stage of the device must have an open-drain or open-collector to allow a wired-AND connection.
The HDMI-CEC controller manages the CEC bidirectional line as an alternate function of a standard GPIO, assuming that it is configured as alternate function open drain. The 27 kΩ
pull-up must be added externally to the microcontroller.
To not interfere with the CEC bus when the application power is removed, it is mandatory to isolate the CEC pin from the bus in such conditions. This can be done by using a MOS transistor, as shown on Figure 577.
| Name | Signal type | Remarks |
|---|---|---|
| CEC | Bidirectional |
Two states:
A 27 kΩ resistor must be added externally. |
| (omitted) |
All transactions on the CEC line consist of an initiator and one or more followers. The initiator is responsible for sending the message structure and the data. The follower is the recipient of any data and is responsible for setting any acknowledgment bits.
A message is conveyed in a single frame that consists of a start bit followed by a header block and optionally an opcode and a variable number of operand blocks.
All these blocks are made of a 8-bit payload - most significant bit is transmitted first - followed by an end of message (EOM) bit and an acknowledge (ACK) bit.
The EOM bit is set in the last block of a message and kept reset in all others. In case a message contains additional blocks after an EOM is indicated, those additional blocks must be ignored. The EOM bit may be set in the header block to ‘ping’ other devices, to make sure they are active.
The acknowledge bit is always set to high impedance by the initiator so that it can be driven low either by the follower that has read its own address in the header, or by the follower that needs to reject a broadcast message.
The header consists of the source logical address field, and the destination logical address field. Note that the special address 0xF is used for broadcast messages.
| (omitted) |
| (omitted) |
The format of the start bit is unique and identifies the start of a message. It must be validated by its low duration and its total duration.
All remaining data bits in the message, after the start bit, have consistent timing. The high-to-low transition at the end of the data bit is the start of the next data bit except for the final bit where the CEC line remains high.
| (omitted) |
All devices transmitting - or retransmitting - a message onto the CEC line must ensure that it has been inactive for a number of bit periods. This signal-free time is defined as the time starting from the final bit of the previous frame and depends on the initiating device and the current status as shown in the table below.
| (omitted) |
Since only one initiator is allowed at any one time, an arbitration mechanism is provided to avoid conflict when more than one initiator begins transmitting at the same time.
CEC line arbitration starts with the leading edge of the start bit and continues until the end of the initiator address bits within the header block. During this period, the initiator must monitor the CEC line, if whilst driving the line to high impedance it reads it back to 0. Assuming then it has lost arbitration, it stops transmitting and becomes a follower.
| (omitted) |
Figure 583 shows an example for a SFT of three nominal bit periods
| (omitted) |
A configurable time window is counted before starting the transmission.
In the SFT = 0 configuration, HDMI-CEC performs automatic SFT calculation ensuring compliance with the HDMI-CEC standard:
This is done to guarantee the maximum priority to a failed transmission and the lowest one to the last initiator that completed successfully its transmission.
Otherwise there is the possibility to configure the SFT bits to count a fixed timing value. Possible values are 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5 data bit periods.
In case of SFTOPT = 0 configuration, SFT starts being counted when the start-of-transmission command is set by software (TXSOM=1).
In case of SFTOPT=1, SFT starts automatically being counted by the HDMI-CEC device when a bus-idle or line error condition is detected. If the SFT timer is completed at the time TXSOM command is set then transmission starts immediately without latency. If the SFT timer is still running instead, the system waits until the timer elapses before transmission can start.
In case of SFTOPT = 1 a bus-event condition starting the SFT timer is detected in the following cases:
If a data bit - excluding the start bit - is considered invalid, the follower is expected to notify such error by generating a low bit period on the CEC line of 1.4 to 1.6 times the nominal data bit period, i.e. 3.6 ms nominally.
| (omitted) |
A message is considered lost and therefore may be retransmitted under the following conditions:
Three kinds of error flag can be detected when the CEC interface is receiving a data bit:
BRE (bit rising error): is set when a bit rising edge is detected outside the windows where it is expected (see Figure 585). BRE flag also generates a CEC interrupt if the BREIE=1.
In the case of a BRE detection, the message reception can be stopped according to the BRESTP bit value and an error bit can be generated if BREGEN bit is set.
When BRE is detected in a broadcast message with BRESTP=1 an error bit is generated even if BREGEN=0 to enforce initiator’s retry of the failed transmission. Error bit generation can be disabled by configuring BREGEN=0, BRDNOGEN=1.
SBPE is set when a bit falling edge is detected earlier than expected (see Figure 585). SBPE flag also generates a CEC interrupt if the SBPEIE=1.
An error bit is always generated on the line in case of a SBPE error detection. An Error Bit is not generated upon SBPE detection only when Listen mode is set (LSTN=1) and the following conditions are met:
LBPE is set when a bit falling edge is not detected in a valid window (see Figure 585). LBPE flag also generates a CEC interrupt if the LBPEIE=1.
LBPE always stops the reception, an error bit is generated on the line when LBPEGEN bit is set.
When LBPE is detected in a broadcast message an error bit is generated even if LBPEGEN=0 to enforce initiator’s retry of the failed transmission. Error bit generation can be disabled by configuring LBPEGEN=0, BRDNOGEN=1.
Note: The BREGEN=1, BRESTP=0 configuration must be avoided
| (omitted) |
| Time | RXTOL | ms | Description |
|---|---|---|---|
| Ts | x | 0 | Bit start event. |
| T1 |
1 | 0.3 | The earliest time for a low - high transition when indicating a logical 1. |
| 0 | 0.4 |
||
| Tn1 | x | 0.6 | The nominal time for a low - high transition when indicating a logical 1. |
| T2 |
0 | 0.8 | The latest time for a low - high transition when indicating a logical 1. |
| 1 | 0.9 |
||
| Tns | x | 1.05 | Nominal sampling time. |
| T3 |
1 | 1.2 | The earliest time a device is permitted return to a high impedance state (logical 0). |
| 0 | 1.3 |
||
| Tn0 | x | 1.5 | The nominal time a device is permitted return to a high impedance state (logical 0). |
| T4 |
0 | 1.7 | The latest time a device is permitted return to a high impedance state (logical 0). |
| 1 | 1.8 |
||
| T5 |
1 | 1.85 |
The earliest time for the start of a following bit. |
| 0 | 2.05 |
||
| Tnf | x | 2.4 | The nominal data bit period. |
| T6 |
0 | 2.75 |
The latest time for the start of a following bit. |
| 1 | 2.95 |
The CEC initiator sets the TXERR flag if detecting low impedance on the CEC line when it is transmitting high impedance and is not expecting a follower asserted bit. TXERR flag also generates a CEC interrupt if the TXERRIE=1.
TXERR assertion stops the message transmission. Application is in charge to retry the failed transmission up to 5 times.
TXERR checks are performed differently depending on the different states of the CEC line and on the RX tolerance configuration.
| (omitted) |
| Time | RXTOL | ms | Description |
|---|---|---|---|
| Ts | x | 0 | Bit start event. |
| T1 |
1 | 0.3 | The earliest time for a low - high transition when indicating a logical 1. |
| 0 | 0.4 |
||
| Tn1 | x | 0.6 | The nominal time for a low - high transition when indicating a logical 1. |
| T2 |
0 | 0.8 | The latest time for a low - high transition when indicating a logical 1. |
| 1 | 0.9 |
||
| Tns | x | 1.05 | Nominal sampling time. |
| T3 |
1 | 1.2 | The earliest time a device is permitted return to a high impedance state (logical 0). |
| 0 | 1.3 |
||
| Tn0 | x | 1.5 | The nominal time a device is permitted return to a high impedance state (logical 0). |
| T4 |
0 | 1.7 | The latest time a device is permitted return to a high impedance state (logical 0). |
| 1 | 1.8 |
||
| T5 |
1 | 1.85 |
The earliest time for the start of a following bit. |
| 0 | 2.05 |
||
| Tnf | x | 2.4 | The nominal data bit period. |
| T6 |
0 | 2.75 |
The latest time for the start of a following bit. |
| 1 | 2.95 |
An interrupt can be produced:
| Interrupt event | Event flag | Enable Control bit |
|---|---|---|
| Rx-Byte Received | RXBR | RXBRIE |
| End of reception | RXEND | RXENDIE |
| Rx-Overrun | RXOVR | RXOVRIE |
| RxBit Rising Error | BRE | BREIE |
| Rx-Short Bit Period Error | SBPE | SBPEIE |
| Rx-Long Bit Period Error | LBPE | LBPEIE |
| Rx-Missing Acknowledge Error | RXACKE | RXACKEIE |
| Arbitration lost | ARBLST | ARBLSTIE |
| Tx-Byte Request | TXBR | TXBRIE |
| End of transmission | TXEND | TXENDIE |
| Tx-Buffer Underrun | TXUDR | TXUDRIE |
| Tx-Error | TXERR | TXERRIE |
| Tx-Missing Acknowledge Error | TXACKE | TXACKEIE |
Refer to Section 1.2 on page 69 for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXE OM |
TXS OM |
CECEN |
| rs | rs | rw |
| Bits 31:3 | Reserved, must be kept at reset value. |
| Bit 2 | TXEOM: Tx End Of Message |
|
The TXEOM bit is set by software to command transmission of the last byte of a CEC message.
TXEOM must be set when CECEN=1.
TXEOM must be set before writing transmission data to TXDR.
If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only |
|
| Bit 1 | TXSOM: Tx Start Of Message |
|
TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
TXSOM must be set when CECEN=1.
TXSOM must be set when transmission data is available into TXDR.
HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from |
|
| Bit 0 | CECEN: CEC enable |
|
The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. |
This register is used to configure the HDMI-CEC controller.
Address offset: 0x04
Reset value: 0x0000 0000
Caution: It is mandatory to write CEC_CFGR only when CECEN=0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LSTN | OAR[14:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | SFT OP |
BRDN OGEN |
LBPE GEN |
BRE GEN |
BRE STP |
RX TOL |
SFT[2:0] |
||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | |||||||
| Bit 31 | LSTN: Listen mode |
|
LSTN bit is set and cleared by software. |
|
| Bits 30:16 | OAR[14:0]: Own addresses configuration |
|
The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. |
|
| Bits 15:9 | Reserved, must be kept at reset value. |
| Bit 8 | SFTOP: SFT Option Bit |
|
The SFTOPT bit is set and cleared by software. |
|
| Bit 7 | BRDNOGEN: Avoid Error-Bit Generation in Broadcast |
|
The BRDNOGEN bit is set and cleared by software. |
|
| Bit 6 | LBPEGEN: Generate Error-Bit on Long Bit Period Error |
|
The LBPEGEN bit is set and cleared by software. If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if |
|
| Bit 5 | BREGEN: Generate Error-Bit on Bit Rising Error |
|
The BREGEN bit is set and cleared by software. If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast |
|
| Bit 4 | BRESTP: Rx-Stop on Bit Rising Error |
|
The BRESTP bit is set and cleared by software. |
|
| Bit 3 | RXTOL: Rx-Tolerance |
|
The RXTOL bit is set and cleared by software.
|
|
| Bits 2:0 | SFT[2:0]: Signal Free Time |
|
SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. ″ 0x0
″ 0x1: 0.5 nominal data bit periods ″ 0x2: 1.5 nominal data bit periods ″ 0x3: 2.5 nominal data bit periods ″ 0x4: 3.5 nominal data bit periods ″ 0x5: 4.5 nominal data bit periods ″ 0x6: 5.5 nominal data bit periods ″ 0x7: 6.5 nominal data bit periods |
Address offset: 0x8
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXD[7:0] |
|||||||
| w | w | w | w | w | w | w | w |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | TXD[7:0]: Tx data |
|
TXD is a write-only register containing the data byte to be transmitted. |
Address offset: 0xC
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RXD[7:0] |
|||||||
| r | r | r | r | r | r | r | r |
||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:0 | RXD[7:0]: Rx data |
|
RXD is read-only and contains the last data byte which has been received from the CEC line. |
Address offset: 0x10
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | TX ACKE |
TX ERR |
TX UDR |
TX END |
TXBR | ARB LST |
RX ACKE |
LBPE | SBPE | BRE | RX OVR |
RX END |
RXBR |
| rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 | rc_w1 |
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bit 12 | TXACKE: Tx-Missing Acknowledge Error |
|
In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. |
|
| Bit 11 | TXERR: Tx-Error |
|
In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. |
|
| Bit 10 | TXUDR: Tx-Buffer Underrun |
|
In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. |
|
| Bit 9 | TXEND: End of Transmission |
|
TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. |
|
| Bit 8 | TXBR: Tx-Byte Request |
|
TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). |
|
| Bit 7 | ARBLST: Arbitration Lost |
|
ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. |
|
| Bit 6 | RXACKE: Rx-Missing Acknowledge |
|
In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. |
|
| Bit 5 | LBPE: Rx-Long Bit Period Error |
|
LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. |
|
| Bit 4 | SBPE: Rx-Short Bit Period Error |
|
SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. |
|
| Bit 3 | BRE: Rx-Bit Rising Error |
|
BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. |
|
| Bit 2 | RXOVR: Rx-Overrun |
|
RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. |
|
| Bit 1 | RXEND: End Of Reception |
|
RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. |
|
| Bit 0 | RXBR: Rx-Byte Received |
|
The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. |
Address offset: 0x14
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | TXACK IE |
TXERR IE |
TX UDRIE |
TXEND IE |
TXBR IE |
ARBLST IE |
RXACK IE |
LBPE IE |
SBPE IE |
BREIE | RXOVR IE |
RXEND IE |
RXBR IE |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:13 | Reserved, must be kept at reset value. |
| Bit 12 | TXACKIE: Tx-Missing Acknowledge Error Interrupt Enable |
|
The TXACKEIE bit is set and cleared by software. |
|
| Bit 11 | TXERRIE: Tx-Error Interrupt Enable |
|
The TXERRIE bit is set and cleared by software. |
|
| Bit 10 | TXUDRIE: Tx-Underrun Interrupt Enable |
|
The TXUDRIE bit is set and cleared by software. |
|
| Bit 9 | TXENDIE: Tx-End Of Message Interrupt Enable |
|
The TXENDIE bit is set and cleared by software. |
|
| Bit 8 | TXBRIE: Tx-Byte Request Interrupt Enable |
|
The TXBRIE bit is set and cleared by software. |
|
| Bit 7 | ARBLSTIE: Arbitration Lost Interrupt Enable |
|
The ARBLSTIE bit is set and cleared by software. |
|
| Bit 6 | RXACKIE: Rx-Missing Acknowledge Error Interrupt Enable |
|
The RXACKIE bit is set and cleared by software. |
|
| Bit 5 | LBPEIE: Long Bit Period Error Interrupt Enable |
|
The LBPEIE bit is set and cleared by software. |
|
| Bit 4 | SBPEIE: Short Bit Period Error Interrupt Enable |
|
The SBPEIE bit is set and cleared by software. |
|
| Bit 3 | BREIE: Bit Rising Error Interrupt Enable |
|
The BREIE bit is set and cleared by software. |
|
| Bit 2 | RXOVRIE: Rx-Buffer Overrun Interrupt Enable |
|
The RXOVRIE bit is set and cleared by software. |
|
| Bit 1 | RXENDIE: End Of Reception Interrupt Enable |
|
The RXENDIE bit is set and cleared by software. |
|
| Bit 0 | RXBRIE: Rx-Byte Received Interrupt Enable |
|
The RXBRIE bit is set and cleared by software. |
Caution: (*) It is mandatory to write CEC_IER only when CECEN=0
The following table summarizes the HDMI-CEC registers.
| Offset | Register name |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 |
CEC_CR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXEOM | TXSOM | CECEN |
| Reset value | 0 | 0 | 0 |
||||||||||||||||||||||||||||||
| 0x04 |
CEC_CFGR
|
LSTN | OAR[14:0] |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | SFTOPT | BRDNOGEN | LBPEGEN | BREGEN | BRESTP | RXTOL | SFT[2:0] |
||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||
| 0x08 |
CEC_TXDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXD[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x0C |
CEC_RXDR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | RXD[7:0] |
|||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||||||||||||||
| 0x10 |
CEC_ISR
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXACKE | TXERR | TXUDR | TXEND | TXBR | ARBLST | RXACKE | LBPE | SBPE | BRE | RXOVR | RXEND | RXBR |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||
| 0x14 |
CEC_IER
|
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TXACKIE | TXERRIE | TXUDRIE | TXENDIE | TXBRIE | ARBLSTIE | RXACKIE | LBPEIE | SBPEIE | BREIE | RXOVRIE | RXENDIE | RXBRIE |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||
Refer to Section 2.2.2 on page 76 for the register boundary addresses.
The STM32F76xxx and STM32F77xxx are built around a Cortex®-M7 with FPU core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined. Once examination is complete, the core and the system may be restored and program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the STM32F76xxx and STM32F77xxx MCUs.
Two interfaces for debug are available:
| (omitted) |
Note: The debug features embedded in the Cortex®-M7 with FPU core are a subset of the Arm®
CoreSight Components Technical Reference Manual.
The Arm® Cortex®-M7 with FPU core provides integrated on-chip debug support. It is comprised of:
It also includes debug features dedicated to the STM32F76xxx and STM32F77xxx:
Note: For further information on debug functionality supported by the Arm® Cortex®-M7 with FPU
core, refer to the Cortex®-M7 with FPU technical reference manual and to the CoreSight
Components Technical Reference Manual (see Section 44.2: Reference Arm®
documentation).
Cortex®-M7 with FPU technical reference manual (TRM)
(see Related documents on page 1)
The core of the STM32F76xxx and STM32F77xxx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an Arm® standard CoreSight debug port that combines a JTAG-DP (5-
pin) interface and a SW-DP (2-pin) interface.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.
| (omitted) |
Figure 588 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins.
This sequence is:
The STM32F76xxx and STM32F77xxx MCUs are available in various packages with different numbers of available pins. As a result, some functionality related to pin availability (TPIU parallel output interface) may differ between packages.
Five pins are used as outputs from the STM32F76xxx and STM32F77xxx for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages.
| SWJ-DP pin name |
JTAG debug port | SW debug port | Pin assign ment |
||
|---|---|---|---|---|---|
| Type | Description | Type | Debug assignment | ||
| JTMS/SWDIO | I | JTAG Test Mode Selection | IO | Serial Wire Data Input/Output | PA13 |
| JTCK/SWCLK | I | JTAG Test Clock | I | Serial Wire Clock | PA14 |
| JTDI | I | JTAG Test Data Input | - | - | PA15 |
| JTDO/TRACESWO | O | JTAG Test Data Output | - | TRACESWO if async trace is enabled | PB3 |
| NJTRST | I | JTAG Test nReset | - | - | PB4 |
After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32F76xxx and STM32F77xxx MCUs offer the possibility of disabling some or all of the SWJ-DP ports and so, of releasing (in gray in the table below) the associated pins for general-purpose IO (GPIO) usage. For more details on how to disable SWJ-DP port pins, please refer to Section 6.3.2: I/O pin alternate function multiplexer and
mapping.
| Available debug ports |
SWJ IO pin assigned |
||||
|---|---|---|---|---|---|
| PA13 / JTMS / SWDIO |
PA14 / JTCK / SWCLK |
PA15 / JTDI |
PB3 / JTDO |
PB4 / NJTRST |
|
| Full SWJ (JTAG-DP + SW-DP) - Reset State | X | X | X | X | X |
| Full SWJ (JTAG-DP + SW-DP) but without NJTRST | X | X | X | X |
|
| JTAG-DP Disabled and SW-DP Enabled | X | X |
|||
| JTAG-DP Disabled and SW-DP Disabled | Released | ||||
Note: When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
GPIO_AFR register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
It is necessary to ensure that the JTAG input pins are not floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on the JTAG input pins:
Once a JTAG IO is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state:
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is
no special recommendation for TCK. However, for JTCK, the device needs an integrated
pull-down.
Having embedded pull-ups and pull-downs removes the need to add external resistors.
To use the serial wire DP to release some GPIOs, the user software must change the GPIO (PA15, PB3 and PB4) configuration mode in the GPIO_MODER register. This releases PA15, PB3 and PB4 which now become available as GPIOs.
When debugging, the host performs the following actions:
Note: For user software designs, note that:
To release the debug pins, remember that they will be first configured either in input-pull-up
(nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after
reset until the instant when the user software releases the pins.
When debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding IO pin
configuration in the IOPORT controller has no effect.
The STM32F76xxx and STM32F77xxx MCUs integrate two serially connected JTAG Debug Ports, the boundary scan Debug Port (IR is 5-bit wide) and the Cortex®-M7 with FPU Debug Port (IR is 4-bit wide).
To access the Debug Port of the Cortex®-M7 with FPU for debug purposes:
Note: Important: Once Serial-Wire is selected using the dedicated Arm® JTAG sequence, the
boundary scan Debug Port is automatically disabled (JTMS forced high).
| (omitted) |
There are several ID codes inside the STM32F76xxx and STM32F77xxx MCUs. ST strongly recommends tools designers to lock their debuggers using the MCU DEVICE ID code located in the external PPB memory map at address 0xE0042000.
The STM32F76xxx and STM32F77xxx MCUs integrate an MCU ID code. This ID identifies the ST MCU part-number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 44.16 on page 1925). This code is accessible using the JTAG debug port (4 to 5 pins) or the SW debug port (two pins) or by the user software. It is even accessible while the MCU is under system reset.
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
DBGMCU_IDCODE
Address: 0xE004 2000
Only 32-bits access supported. Read-only.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REV_ID |
Res. | Res. | Res. | Res. | DEV_ID |
||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r |
||||
| Bits 31:16 | REV_ID[15:0] Revision identifier |
|
This field indicates the revision of the device: |
|
| Bits 15:12 | Reserved, must be kept at reset value. |
| Bits 11:0 | DEV_ID[11:0]: Device identifier |
|
The device ID is 0x451. |
JTAG ID code
The Debug Port of the STM32F76xxx and STM32F77xxx BSC (boundary scan) integrates a JTAG ID code equal to 0x06451041.
The Debug Port of the Arm® Cortex®-M7 with FPU integrates a JTAG ID code. This ID code is the Arm® default one and has not been modified. This code is only accessible by the JTAG Debug Port.
This code is 0x5BA00477 (corresponds to Cortex®-M7 with FPU, see Section 44.2:
Reference Arm® documentation).
The Arm® Cortex®-M7 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB ROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two pins) or by the user software.
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five data registers (for full details, refer to the Cortex®-M7 with FPU technical reference manual
(TRM), for references, please see Section 44.2: Reference Arm® documentation).
| IR(3:0) | Data register | Details |
|---|---|---|
| 1111 |
BYPASS [1 bit] |
- |
| 1110 |
IDCODE [32 bits] |
ID CODE 0x06451041 (Arm® Cortex®-M7 with FPU ID Code) |
| 1010 |
DPACC [35 bits] |
Debug port access register This initiates a debug port and allows access to a debug port register.
Refer to Table 319 for a description of the A(3:2) bits |
| 1011 |
APACC [35 bits] |
Access port access register Initiates an access port and allows access to an access port register.
There are many AP Registers (see AHB-AP) addressed as the combination of:
|
| 1000 |
ABORT [35 bits] |
Abort register
|
| Address | A(3:2) value | Description |
|---|---|---|
| 0x0 | 00 | Reserved, must be kept at reset value. |
| 0x4 | 01 |
DP CTRL/STAT register. Used to:
|
| 0x8 | 10 |
DP SELECT register: Used to select the current access port and the active 4-words register window.
|
| 0xC | 11 |
DP RDBUFF register: Used to allow the debugger to get the final result after a sequence of operations (without requesting new JTAG-DP operation) |
This synchronous serial protocol uses two pins:
The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm®).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted where the line is not driven by the host nor the target. By default, this turnaround time is one bit time, however this can be adjusted by configuring the SWCLK frequency.
Each sequence consist of three phases:
| Bit | Name | Description |
|---|---|---|
| 0 | Start | Must be “1” |
| 1 | APnDP |
0: DP Access 1: AP Access |
| 2 | RnW |
0: Write Request 1: Read Request |
| 4:3 | A(3:2) | Address field of the DP or AP registers (refer to Table 319) |
| 5 | Parity | Single bit parity of preceding bits |
| 6 | Stop | 0 |
| 7 | Park | Not driven by the host. Must be read as “1” by the target because of the pull-up |
Refer to the Cortex®-M7 with FPU TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target drive the line.
| Bit | Name | Description |
|---|---|---|
| 0..2 | ACK |
001: FAULT 010: WAIT 100: OK |
The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received.
| Bit | Name | Description |
|---|---|---|
| 0..31 | WDATA or RDATA | Write or Read data |
| 32 | Parity | Single parity of the 32 data bits |
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It follows the JEP-106 standard. This ID code is the default Arm® one and is set to 0x5BA02477 (corresponding to Cortex®-M7 with FPU).
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
Further details of the SW-DP state machine can be found in the Cortex®-M7 with FPU TRM
and the CoreSight Components Technical Reference Manual.
Access to these registers are initiated when APnDP=0
| A(3:2) | R/W |
CTRLSEL bit of SELECT register |
Register | Notes |
|---|---|---|---|---|
| 00 | Read | - | IDCODE | The manufacturer code is not set to ST code. 0x5BA02477 (identifies the SW-DP) |
| 00 | Write | - | ABORT | - |
| 01 | Read/Write | 0 | DP- CTRL/STAT |
Purpose is to:
|
| 01 | Read/Write | 1 | WIRE CONTROL |
Purpose is to configure the physical serial port protocol (like the duration of the turnaround time) |
| 10 | Read | - | READ RESEND |
Enables recovery of the read data from a corrupted debugger transfer, without repeating the original AP transfer. |
| 10 | Write | - | SELECT | The purpose is to select the current access port and the active 4-words register window |
| 11 | Read/Write | - | READ BUFFER |
This read buffer is useful because AP accesses are posted (the result of a read AP request is available on the next AP transaction). This read buffer captures data from the AP, presented as the result of a previous read, without initiating a new transaction |
Access to these registers are initiated when APnDP=1
There are many AP Registers (see AHB-AP) addressed as the combination of:
Features:
The address of the 32-bits AHP-AP registers are 6-bits wide (up to 64 words or 256 bytes) and consists of:
The AHB-AP of the Cortex®-M7 with FPU includes 9 x 32-bits registers:
| Address offset | Register name | Notes |
|---|---|---|
| 0x00 | AHB-AP Control and Status Word |
Configures and controls transfers through the AHB interface (size, hprot, status on current transfer, address increment type |
| 0x04 | AHB-AP Transfer Address | - |
| 0x0C | AHB-AP Data Read/Write | - |
| 0x10 | AHB-AP Banked Data 0 | Directly maps the 4 aligned data words without rewriting the Transfer Address Register. |
| 0x14 | AHB-AP Banked Data 1 | |
| 0x18 | AHB-AP Banked Data 2 | |
| 0x1C | AHB-AP Banked Data 3 | |
| 0xF8 | AHB-AP Debug ROM Address | Base Address of the debug interface |
| 0xFC | AHB-AP ID Register | - |
Refer to the Cortex®-M7 with FPU TRM for further details.
Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can access these registers directly over the internal Private Peripheral Bus (PPB).
It consists of 4 registers:
| Register | Description |
|---|---|
| DHCSR |
The 32-bit Debug Halting Control and Status Register This provides status information about the state of the processor enable core debug halt and step the processor |
| DCRSR |
The 17-bit Debug Core Register Selector Register: This selects the processor register to transfer data to or from. |
| DCRDR |
The 32-bit Debug Core Register Data Register: This holds data for reading and writing registers to and from the processor selected by the DCRSR (Selector) register. |
| DEMCR |
The 32-bit Debug Exception and Monitor Control Register: This provides Vector Catching and Debug Monitor Control. This register contains a bit named TRCENA which enable the use of a TRACE. |
Note: Important: these registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Cortex®-M7 with FPU TRM for further details.
To Halt on reset, it is necessary to:
The reset system of the STM32F76xxx and STM32F77xxx MCU comprises the following reset sources:
The Cortex®-M7 with FPU differentiates the reset of the debug part (generally PORRESETn) and the other one (SYSRESETn)
This way, it is possible for the debugger to connect under System Reset, programming the Core Debug Registers to halt the core when fetching the reset vector. Then the host can release the system reset and the core will immediately halt without having executed any instructions. In addition, it is possible to program any debug features under System Reset.
Note: It is highly recommended for the debugger host to connect (set a breakpoint in the reset
vector) under system reset.
Typically in Cortex-M architecture the FPB unit allows to:
Where the use of a Software Patch or a Hardware Breakpoint is exclusive.
But there are some major changes in Cortex®-M7 FPB:
The DWT unit consists of four comparators. They are configurable as:
The DWT also provides some means to give some profiling informations. For this, some counters are accessible to give the number of:
The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated as:
The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete packets sequence to the debugger host.
The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM.
Time stamp packets encode time stamp information, generic control and synchronization. It uses a 21-bit timestamp counter (with possible prescalers) which is reset at each time stamp packet emission. This counter can be either clocked by the CPU clock or the SWV clock.
A synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is emitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first).
A synchronization packet is a timestamp packet control. It is emitted at each DWT trigger.
For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control Register must be set.
Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which
will send only TPIU synchronization packets and not ITM synchronization packets.
An overflow packet consists is a special timestamp packets which indicates that data has been written but the FIFO was full.
| Address | Register | Details |
|---|---|---|
| @E0000FB0 | ITM lock access | Write 0xC5ACCE55 to unlock Write Access to the other ITM registers |
| @E0000E80 | ITM trace control |
Bits 31-24 = Always 0 |
|
= Busy |
||
| Bits 22-16 = 7-bits ATB ID which identifies the source of the trace data. |
||
| Bits 15-10 = Always 0 |
||
|
= TSPrescale = Time Stamp Prescaler |
||
| Bits 7-5 = Reserved |
||
|
= SWOENA = Enable SWV behavior (to clock the |
||
|
= DWTENA: Enable the DWT Stimulus |
||
| emit the synchronization packets. = SYNCENA: this bit must be to 1 to enable the DWT to |
||
|
= TSENA (Timestamp Enable) |
||
|
= ITMENA: Global Enable Bit of the ITM |
||
| @E0000E40 | ITM trace privilege |
mask to enable tracing ports31:24 |
|
mask to enable tracing ports23:16 |
||
|
mask to enable tracing ports15:8 |
||
|
mask to enable tracing ports7:0 |
||
| @E0000E00 | ITM trace enable | Each bit enables the corresponding Stimulus port to generate trace. |
| @E0000000- E000007C |
Stimulus port registers 0-31 |
Write the 32-bits data on the selected Stimulus Port (32 available) to be traced out. |
Example of configuration
To output a simple value to the TPIU:
The ETM enables the reconstruction of program execution. Data are traced using the Data Watchpoint and Trace (DWT) component or the Instruction Trace Macrocell (ITM) whereas instructions are traced using the Embedded Trace Macrocell (ETM).
The ETM transmits information as packets and is triggered by embedded resources. These resources must be programmed independently and the trigger source is selected using the Trigger Event Register (0xE0041008). An event could be a simple event (address match from an address comparator) or a logic equation between 2 events. The trigger source is one of the fourth comparators of the DWT module, The following events can be monitored:
For more informations on the trigger resources refer to Section 44.13: DWT (data
watchpoint trigger).
The packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit). The formatter of the TPIU adds some extra packets (refer to Section 44.17: Pelican TPIU (trace
port interface unit)) and then outputs the complete packet sequence to the debugger host.
Note: N.B: Cortex-M7 ETM is compliant with Arm ETM architecture v4, which programming model
is not backward compatible with Cortex-M4 ETM one (ETM architecture v3.5).
This part is described in the chapter 6 ETM v4 architecture specification (IHI0064B).
For more information on registers refer to the Pelican ETM technical reference manual (DDI0494-2a) and the ETM v4 architecture specification (IHI0064B).
To output a simple value to the TPIU:
ETM:
The MCU debug component helps the debugger provide support for:
To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior:
During a breakpoint, it is necessary to choose how the counter of timers and watchdog should behave:
For the bxCAN, the user can choose to block the update of the receive register during a breakpoint.
For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.
This register allows the configuration of the MCU under DEBUG. This concerns:
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software to write to these registers.
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
TRACE_ MODE [1:0] |
TRACE _CLKIN EN |
Res. | Res. |
DBG_ STAND BY |
DBG_ STOP |
DBG_ SLEEP |
|
| rw | rw | rw | rw | rw | rw | ||||||||||||||||||||||||||
| Bits 31:8 | Reserved, must be kept at reset value. |
| Bits 7:5 | TRACE_MODE[1:0] and TRACE_CLKINEN: Trace clock and pin assignment control |
|
|
| Bits 4:3 | Reserved, must be kept at reset value. |
| Bit 2 | DBG_STANDBY: Debug Standby mode |
|
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. |
|
| Bit 1 | DBG_STOP: Debug Stop mode |
|
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. |
|
| Bit 0 | DBG_SLEEP: Debug Sleep mode |
|
0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled. |
The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns APB2 peripherals. It is mapped on the external PPB bus at address 0xE004 2008
It is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.
Address: 0xE004 2008
Only 32-bit access is supported.
Power-on-reset (POR): 0x0000 0000 (not reset by system reset)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. |
DBG_CAN2_STOP | DBG_CAN1_STOP | DBG_I2C4_SMBUS_TIMEOUT | DBG_I2C3_SMBUS_TIMEOUT | DBG_I2C2_SMBUS_TIMEOUT | DBG_I2C1_SMBUS_TIMEOUT | Res. | Res. | Res. | Res. | Res. |
Res. | Res. |
DBG_CAN3_STOP | DBG_IWDG_STOP | DBG_WWDG_STOP | DBG_RTC_STOP | DBG_LPTIM1_STOP | DBG_TIM14_STOP | DBG_TIM13_STOP | DBG_TIM12_STOP | DBG_TIM7_STOP | DBG_TIM6_STOP | DBG_TIM5_STOP | DBG_TIM4_STOP | DBG_TIM3_STOP | DBG_TIM2_STOP |
| rw | rw | rw | rw | rw | rw |
rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| Bits 31:27 | Reserved, must be kept at reset value. |
| Bit 26 | DBG_CAN2_STOP: Debug CAN2 stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 25 | DBG_CAN1_STOP: Debug CAN2 stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 24 | DBG_I2C4_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 23 | DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 22 | DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 21 | DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bits 20:14 | Reserved, must be kept at reset value. |
| Bit 13 | DBG_CAN3_STOP: Debug CAN3 stopped when Core is halted |
|
0: Same behavior as in normal mode |
|
| Bit 12 | DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted |
|
0: The independent watchdog counter clock continues even if the core is halted |
|
| Bit 11 | DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted |
|
0: The window watchdog counter clock continues even if the core is halted |
|
| Bit 10 | DBG_RTC_STOP: RTC stopped when Core is halted |
|
0: The RTC counter clock continues even if the core is halted |
|
| Bit 9 | DBG_LPTIM1_STOP: LPTMI1 counter stopped when core is halted |
|
0: The clock of LPTIM1 counter is fed even if the core is halted |
|
| Bits 8:0 | DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=2..7, 12..14) |
|
0: The clock of the involved Timer Counter is fed even if the core is halted |
The DBGMCU_APB2_FZ register is used to configure the MCU under Debug. It concerns APB2 peripherals.
This register is mapped on the external PPB bus at address 0xE004 200C
It is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.
Address: 0xE004 200C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG_TIM11 _STOP |
DBG_TIM10 _STOP |
DBG_TIM9_ STOP |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG_TIM8_ STOP |
DBG_TIM1_ STOP |
| rw | rw | rw |
rw | rw |
| Bits 31:19 | Reserved, must be kept at reset value. |
| Bits 18:16 | DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..11) |
|
0: The clock of the involved Timer Counter is fed even if the core is halted |
|
| Bits 15:2 | Reserved, must be kept at reset value. |
| Bit 1 | DBG_TIM8_STOP: TIM8 counter stopped when core is halted |
|
0: The clock of the involved Timer Counter is fed even if the core is halted |
|
| Bit 0 | DBG_TIM1_STOP: TIM1 counter stopped when core is halted |
|
0: The clock of the involved Timer Counter is fed even if the core is halted |
The TPIU acts as a bridge between the on-chip trace data from the ITM, the ETM and the external trace capture device.
The output data stream encapsulates the trace source ID, that is then captured by a trace
port analyzer (TPA).
The core embeds a simple TPIU, especially designed for low-cost debug (consisting of a special version of the CoreSight TPIU).
| (omitted) |
Asynchronous mode
The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode).
| TPIU pin name |
Trace synchronous mode |
|
|---|---|---|
| Type | Description |
|
| TRACESWO | O | TRACE Async Data Output |
Synchronous mode
The synchronous mode requires from 2 to 6 extra pins depending on the data trace size and is only available in the larger packages. In addition it is available in JTAG mode and in Serial Wire mode and provides better bandwidth output capabilities than asynchronous trace.
| TPIU pin name |
Trace synchronous mode |
|
|---|---|---|
| Type | Description |
|
| TRACECK | O | TRACE Clock |
| TRACED[3:0] | O |
TRACE Sync Data Outputs Can be 1, 2 or 4. |
TPIU TRACE pin assignment
By default, these pins are NOT assigned. They can be assigned by setting the TRACE_CLKINEN and TRACE_MODE bits in the MCU Debug component configuration
register. This configuration has to be done by the debugger host.
In addition, the number of pins to assign depends on the trace configuration (asynchronous or synchronous).
To assign the TRACE pin, the debugger host must program the bits TRACE_CLKINEN and TRACE_MODE[1:0] of the Debug MCU configuration register (DBGMCU_CR). By default the TRACE pins are not assigned.
This register is mapped on the external PPB and is reset by the PORESET (and not by the SYSTEM reset). It can be written by the debugger under SYSTEM reset.
| DBGMCU_CR register |
Pins assigned for: |
TRACE IO pin assigned |
||||||
|---|---|---|---|---|---|---|---|---|
| TRAC E_CL KINEN |
TRACE _MODE [1:0] |
JTDO/ TRACESWO | TRACECK | TRACED[0] | TRACED[1] | TRACED[2] | TRACED[3] |
|
| 0 | XX | No Trace (default state) | Released (1) | - |
||||
| 1 | 00 | Asynchronous Trace | TRACESWO | - | - | Released (usable as GPIO) |
||
| 1 | different of 00 |
Synchronous Trace 1 bit(2) |
Released (1) |
TRACECK | TRACED[0] | - | - | - |
| 1 | different of 00 |
Synchronous Trace 2 bit(2) | TRACECK | TRACED[0] | TRACED[1] | - | - |
|
| 1 | different of 00 |
Synchronous Trace 4 bit(2) | TRACECK | TRACED[0] | TRACED[1] | TRACED[2] | TRACED[3] |
|
Selected with Bit[3:0] Current port size from TPIU register.
By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_CLKINEN has been set.
The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the
SPP_R (Selected Pin Protocol) register of the TPIU.
It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R (Current Sync Port Size Register) of the TPIU:
The purpose of this formatter is to build 128 bit frames containing trace data from, potentially, both the ETM and the ITM, and to allow at a trace analyzer level a correlation between trace packets and emitters.
The formatter protocol outputs data in 16-byte frames:
Note: Refer to the Arm® CoreSight Architecture Specification v1.0 (Arm® IHI 0029B) for further
information
The TPIU can generate two types of synchronization packets:
The Frame Synchronization packet (or Full Word Synchronization packet)
It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not occur at any other time provided that the ID source code 0x7F has not been used.
It is output periodically between frames.
In continuous mode, the TPA must discard all these frames once a synchronization frame has been found.
The Half-Word Synchronization packet
It consists of the half word: 0x7F_FF (LSB emitted first).
It is output periodically between or within frames.
These packets are only generated in continuous mode and enable the TPA to detect that the TRACE port is in IDLE mode (no TRACE to be captured). When detected by the TPA, it must be discarded.
There is no Synchronization Counter register implemented in the TPIU of the core. Consequently, the synchronization trigger can only be generated by the DWT. Refer to the registers DWT Control Register (bits SYNCTAP[11:10]) and the DWT Current PC Sampler Cycle Count Register.
The TPIU Frame synchronization packet (0x7F_FF_FF_FF) is emitted:
TRACE_CLKINEN bit in the DBGMCU_CFG register is set. In this case, the word 0x7F_FF_FF_FF is not followed by any formatted packet.
The trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0)
The output clock is output to the debugger (TRACECK)
Here, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is used.
Note: In this synchronous mode, it is not required to provide a stable clock frequency.
The TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal to HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2.
This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO. Obviously there is a limited bandwidth.
Single IO trace mode is typically suitable for ITM trace output. Also, formatter is disabled in case of asynchronous trace, so merging of ETM and ITM trace streams is not possible.
TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this functionality is available in all STM32F76xxx and STM32F77xxx packages.
This asynchronous mode requires a constant frequency for TRACECLKIN. For the standard UART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded version is tolerant up to 10%.
In the STM32F76xxx and STM32F77xxx, this TRACECLKIN input is internally connected to HCLK. This means that when in asynchronous trace mode, the application is restricted to use time frames where the CPU frequency is stable.
Note: Important: when using asynchronous trace: it is important to be aware that:
The default clock of the STM32F76xxx and STM32F77xxx MCUs is the internal RC
oscillator. Its frequency under reset is different from the one after reset release. This is
because the RC calibration is the default one under system reset and is updated at each
system reset release.
Consequently, the trace port analyzer (TPA) should not enable the trace (with the
TRACE_CLKINEN bit) under system reset, because a Synchronization Frame Packet will
be issued with a different bit time than trace packets which will be transmitted after reset
release.
The TPIU APB registers can be read and written only if the bit TRCENA of the Debug Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read as zero (the output of this bit enables the PCLK of the TPIU).
| Address | Register | Description |
|---|---|---|
| 0xE0040004 | Current port size |
Allows the trace port size to be selected: Port size = 1 Port size = 2 Port size = 3, not supported Port Size = 4 Only 1 bit must be set. By default, the port size is one bit. (0x00000001) |
| 0xE00400F0 | Selected pin protocol |
Allows the Trace Port Protocol to be selected: Bit1:0= 00: Sync Trace Port Mode |
| 0xE0040304 | Formatter and flush control |
Bits 31-9 = always ‘0 = TrigIn = always ‘1 to indicate that triggers are indicated Bits 3-2 = always 0 = EnFCont. In Sync Trace mode (Select_Pin_Protocol register continuous mode. In asynchronous mode (Select_Pin_Protocol register bit1:0 <> 00), this bit can be written to activate or not the formatter. = always 0 The resulting default value is 0x102 Note: In synchronous mode, because the TRACECTL pin is not mapped outside the chip, the formatter is always enabled in continuous mode -this way the formatter inserts some control packets to identify the source of the trace packets). |
| 0xE0040300 | Formatter and flush status | Not used in Cortex®-M7 with FPU, always read as 0x00000008 |
The following table summarizes the Debug registers.
| Addr. | Register |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0xE004 2000 |
DBGMCU _IDCODE |
REV_ID |
Res. | Res. | Res. | Res. | DEV_ID |
||||||||||||||||||||||||||
| Reset value(1) | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
|||||
| 0xE004 2004 |
DBGMCU_CR
|
Res. | Res. | Res. | Res. | Res. | Res.. | Res. | Res. | Res. | Res. | Res. | DBG_TIM7_STOP | DBG_TIM6_STOP | DBG_TIM5_STOP | DBG_TIM8_STOP | DBG_I2C2_SMBUS_TIMEOUT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TMR[1OA:CD0]EE_ | TRACE_ | Res. | Res. | DBG_STANDBY | DBG_STOP | DBG_SLEEP | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||
| 0xE004 2008 |
DBGMCU_ APB1_FZ |
Res. | Res. | Res. | Res. | Res. | DBG_CAN2_STOP | DBG_CAN1_STOP | DBG_I2C4_SMBUS_TIMEOUT | DBG_I2C3_SMBUS_TIMEOUT | DBG_I2C2_SMBUS_TIMEOUT | DBG_I2C1_SMBUS_TIMEOUT | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG_CAN3_STOP | DBG_IWDG_STOP | DBG_WWDG_STOP | DBG_LPTIM1_STOP | DBG_RTC_STOP | DBG_TIM14_STOP | DBG_TIM13_STOP | DBG_TIM12_STOP | DBG_TIM7_STOP | DBG_TIM6_STOP | DBG_TIM5_STOP | DBG_TIM4_STOP | DBG_TIM3_STOP | DBG_TIM2_STOP |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|||||||||||||
| 0xE004 200C |
DBGMCU_ APB2_FZ |
Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG_TIM11_STOP | DBG_TIM10_STOP | DBG_TIM9_STOP | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG_TIM8_STOP | DBG_TIM1_STOP |
| Reset value | 0 | 0 | 0 | 0 | 0 |
||||||||||||||||||||||||||||
The electronic signature is stored in the Flash memory area. It can be read using the JTAG/SWD or the CPU. It contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the STM32F76xxx and STM32F77xxx microcontrollers.
The unique device identifier is ideally suited:
The 96-bit unique device identifier provides a reference number which is unique for any device and in any context. These bits can never be altered by the user.
The 96-bit unique device identifier can also be read in single bytes/half-words/words in different ways and then be concatenated using a custom algorithm.
Base address: 0x1FF0 F420
Address offset: 0x00
Read only = 0xXXXX XXXX where X is factory-programmed
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| U_ID[31:0] |
|||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | U_ID[31:0]: 31:0 unique ID bits |
Address offset: 0x04
Read only = 0xXXXX XXXX where X is factory-programmed
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| U_ID[63:48] |
U_ID[47:32] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 | U_ID[63:32]: 63:32 unique ID bits |
Address offset: 0x08
Read only = 0xXXXX XXXX where X is factory-programmed
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| U_ID[95:80] |
U_ID[79:64] |
||||||||||||||||||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 31:0 |
U_ID[95:64]:
95:64 Unique ID bits.
|
Base address: 0x1FF0 F442
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| F_SIZE |
|||||||||||||||
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
| Bits 15:0 | F_ID[15:0]: Flash memory size |
|
This bitfield indicates the size of the device Flash memory expressed in Kbytes. |
Base address: 0x1FFF 7BF0
Address offset: 0x00
Read only = 0xXXXX where X is factory-programmed
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | PKG[2:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
||
| rw | rw | rw |
|||||||||||||
| Bits 15:11 | Reserved, must be kept at reset value. |
| Bits 10:8 | PGK[2:0]: Package type |
|
0x111: STM32F767 and STM32F777 LQFP208 and TFBGA216 package |
|
| Bits 7:0 | Reserved, must be kept at reset value. |
| Date | Revision | Changes |
|---|---|---|
| 02-Feb-2016 | 1 | Initial release. |
| 24-Apr-2016 | 2 |
Updated RTC section:
Updated LDC-TFT section:
Updated HASH section:
Updated FMC section:
Updated DMA section:
Updated RCC section:
|
| 24-Apr-2016 | 2 (continued) |
Updated TIMER section:
Updated I2C2 section:
Updated system configuration:
Updated DFSDM section:
Changed DFSDM into DFSDM1:
|
| 24-Apr-2016 | 2 (continued) |
Updated USART section:
Updated Power Controller (PWR) section:
Updated Flash memory section:
Updated system configuration controller section:
|
| 08-Nov-2017 | 3 |
Updated RCC section:
Updated Section 5.3.25: RCC dedicated clocks configuration Update Section 5.3.21: RCC clock control & status register Updated Figure 13: Clock tree OTG_HS_SCL renamed by OTG_HS_ULPI_CK and the SYSCLK, Cortex core and HCLK clocks advertised as 216 MHz max. Updated Section 5.3.2: RCC PLL configuration register Updated Section 5.3.27: RCC register map PADRSTF in PINRSTF. Updated Section 5.3.20: RCC backup domain control register Updated Section 5.3.14: RCC APB2 peripheral clock enable register Updated Section 5.3.3: RCC clock configuration register
Updated PWR section:
Updated Section 4.1.5: Battery backup domain note removing ‘only one I/O at a time can be used as an output’ sentence. Updated Section 4.4.2: PWR power control/status register
Updated LTDC section:
Updated Section 19: LCD-TFT display controller (LTDC) which must apply to the whole STM32F756xx and STM32F77xxx devices.
Updated SYSCFG section:
Updated Section 7.2.6: SYSCFG external interrupt configuration
Updated Flash memory section:
Updated Section 3.4.1: Option bytes description:
Updated Section 3.7.7: Flash option control register
Updated Section 3.7.6: Flash option control register Updated Section 3.7.7: Flash option control register |
| 08-Nov-2017 | 3 (continued) |
Updated CRYPT section:
Updated Section 23: Cryptographic processor (CRYP) which must apply to the whole STM32F77xxx devices.
Updated HASH section:
Updated Section 24: Hash processor (HASH) which must apply to the whole STM32F77xxx devices.
Updated QUAD-SPI section:
Updated Section 14.3.5: QUADSPI indirect mode ‘FIFO and data management’ last paragraph for a 32-byte FIFO.
Updated I2C2 section:
Updated Section 33.4.9: I2C_TIMINGR register configuration
Updated general-purpose timer section:
Updated Section : SDRAM Control registers 1,2 (FMC_SDCR1,2) Bits [1:0] ‘01’ description for SPDIFRX_FRAME_SYNC’.
Updated DFSDM section:
Updated JEXTSEL bit description in Section 17.8.1: DFSDM filter x
Updated FMC section:
Updated Section : SDRAM Control registers 1,2 (FMC_SDCR1,2)
Updated USB section:
Updated Section 41.15.38: OTG all endpoints interrupt mask
Updated RTC section:
Updated Figure 348: RTC block diagram WUCKSEL dividers for /2,4,8,16.
Updated ETHERNET section:
Updated Section : Ethernet MAC MII address register
Updated USART section:
Updated USART configuration version 1.3. |
| 16-Mar-2018 | 4 |
Documentation conventions section:
Added Section 1.1: General information with Arm logo
USB section:
Memory organization section
Added Figure 2: Memory map.
PWR section:
Updated Section 4.1.5: Battery backup domain note removing ‘only one I/O at a time can be used as an output’ sentence. Updated Section 4.4.2: PWR power control/status register
SDMMC section:
Updated Section 39.8.8: SDMMC data length register
RTC section:
Updated Section 32.6.3: RTC control register (RTC_CR) WUTE bit description adding note.
I2C2 section:
Updated Figure 351: Setup and hold timings.
DSI Host (DSI) section:
Updated Section 20: DSI Host (DSI).
DEBUG section:
Updated Section 44.6.1: MCU device ID code REV_ID[15:0] bit description adding revZ.
RCC section:
Updated Figure 13: Clock tree note 2 replacing by ‘RCC_DCKCFGR1’ register. Updated Section 5.3.25: RCC dedicated clocks configuration Updated Section 5.3.26: RCC dedicated clocks configuration |
|
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